* Denali NAND controller

Required properties:
  - compatible : should be one of the following:
      "altr,socfpga-denali-nand"            - for Altera SOCFPGA
      "socionext,uniphier-denali-nand-v5a"  - for Socionext UniPhier (v5a)
      "socionext,uniphier-denali-nand-v5b"  - for Socionext UniPhier (v5b)
  - reg : should contain registers location and length for data and reg.
  - reg-names: Should contain the reg names "nand_data" and "denali_reg"
  - #address-cells: should be 1. The cell encodes the chip select connection.
  - #size-cells : should be 0.
  - interrupts : The interrupt number.
  - clocks: should contain phandle of the controller core clock, the bus
    interface clock, and the ECC circuit clock.
  - clock-names: should contain "nand", "nand_x", "ecc"

Optional properties:
  - resets: may contain phandles to the controller core reset, the register
    reset
  - reset-names: may contain "nand", "reg"

Sub-nodes:
  Sub-nodes represent available NAND chips.

  Required properties:
    - reg: should contain the bank ID of the controller to which each chip
      select is connected.

  Optional properties:
    - nand-ecc-step-size: see nand-controller.yaml for details.
      If present, the value must be
        512        for "altr,socfpga-denali-nand"
        1024       for "socionext,uniphier-denali-nand-v5a"
        1024       for "socionext,uniphier-denali-nand-v5b"
    - nand-ecc-strength: see nand-controller.yaml for details. Valid values are:
        8, 15      for "altr,socfpga-denali-nand"
        8, 16, 24  for "socionext,uniphier-denali-nand-v5a"
        8, 16      for "socionext,uniphier-denali-nand-v5b"
    - nand-ecc-maximize: see nand-controller.yaml for details

The chip nodes may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.

Examples:

nand: nand@ff900000 {
	#address-cells = <1>;
	#size-cells = <0>;
	compatible = "altr,socfpga-denali-nand";
	reg = <0xff900000 0x20>, <0xffb80000 0x1000>;
	reg-names = "nand_data", "denali_reg";
	clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
	clock-names = "nand", "nand_x", "ecc";
	resets = <&nand_rst>, <&nand_reg_rst>;
	reset-names = "nand", "reg";
	interrupts = <0 144 4>;

	nand@0 {
		reg = <0>;
	}
};
