Qualcomm QMP PHY controller
===========================

QMP phy controller supports physical layer functionality for a number of
controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.

Required properties:
 - compatible: compatible list, contains:
	       "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
	       "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
	       "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
	       "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
	       "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845.

 - reg:
   - For "qcom,sdm845-qmp-usb3-phy":
     - index 0: address and length of register set for PHY's common serdes
       block.
     - named register "dp_com" (using reg-names): address and length of the
       DP_COM control block.
   - For all others:
     - offset and length of register set for PHY's common serdes block.

 - #clock-cells: must be 1
    - Phy pll outputs a bunch of clocks for Tx, Rx and Pipe
      interface (for pipe based PHYs). These clock are then gate-controlled
      by gcc.
 - #address-cells: must be 1
 - #size-cells: must be 1
 - ranges: must be present

 - clocks: a list of phandles and clock-specifier pairs,
	   one for each entry in clock-names.
 - clock-names: "cfg_ahb" for phy config clock,
		"aux" for phy aux clock,
		"ref" for 19.2 MHz ref clk,
		"com_aux" for phy common block aux clock,
		For "qcom,msm8996-qmp-pcie-phy" must contain:
			"aux", "cfg_ahb", "ref".
		For "qcom,msm8996-qmp-usb3-phy" must contain:
			"aux", "cfg_ahb", "ref".
		For "qcom,qmp-v3-usb3-phy" must contain:
			"aux", "cfg_ahb", "ref", "com_aux".

 - resets: a list of phandles and reset controller specifier pairs,
	   one for each entry in reset-names.
 - reset-names: "phy" for reset of phy block,
		"common" for phy common block reset,
		"cfg" for phy's ahb cfg block reset (Optional).
		For "qcom,msm8996-qmp-pcie-phy" must contain:
		 "phy", "common", "cfg".
		For "qcom,msm8996-qmp-usb3-phy" must contain
		 "phy", "common".
		For "qcom,ipq8074-qmp-pcie-phy" must contain:
		 "phy", "common".

 - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
 - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.

Optional properties:
 - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
			pll block.

Required nodes:
 - Each device node of QMP phy is required to have as many child nodes as
   the number of lanes the PHY has.

Required properties for child node:
 - reg: list of offset and length pairs of register sets for PHY blocks -
	- index 0: tx
	- index 1: rx
	- index 2: pcs
	- index 3: pcs_misc (optional)

 - #phy-cells: must be 0

 - clocks: a list of phandles and clock-specifier pairs,
	   one for each entry in clock-names.
 - clock-names: Must contain following for pcie and usb qmp phys:
		 "pipe<lane-number>" for pipe clock specific to each lane.
 - clock-output-names: Name of the PHY clock that will be the parent for
		       the above pipe clock.

	For "qcom,ipq8074-qmp-pcie-phy":
		- "pcie20_phy0_pipe_clk"	Pipe Clock parent
			(or)
		  "pcie20_phy1_pipe_clk"

 - resets: a list of phandles and reset controller specifier pairs,
	   one for each entry in reset-names.
 - reset-names: Must contain following for pcie qmp phys:
		 "lane<lane-number>" for reset specific to each lane.

Example:
	phy@34000 {
		compatible = "qcom,msm8996-qmp-pcie-phy";
		reg = <0x34000 0x488>;
		#clock-cells = <1>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
			<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
			<&gcc GCC_PCIE_CLKREF_CLK>;
		clock-names = "aux", "cfg_ahb", "ref";

		vdda-phy-supply = <&pm8994_l28>;
		vdda-pll-supply = <&pm8994_l12>;

		resets = <&gcc GCC_PCIE_PHY_BCR>,
			<&gcc GCC_PCIE_PHY_COM_BCR>,
			<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
		reset-names = "phy", "common", "cfg";

		pciephy_0: lane@35000 {
			reg = <0x35000 0x130>,
				<0x35200 0x200>,
				<0x35400 0x1dc>;
			#phy-cells = <0>;

			clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
			clock-names = "pipe0";
			clock-output-names = "pcie_0_pipe_clk_src";
			resets = <&gcc GCC_PCIE_0_PHY_BCR>;
			reset-names = "lane0";
		};

		pciephy_1: lane@36000 {
		...
		...
	};
