Amlogic Meson SPI controllers

* SPIFC (SPI Flash Controller)

The Meson SPIFC is a controller optimized for communication with SPI
NOR memories, without DMA support and a 64-byte unified transmit /
receive buffer.

Required properties:
 - compatible: should be "amlogic,meson6-spifc" or "amlogic,meson-gxbb-spifc"
 - reg: physical base address and length of the controller registers
 - clocks: phandle of the input clock for the baud rate generator
 - #address-cells: should be 1
 - #size-cells: should be 0

	spi@c1108c80 {
		compatible = "amlogic,meson6-spifc";
		reg = <0xc1108c80 0x80>;
		clocks = <&clk81>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

* SPICC (SPI Communication Controller)

The Meson SPICC is generic SPI controller for general purpose Full-Duplex
communications with dedicated 16 words RX/TX PIO FIFOs.

Required properties:
 - compatible: should be "amlogic,meson-gx-spicc" on Amlogic GX SoCs.
 - reg: physical base address and length of the controller registers
 - interrupts: The interrupt specifier
 - clock-names: Must contain "core"
 - clocks: phandle of the input clock for the baud rate generator
 - #address-cells: should be 1
 - #size-cells: should be 0

Optional properties:
 - resets: phandle of the internal reset line

See ../spi/spi-bus.txt for more details on SPI bus master and slave devices
required and optional properties.

Example :
	spi@c1108d80 {
		compatible = "amlogic,meson-gx-spicc";
		reg = <0xc1108d80 0x80>;
		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
		clock-names = "core";
		clocks = <&clk81>;
		#address-cells = <1>;
		#size-cells = <0>;
	};
