MT8173 xHCI

The device node for Mediatek SOC USB3.0 host controller

Required properties:
 - compatible : should contain "mediatek,mt8173-xhci"
 - reg : specifies physical base address and size of the registers,
	the first one for MAC, the second for IPPC
 - interrupts : interrupt used by the controller
 - power-domains : a phandle to USB power domain node to control USB's
	mtcmos
 - vusb33-supply : regulator of USB avdd3.3v

 - clocks : a list of phandle + clock-specifier pairs, one for each
	entry in clock-names
 - clock-names : must contain
	"sys_ck": for clock of xHCI MAC
	"wakeup_deb_p0": for USB wakeup debounce clock of port0
	"wakeup_deb_p1": for USB wakeup debounce clock of port1

 - phys : a list of phandle + phy specifier pairs

Optional properties:
 - mediatek,wakeup-src : 1: ip sleep wakeup mode; 2: line state wakeup
	mode;
 - mediatek,syscon-wakeup : phandle to syscon used to access USB wakeup
	control register, it depends on "mediatek,wakeup-src".
 - vbus-supply : reference to the VBUS regulator;
 - usb3-lpm-capable : supports USB3.0 LPM

Example:
usb30: usb@11270000 {
	compatible = "mediatek,mt8173-xhci";
	reg = <0 0x11270000 0 0x1000>,
	      <0 0x11280700 0 0x0100>;
	interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>;
	power-domains = <&scpsys MT8173_POWER_DOMAIN_USB>;
	clocks = <&topckgen CLK_TOP_USB30_SEL>,
		 <&pericfg CLK_PERI_USB0>,
		 <&pericfg CLK_PERI_USB1>;
	clock-names = "sys_ck",
		      "wakeup_deb_p0",
		      "wakeup_deb_p1";
	phys = <&phy_port0 PHY_TYPE_USB3>,
	       <&phy_port1 PHY_TYPE_USB2>;
	vusb33-supply = <&mt6397_vusb_reg>;
	vbus-supply = <&usb_p1_vbus>;
	usb3-lpm-capable;
	mediatek,syscon-wakeup = <&pericfg>;
	mediatek,wakeup-src = <1>;
};
