rt2400pci.c 52.9 KB
Newer Older
1
/*
2
	Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
	<http://rt2x00.serialmonkey.com>

	This program is free software; you can redistribute it and/or modify
	it under the terms of the GNU General Public License as published by
	the Free Software Foundation; either version 2 of the License, or
	(at your option) any later version.

	This program is distributed in the hope that it will be useful,
	but WITHOUT ANY WARRANTY; without even the implied warranty of
	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	GNU General Public License for more details.

	You should have received a copy of the GNU General Public License
	along with this program; if not, write to the
	Free Software Foundation, Inc.,
	59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 */

/*
	Module: rt2400pci
	Abstract: rt2400pci device specific routines.
	Supported chipsets: RT2460.
 */

#include <linux/delay.h>
#include <linux/etherdevice.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/eeprom_93cx6.h>
34
#include <linux/slab.h>
35 36

#include "rt2x00.h"
37
#include "rt2x00mmio.h"
38 39 40 41 42 43 44 45 46 47 48 49
#include "rt2x00pci.h"
#include "rt2400pci.h"

/*
 * Register access.
 * All access to the CSR registers will go through the methods
 * rt2x00pci_register_read and rt2x00pci_register_write.
 * BBP and RF register require indirect register access,
 * and use the CSR registers BBPCSR and RFCSR to achieve this.
 * These indirect registers work with busy bits,
 * and we will try maximal REGISTER_BUSY_COUNT times to access
 * the register while taking a REGISTER_BUSY_DELAY us delay
Mark Einon's avatar
Mark Einon committed
50
 * between each attempt. When the busy bit is still set at that time,
51 52 53
 * the access attempt is considered to have failed,
 * and we will print an error.
 */
54 55 56 57
#define WAIT_FOR_BBP(__dev, __reg) \
	rt2x00pci_regbusy_read((__dev), BBPCSR, BBPCSR_BUSY, (__reg))
#define WAIT_FOR_RF(__dev, __reg) \
	rt2x00pci_regbusy_read((__dev), RFCSR, RFCSR_BUSY, (__reg))
58

Adam Baker's avatar
Adam Baker committed
59
static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
60 61 62 63
				const unsigned int word, const u8 value)
{
	u32 reg;

64 65
	mutex_lock(&rt2x00dev->csr_mutex);

66
	/*
67 68
	 * Wait until the BBP becomes available, afterwards we
	 * can safely write the new data into the register.
69
	 */
70 71 72 73 74 75 76 77 78
	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
		reg = 0;
		rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
		rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
		rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
		rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);

		rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
	}
79 80

	mutex_unlock(&rt2x00dev->csr_mutex);
81 82
}

Adam Baker's avatar
Adam Baker committed
83
static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
84 85 86 87
			       const unsigned int word, u8 *value)
{
	u32 reg;

88 89
	mutex_lock(&rt2x00dev->csr_mutex);

90
	/*
91 92 93 94 95 96
	 * Wait until the BBP becomes available, afterwards we
	 * can safely write the read request into the register.
	 * After the data has been written, we wait until hardware
	 * returns the correct value, if at any time the register
	 * doesn't become available in time, reg will be 0xffffffff
	 * which means we return 0xff to the caller.
97
	 */
98 99 100 101 102
	if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
		reg = 0;
		rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
		rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
		rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
103

104
		rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
105

106 107
		WAIT_FOR_BBP(rt2x00dev, &reg);
	}
108 109

	*value = rt2x00_get_field32(reg, BBPCSR_VALUE);
110 111

	mutex_unlock(&rt2x00dev->csr_mutex);
112 113
}

Adam Baker's avatar
Adam Baker committed
114
static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
115 116 117 118
			       const unsigned int word, const u32 value)
{
	u32 reg;

119 120
	mutex_lock(&rt2x00dev->csr_mutex);

121 122 123 124 125 126 127 128 129 130 131 132 133
	/*
	 * Wait until the RF becomes available, afterwards we
	 * can safely write the new data into the register.
	 */
	if (WAIT_FOR_RF(rt2x00dev, &reg)) {
		reg = 0;
		rt2x00_set_field32(&reg, RFCSR_VALUE, value);
		rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
		rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
		rt2x00_set_field32(&reg, RFCSR_BUSY, 1);

		rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
		rt2x00_rf_write(rt2x00dev, word, value);
134 135
	}

136
	mutex_unlock(&rt2x00dev->csr_mutex);
137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172
}

static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
{
	struct rt2x00_dev *rt2x00dev = eeprom->data;
	u32 reg;

	rt2x00pci_register_read(rt2x00dev, CSR21, &reg);

	eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
	eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
	eeprom->reg_data_clock =
	    !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
	eeprom->reg_chip_select =
	    !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
}

static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
{
	struct rt2x00_dev *rt2x00dev = eeprom->data;
	u32 reg = 0;

	rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
	rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
	rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
			   !!eeprom->reg_data_clock);
	rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
			   !!eeprom->reg_chip_select);

	rt2x00pci_register_write(rt2x00dev, CSR21, reg);
}

#ifdef CONFIG_RT2X00_LIB_DEBUGFS
static const struct rt2x00debug rt2400pci_rt2x00debug = {
	.owner	= THIS_MODULE,
	.csr	= {
173 174 175 176
		.read		= rt2x00pci_register_read,
		.write		= rt2x00pci_register_write,
		.flags		= RT2X00DEBUGFS_OFFSET,
		.word_base	= CSR_REG_BASE,
177 178 179 180 181 182
		.word_size	= sizeof(u32),
		.word_count	= CSR_REG_SIZE / sizeof(u32),
	},
	.eeprom	= {
		.read		= rt2x00_eeprom_read,
		.write		= rt2x00_eeprom_write,
183
		.word_base	= EEPROM_BASE,
184 185 186 187 188 189
		.word_size	= sizeof(u16),
		.word_count	= EEPROM_SIZE / sizeof(u16),
	},
	.bbp	= {
		.read		= rt2400pci_bbp_read,
		.write		= rt2400pci_bbp_write,
190
		.word_base	= BBP_BASE,
191 192 193 194 195 196
		.word_size	= sizeof(u8),
		.word_count	= BBP_SIZE / sizeof(u8),
	},
	.rf	= {
		.read		= rt2x00_rf_read,
		.write		= rt2400pci_rf_write,
197
		.word_base	= RF_BASE,
198 199 200 201 202 203 204 205 206 207 208
		.word_size	= sizeof(u32),
		.word_count	= RF_SIZE / sizeof(u32),
	},
};
#endif /* CONFIG_RT2X00_LIB_DEBUGFS */

static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
{
	u32 reg;

	rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
209
	return rt2x00_get_field32(reg, GPIOCSR_VAL0);
210 211
}

212
#ifdef CONFIG_RT2X00_LIB_LEDS
213
static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
214 215 216 217 218 219 220 221 222
				     enum led_brightness brightness)
{
	struct rt2x00_led *led =
	    container_of(led_cdev, struct rt2x00_led, led_dev);
	unsigned int enabled = brightness != LED_OFF;
	u32 reg;

	rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);

223
	if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
224
		rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
225 226
	else if (led->type == LED_TYPE_ACTIVITY)
		rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
227 228 229

	rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
}
230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245

static int rt2400pci_blink_set(struct led_classdev *led_cdev,
			       unsigned long *delay_on,
			       unsigned long *delay_off)
{
	struct rt2x00_led *led =
	    container_of(led_cdev, struct rt2x00_led, led_dev);
	u32 reg;

	rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
	rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
	rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
	rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);

	return 0;
}
246 247 248 249 250 251 252 253 254 255 256

static void rt2400pci_init_led(struct rt2x00_dev *rt2x00dev,
			       struct rt2x00_led *led,
			       enum led_type type)
{
	led->rt2x00dev = rt2x00dev;
	led->type = type;
	led->led_dev.brightness_set = rt2400pci_brightness_set;
	led->led_dev.blink_set = rt2400pci_blink_set;
	led->flags = LED_INITIALIZED;
}
257
#endif /* CONFIG_RT2X00_LIB_LEDS */
258

259 260 261
/*
 * Configuration handlers.
 */
262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281
static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
				    const unsigned int filter_flags)
{
	u32 reg;

	/*
	 * Start configuration steps.
	 * Note that the version error will always be dropped
	 * since there is no filter for it at this time.
	 */
	rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
	rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
			   !(filter_flags & FIF_FCSFAIL));
	rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
			   !(filter_flags & FIF_PLCPFAIL));
	rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
			   !(filter_flags & FIF_CONTROL));
	rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
			   !(filter_flags & FIF_PROMISC_IN_BSS));
	rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
282 283
			   !(filter_flags & FIF_PROMISC_IN_BSS) &&
			   !rt2x00dev->intf_ap_count);
284 285 286 287
	rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
	rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
}

288 289 290 291
static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
				  struct rt2x00_intf *intf,
				  struct rt2x00intf_conf *conf,
				  const unsigned int flags)
292
{
293 294
	unsigned int bcn_preload;
	u32 reg;
295

296 297 298 299
	if (flags & CONFIG_UPDATE_TYPE) {
		/*
		 * Enable beacon config
		 */
300
		bcn_preload = PREAMBLE + GET_DURATION(IEEE80211_HEADER, 20);
301 302 303
		rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
		rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
		rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
304

305 306 307 308 309 310 311
		/*
		 * Enable synchronisation.
		 */
		rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
		rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
		rt2x00pci_register_write(rt2x00dev, CSR14, reg);
	}
312

313 314 315
	if (flags & CONFIG_UPDATE_MAC)
		rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
					      conf->mac, sizeof(conf->mac));
316

317 318 319
	if (flags & CONFIG_UPDATE_BSSID)
		rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
					      conf->bssid, sizeof(conf->bssid));
320 321
}

322
static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
323 324
				 struct rt2x00lib_erp *erp,
				 u32 changed)
325
{
326
	int preamble_mask;
327 328
	u32 reg;

329 330 331
	/*
	 * When short preamble is enabled, we should set bit 0x08
	 */
332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397
	if (changed & BSS_CHANGED_ERP_PREAMBLE) {
		preamble_mask = erp->short_preamble << 3;

		rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
		rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, 0x1ff);
		rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, 0x13a);
		rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
		rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
		rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);

		rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
		rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
		rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
		rt2x00_set_field32(&reg, ARCSR2_LENGTH,
				   GET_DURATION(ACK_SIZE, 10));
		rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);

		rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
		rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
		rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
		rt2x00_set_field32(&reg, ARCSR2_LENGTH,
				   GET_DURATION(ACK_SIZE, 20));
		rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);

		rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
		rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
		rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
		rt2x00_set_field32(&reg, ARCSR2_LENGTH,
				   GET_DURATION(ACK_SIZE, 55));
		rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);

		rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
		rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
		rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
		rt2x00_set_field32(&reg, ARCSR2_LENGTH,
				   GET_DURATION(ACK_SIZE, 110));
		rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
	}

	if (changed & BSS_CHANGED_BASIC_RATES)
		rt2x00pci_register_write(rt2x00dev, ARCSR1, erp->basic_rates);

	if (changed & BSS_CHANGED_ERP_SLOT) {
		rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
		rt2x00_set_field32(&reg, CSR11_SLOT_TIME, erp->slot_time);
		rt2x00pci_register_write(rt2x00dev, CSR11, reg);

		rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
		rt2x00_set_field32(&reg, CSR18_SIFS, erp->sifs);
		rt2x00_set_field32(&reg, CSR18_PIFS, erp->pifs);
		rt2x00pci_register_write(rt2x00dev, CSR18, reg);

		rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
		rt2x00_set_field32(&reg, CSR19_DIFS, erp->difs);
		rt2x00_set_field32(&reg, CSR19_EIFS, erp->eifs);
		rt2x00pci_register_write(rt2x00dev, CSR19, reg);
	}

	if (changed & BSS_CHANGED_BEACON_INT) {
		rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
		rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
				   erp->beacon_int * 16);
		rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
				   erp->beacon_int * 16);
		rt2x00pci_register_write(rt2x00dev, CSR12, reg);
	}
398 399
}

400 401
static void rt2400pci_config_ant(struct rt2x00_dev *rt2x00dev,
				 struct antenna_setup *ant)
402
{
403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449
	u8 r1;
	u8 r4;

	/*
	 * We should never come here because rt2x00lib is supposed
	 * to catch this and send us the correct antenna explicitely.
	 */
	BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
	       ant->tx == ANTENNA_SW_DIVERSITY);

	rt2400pci_bbp_read(rt2x00dev, 4, &r4);
	rt2400pci_bbp_read(rt2x00dev, 1, &r1);

	/*
	 * Configure the TX antenna.
	 */
	switch (ant->tx) {
	case ANTENNA_HW_DIVERSITY:
		rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
		break;
	case ANTENNA_A:
		rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
		break;
	case ANTENNA_B:
	default:
		rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
		break;
	}

	/*
	 * Configure the RX antenna.
	 */
	switch (ant->rx) {
	case ANTENNA_HW_DIVERSITY:
		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
		break;
	case ANTENNA_A:
		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
		break;
	case ANTENNA_B:
	default:
		rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
		break;
	}

	rt2400pci_bbp_write(rt2x00dev, 4, r4);
	rt2400pci_bbp_write(rt2x00dev, 1, r1);
450 451 452
}

static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
453
				     struct rf_channel *rf)
454 455 456 457
{
	/*
	 * Switch on tuning bits.
	 */
458 459
	rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
	rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
460

461 462 463
	rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
	rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
	rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
464 465 466 467

	/*
	 * RF2420 chipset don't need any additional actions.
	 */
468
	if (rt2x00_rf(rt2x00dev, RF2420))
469 470 471 472 473 474 475
		return;

	/*
	 * For the RT2421 chipsets we need to write an invalid
	 * reference clock rate to activate auto_tune.
	 * After that we set the value back to the correct channel.
	 */
476
	rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
477
	rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
478
	rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
479 480 481

	msleep(1);

482 483 484
	rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
	rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
	rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
485 486 487 488 489 490

	msleep(1);

	/*
	 * Switch off tuning bits.
	 */
491 492
	rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
	rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
493

494 495
	rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
	rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
496 497 498 499

	/*
	 * Clear false CRC during channel switch.
	 */
500
	rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
501 502 503 504 505 506 507
}

static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
{
	rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
}

508 509
static void rt2400pci_config_retry_limit(struct rt2x00_dev *rt2x00dev,
					 struct rt2x00lib_conf *libconf)
510
{
511
	u32 reg;
512

513 514 515 516 517 518
	rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
	rt2x00_set_field32(&reg, CSR11_LONG_RETRY,
			   libconf->conf->long_frame_max_tx_count);
	rt2x00_set_field32(&reg, CSR11_SHORT_RETRY,
			   libconf->conf->short_frame_max_tx_count);
	rt2x00pci_register_write(rt2x00dev, CSR11, reg);
519 520
}

521 522 523 524 525 526 527 528 529 530 531
static void rt2400pci_config_ps(struct rt2x00_dev *rt2x00dev,
				struct rt2x00lib_conf *libconf)
{
	enum dev_state state =
	    (libconf->conf->flags & IEEE80211_CONF_PS) ?
		STATE_SLEEP : STATE_AWAKE;
	u32 reg;

	if (state == STATE_SLEEP) {
		rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
		rt2x00_set_field32(&reg, CSR20_DELAY_AFTER_TBCN,
532
				   (rt2x00dev->beacon_int - 20) * 16);
533 534 535 536 537 538 539 540 541
		rt2x00_set_field32(&reg, CSR20_TBCN_BEFORE_WAKEUP,
				   libconf->conf->listen_interval - 1);

		/* We must first disable autowake before it can be enabled */
		rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
		rt2x00pci_register_write(rt2x00dev, CSR20, reg);

		rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 1);
		rt2x00pci_register_write(rt2x00dev, CSR20, reg);
542 543 544 545
	} else {
		rt2x00pci_register_read(rt2x00dev, CSR20, &reg);
		rt2x00_set_field32(&reg, CSR20_AUTOWAKE, 0);
		rt2x00pci_register_write(rt2x00dev, CSR20, reg);
546 547 548 549 550
	}

	rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
}

551
static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
552 553
			     struct rt2x00lib_conf *libconf,
			     const unsigned int flags)
554
{
555
	if (flags & IEEE80211_CONF_CHANGE_CHANNEL)
556
		rt2400pci_config_channel(rt2x00dev, &libconf->rf);
557
	if (flags & IEEE80211_CONF_CHANGE_POWER)
558 559
		rt2400pci_config_txpower(rt2x00dev,
					 libconf->conf->power_level);
560 561
	if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
		rt2400pci_config_retry_limit(rt2x00dev, libconf);
562 563
	if (flags & IEEE80211_CONF_CHANGE_PS)
		rt2400pci_config_ps(rt2x00dev, libconf);
564 565 566
}

static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
567
				const int cw_min, const int cw_max)
568 569 570 571
{
	u32 reg;

	rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
572 573
	rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
	rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
574 575 576 577 578 579
	rt2x00pci_register_write(rt2x00dev, CSR11, reg);
}

/*
 * Link tuning
 */
580 581
static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
				 struct link_qual *qual)
582 583 584 585 586 587 588 589
{
	u32 reg;
	u8 bbp;

	/*
	 * Update FCS error count from register.
	 */
	rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
590
	qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
591 592 593 594 595

	/*
	 * Update False CCA count from register.
	 */
	rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
596
	qual->false_cca = bbp;
597 598
}

599 600
static inline void rt2400pci_set_vgc(struct rt2x00_dev *rt2x00dev,
				     struct link_qual *qual, u8 vgc_level)
601
{
602 603 604 605 606
	if (qual->vgc_level_reg != vgc_level) {
		rt2400pci_bbp_write(rt2x00dev, 13, vgc_level);
		qual->vgc_level = vgc_level;
		qual->vgc_level_reg = vgc_level;
	}
607 608
}

609 610
static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev,
				  struct link_qual *qual)
611
{
612
	rt2400pci_set_vgc(rt2x00dev, qual, 0x08);
613 614
}

615 616
static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev,
				 struct link_qual *qual, const u32 count)
617 618 619 620 621
{
	/*
	 * The link tuner should not run longer then 60 seconds,
	 * and should run once every 2 seconds.
	 */
622
	if (count > 60 || !(count & 1))
623 624 625 626 627
		return;

	/*
	 * Base r13 link tuning on the false cca count.
	 */
628 629 630 631
	if ((qual->false_cca > 512) && (qual->vgc_level < 0x20))
		rt2400pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level);
	else if ((qual->false_cca < 100) && (qual->vgc_level > 0x08))
		rt2400pci_set_vgc(rt2x00dev, qual, --qual->vgc_level);
632 633
}

634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665
/*
 * Queue handlers.
 */
static void rt2400pci_start_queue(struct data_queue *queue)
{
	struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
	u32 reg;

	switch (queue->qid) {
	case QID_RX:
		rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
		rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 0);
		rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
		break;
	case QID_BEACON:
		rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
		rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
		rt2x00_set_field32(&reg, CSR14_TBCN, 1);
		rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
		rt2x00pci_register_write(rt2x00dev, CSR14, reg);
		break;
	default:
		break;
	}
}

static void rt2400pci_kick_queue(struct data_queue *queue)
{
	struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
	u32 reg;

	switch (queue->qid) {
Ivo van Doorn's avatar
Ivo van Doorn committed
666
	case QID_AC_VO:
667 668 669 670
		rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
		rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
		rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
		break;
Ivo van Doorn's avatar
Ivo van Doorn committed
671
	case QID_AC_VI:
672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691
		rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
		rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
		rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
		break;
	case QID_ATIM:
		rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
		rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
		rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
		break;
	default:
		break;
	}
}

static void rt2400pci_stop_queue(struct data_queue *queue)
{
	struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
	u32 reg;

	switch (queue->qid) {
Ivo van Doorn's avatar
Ivo van Doorn committed
692 693
	case QID_AC_VO:
	case QID_AC_VI:
694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709
	case QID_ATIM:
		rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
		rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
		rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
		break;
	case QID_RX:
		rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
		rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX, 1);
		rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
		break;
	case QID_BEACON:
		rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
		rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
		rt2x00_set_field32(&reg, CSR14_TBCN, 0);
		rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
		rt2x00pci_register_write(rt2x00dev, CSR14, reg);
710 711 712 713

		/*
		 * Wait for possibly running tbtt tasklets.
		 */
714
		tasklet_kill(&rt2x00dev->tbtt_tasklet);
715 716 717 718 719 720
		break;
	default:
		break;
	}
}

721 722 723
/*
 * Initialization functions.
 */
724
static bool rt2400pci_get_entry_state(struct queue_entry *entry)
725
{
726
	struct queue_entry_priv_pci *entry_priv = entry->priv_data;
727 728
	u32 word;

729 730
	if (entry->queue->qid == QID_RX) {
		rt2x00_desc_read(entry_priv->desc, 0, &word);
731

732 733 734
		return rt2x00_get_field32(word, RXD_W0_OWNER_NIC);
	} else {
		rt2x00_desc_read(entry_priv->desc, 0, &word);
735

736 737 738
		return (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
		        rt2x00_get_field32(word, TXD_W0_VALID));
	}
739 740
}

741
static void rt2400pci_clear_entry(struct queue_entry *entry)
742
{
743
	struct queue_entry_priv_pci *entry_priv = entry->priv_data;
744
	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
745 746
	u32 word;

747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764
	if (entry->queue->qid == QID_RX) {
		rt2x00_desc_read(entry_priv->desc, 2, &word);
		rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH, entry->skb->len);
		rt2x00_desc_write(entry_priv->desc, 2, word);

		rt2x00_desc_read(entry_priv->desc, 1, &word);
		rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
		rt2x00_desc_write(entry_priv->desc, 1, word);

		rt2x00_desc_read(entry_priv->desc, 0, &word);
		rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
		rt2x00_desc_write(entry_priv->desc, 0, word);
	} else {
		rt2x00_desc_read(entry_priv->desc, 0, &word);
		rt2x00_set_field32(&word, TXD_W0_VALID, 0);
		rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
		rt2x00_desc_write(entry_priv->desc, 0, word);
	}
765 766
}

767
static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
768
{
769
	struct queue_entry_priv_pci *entry_priv;
770 771 772 773 774 775
	u32 reg;

	/*
	 * Initialize registers.
	 */
	rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
776 777
	rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
	rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
778
	rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit);
779
	rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
780 781
	rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);

782
	entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
783
	rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
784
	rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
785
			   entry_priv->desc_dma);
786 787
	rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);

788
	entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
789
	rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
790
	rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
791
			   entry_priv->desc_dma);
792 793
	rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);

794
	entry_priv = rt2x00dev->atim->entries[0].priv_data;
795
	rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
796
	rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
797
			   entry_priv->desc_dma);
798 799
	rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);

800
	entry_priv = rt2x00dev->bcn->entries[0].priv_data;
801
	rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
802
	rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
803
			   entry_priv->desc_dma);
804 805 806 807
	rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);

	rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
	rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
808
	rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
809 810
	rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);

811
	entry_priv = rt2x00dev->rx->entries[0].priv_data;
812
	rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
813 814
	rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
			   entry_priv->desc_dma);
815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839
	rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);

	return 0;
}

static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
{
	u32 reg;

	rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
	rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
	rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
	rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);

	rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
	rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
	rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
	rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
	rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);

	rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
	rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
			   (rt2x00dev->rx->data_size / 128));
	rt2x00pci_register_write(rt2x00dev, CSR9, reg);

840 841 842 843 844 845 846 847 848 849 850
	rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
	rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
	rt2x00_set_field32(&reg, CSR14_TSF_SYNC, 0);
	rt2x00_set_field32(&reg, CSR14_TBCN, 0);
	rt2x00_set_field32(&reg, CSR14_TCFP, 0);
	rt2x00_set_field32(&reg, CSR14_TATIMW, 0);
	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
	rt2x00_set_field32(&reg, CSR14_CFP_COUNT_PRELOAD, 0);
	rt2x00_set_field32(&reg, CSR14_TBCM_PRELOAD, 0);
	rt2x00pci_register_write(rt2x00dev, CSR14, reg);

851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909
	rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);

	rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
	rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
	rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);

	rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
	rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
	rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
	rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
	rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
	rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
	rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
	rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);

	rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);

	if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
		return -EBUSY;

	rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
	rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);

	rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
	rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
	rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);

	rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
	rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
	rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);

	rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
	rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
	rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
	rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
	rt2x00pci_register_write(rt2x00dev, CSR1, reg);

	rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
	rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
	rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
	rt2x00pci_register_write(rt2x00dev, CSR1, reg);

	/*
	 * We must clear the FCS and FIFO error count.
	 * These registers are cleared on read,
	 * so we may pass a useless variable to store the value.
	 */
	rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
	rt2x00pci_register_read(rt2x00dev, CNT4, &reg);

	return 0;
}

910
static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
911 912 913 914 915 916 917
{
	unsigned int i;
	u8 value;

	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
		rt2400pci_bbp_read(rt2x00dev, 0, &value);
		if ((value != 0xff) && (value != 0x00))
918
			return 0;
919 920 921 922 923
		udelay(REGISTER_BUSY_DELAY);
	}

	ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
	return -EACCES;
924 925 926 927 928 929 930 931 932 933 934
}

static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
{
	unsigned int i;
	u16 eeprom;
	u8 reg_id;
	u8 value;

	if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
		return -EACCES;
935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969

	rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
	rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
	rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
	rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
	rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
	rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
	rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
	rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
	rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
	rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
	rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
	rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
	rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
	rt2400pci_bbp_write(rt2x00dev, 31, 0x00);

	for (i = 0; i < EEPROM_BBP_SIZE; i++) {
		rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);

		if (eeprom != 0xffff && eeprom != 0x0000) {
			reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
			value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
			rt2400pci_bbp_write(rt2x00dev, reg_id, value);
		}
	}

	return 0;
}

/*
 * Device state switch handlers.
 */
static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
				 enum dev_state state)
{
970
	int mask = (state == STATE_RADIO_IRQ_OFF);
971
	u32 reg;
972
	unsigned long flags;
973 974 975 976 977 978 979 980 981 982 983 984 985 986

	/*
	 * When interrupts are being enabled, the interrupt registers
	 * should clear the register to assure a clean state.
	 */
	if (state == STATE_RADIO_IRQ_ON) {
		rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
		rt2x00pci_register_write(rt2x00dev, CSR7, reg);
	}

	/*
	 * Only toggle the interrupts bits we are going to use.
	 * Non-checked interrupt bits are disabled by default.
	 */
987 988
	spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);

989 990 991 992 993 994 995
	rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
	rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
	rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
	rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
	rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
	rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
	rt2x00pci_register_write(rt2x00dev, CSR8, reg);
996 997 998 999 1000 1001 1002 1003

	spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);

	if (state == STATE_RADIO_IRQ_OFF) {
		/*
		 * Ensure that all tasklets are finished before
		 * disabling the interrupts.
		 */
1004 1005 1006
		tasklet_kill(&rt2x00dev->txstatus_tasklet);
		tasklet_kill(&rt2x00dev->rxdone_tasklet);
		tasklet_kill(&rt2x00dev->tbtt_tasklet);
1007
	}
1008 1009 1010 1011 1012 1013 1014
}

static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
{
	/*
	 * Initialize all registers.
	 */
1015 1016 1017
	if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
		     rt2400pci_init_registers(rt2x00dev) ||
		     rt2400pci_init_bbp(rt2x00dev)))
1018 1019 1020 1021 1022 1023 1024 1025
		return -EIO;

	return 0;
}

static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
{
	/*
1026
	 * Disable power
1027
	 */
1028
	rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1029 1030 1031 1032 1033
}

static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
			       enum dev_state state)
{
1034
	u32 reg, reg2;
1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054
	unsigned int i;
	char put_to_sleep;
	char bbp_state;
	char rf_state;

	put_to_sleep = (state != STATE_AWAKE);

	rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
	rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
	rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
	rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
	rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
	rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);

	/*
	 * Device is not guaranteed to be in the requested state yet.
	 * We must wait until the register indicates that the
	 * device has entered the correct state.
	 */
	for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1055 1056 1057
		rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg2);
		bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE);
		rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE);
1058 1059
		if (bbp_state == state && rf_state == state)
			return 0;
1060
		rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078
		msleep(10);
	}

	return -EBUSY;
}

static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
				      enum dev_state state)
{
	int retval = 0;

	switch (state) {
	case STATE_RADIO_ON:
		retval = rt2400pci_enable_radio(rt2x00dev);
		break;
	case STATE_RADIO_OFF:
		rt2400pci_disable_radio(rt2x00dev);
		break;
1079 1080 1081
	case STATE_RADIO_IRQ_ON:
	case STATE_RADIO_IRQ_OFF:
		rt2400pci_toggle_irq(rt2x00dev, state);
1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093
		break;
	case STATE_DEEP_SLEEP:
	case STATE_SLEEP:
	case STATE_STANDBY:
	case STATE_AWAKE:
		retval = rt2400pci_set_state(rt2x00dev, state);
		break;
	default:
		retval = -ENOTSUPP;
		break;
	}

1094 1095 1096 1097
	if (unlikely(retval))
		ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
		      state, retval);

1098 1099 1100 1101 1102 1103
	return retval;
}

/*
 * TX descriptor initialization
 */
1104
static void rt2400pci_write_tx_desc(struct queue_entry *entry,
1105
				    struct txentry_desc *txdesc)
1106
{
1107 1108
	struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
	struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1109
	__le32 *txd = entry_priv->desc;
1110 1111 1112 1113 1114
	u32 word;

	/*
	 * Start writing the descriptor words.
	 */
1115
	rt2x00_desc_read(txd, 1, &word);
1116
	rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, skbdesc->skb_dma);
1117
	rt2x00_desc_write(txd, 1, word);
1118

1119
	rt2x00_desc_read(txd, 2, &word);
1120 1121
	rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, txdesc->length);
	rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, txdesc->length);
1122 1123 1124
	rt2x00_desc_write(txd, 2, word);

	rt2x00_desc_read(txd, 3, &word);
1125
	rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->u.plcp.signal);
1126 1127
	rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
	rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1128
	rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->u.plcp.service);
1129 1130
	rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
	rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1131 1132 1133
	rt2x00_desc_write(txd, 3, word);

	rt2x00_desc_read(txd, 4, &word);
1134 1135
	rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW,
			   txdesc->u.plcp.length_low);
1136 1137
	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1138 1139
	rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH,
			   txdesc->u.plcp.length_high);
1140 1141
	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
	rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1142 1143
	rt2x00_desc_write(txd, 4, word);

1144 1145 1146 1147 1148
	/*
	 * Writing TXD word 0 must the last to prevent a race condition with
	 * the device, whereby the device may take hold of the TXD before we
	 * finished updating it.
	 */
1149 1150 1151 1152
	rt2x00_desc_read(txd, 0, &word);
	rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
	rt2x00_set_field32(&word, TXD_W0_VALID, 1);
	rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1153
			   test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1154
	rt2x00_set_field32(&word, TXD_W0_ACK,
1155
			   test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1156
	rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1157
			   test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1158
	rt2x00_set_field32(&word, TXD_W0_RTS,
1159
			   test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1160
	rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->u.plcp.ifs);
1161
	rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
Ivo van Doorn's avatar
Ivo van Doorn committed
1162
			   test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1163
	rt2x00_desc_write(txd, 0, word);
1164 1165 1166 1167 1168 1169

	/*
	 * Register descriptor details in skb frame descriptor.
	 */
	skbdesc->desc = txd;
	skbdesc->desc_len = TXD_DESC_SIZE;
1170 1171 1172 1173 1174
}

/*
 * TX data initialization
 */
1175 1176
static void rt2400pci_write_beacon(struct queue_entry *entry,
				   struct txentry_desc *txdesc)
1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188
{
	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
	u32 reg;

	/*
	 * Disable beaconing while we are reloading the beacon data,
	 * otherwise we might be sending out invalid data.
	 */
	rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
	rt2x00pci_register_write(rt2x00dev, CSR14, reg);

1189 1190 1191 1192 1193 1194 1195 1196
	if (rt2x00queue_map_txskb(entry)) {
		ERROR(rt2x00dev, "Fail to map beacon, aborting\n");
		goto out;
	}
	/*
	 * Enable beaconing again.
	 */
	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1197 1198 1199
	/*
	 * Write the TX descriptor for the beacon.
	 */
1200
	rt2400pci_write_tx_desc(entry, txdesc);
1201 1202 1203 1204 1205

	/*
	 * Dump beacon to userspace through debugfs.
	 */
	rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
1206
out:
1207 1208 1209 1210 1211
	/*
	 * Enable beaconing again.
	 */
	rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
	rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1212 1213
}

1214 1215 1216
/*
 * RX control handlers
 */
1217 1218
static void rt2400pci_fill_rxdone(struct queue_entry *entry,
				  struct rxdone_entry_desc *rxdesc)
1219
{
1220
	struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1221
	struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1222 1223
	u32 word0;
	u32 word2;
Ivo van Doorn's avatar
Ivo van Doorn committed
1224
	u32 word3;
1225 1226 1227 1228
	u32 word4;
	u64 tsf;
	u32 rx_low;
	u32 rx_high;
1229

1230 1231 1232
	rt2x00_desc_read(entry_priv->desc, 0, &word0);
	rt2x00_desc_read(entry_priv->desc, 2, &word2);
	rt2x00_desc_read(entry_priv->desc, 3, &word3);
1233
	rt2x00_desc_read(entry_priv->desc, 4, &word4);
1234

1235
	if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1236
		rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1237
	if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1238
		rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1239

1240 1241 1242 1243 1244 1245 1246 1247 1248
	/*
	 * We only get the lower 32bits from the timestamp,
	 * to get the full 64bits we must complement it with
	 * the timestamp from get_tsf().
	 * Note that when a wraparound of the lower 32bits
	 * has occurred between the frame arrival and the get_tsf()
	 * call, we must decrease the higher 32bits with 1 to get
	 * to correct value.
	 */
1249
	tsf = rt2x00dev->ops->hw->get_tsf(rt2x00dev->hw, NULL);
1250 1251 1252 1253 1254 1255
	rx_low = rt2x00_get_field32(word4, RXD_W4_RX_END_TIME);
	rx_high = upper_32_bits(tsf);

	if ((u32)tsf <= rx_low)
		rx_high--;

1256 1257
	/*
	 * Obtain the status about this packet.
1258 1259
	 * The signal is the PLCP value, and needs to be stripped
	 * of the preamble bit (0x08).
1260
	 */
1261
	rxdesc->timestamp = ((u64)rx_high << 32) | rx_low;
1262
	rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
Ivo van Doorn's avatar
Ivo van Doorn committed
1263
	rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1264 1265
	    entry->queue->rt2x00dev->rssi_offset;
	rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1266

1267
	rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1268 1269
	if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
		rxdesc->dev_flags |= RXDONE_MY_BSS;
1270 1271 1272 1273 1274
}

/*
 * Interrupt functions.
 */
1275
static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1276
			     const enum data_queue_qid queue_idx)
1277
{
1278
	struct data_queue *queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
1279
	struct queue_entry_priv_pci *entry_priv;
1280 1281
	struct queue_entry *entry;
	struct txdone_entry_desc txdesc;
1282 1283
	u32 word;

1284 1285
	while (!rt2x00queue_empty(queue)) {
		entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1286 1287
		entry_priv = entry->priv_data;
		rt2x00_desc_read(entry_priv->desc, 0, &word);
1288 1289 1290 1291 1292 1293 1294 1295

		if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
		    !rt2x00_get_field32(word, TXD_W0_VALID))
			break;

		/*
		 * Obtain the status about this packet.
		 */
1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307
		txdesc.flags = 0;
		switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
		case 0: /* Success */
		case 1: /* Success with retry */
			__set_bit(TXDONE_SUCCESS, &txdesc.flags);
			break;
		case 2: /* Failure, excessive retries */
			__set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
			/* Don't break, this is a failed frame! */
		default: /* Failure */
			__set_bit(TXDONE_FAILURE, &txdesc.flags);
		}
1308
		txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1309

1310
		rt2x00lib_txdone(entry, &txdesc);
1311 1312 1313
	}
}

1314 1315
static inline void rt2400pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
					      struct rt2x00_field32 irq_field)
1316
{
1317
	u32 reg;
1318 1319

	/*
1320 1321
	 * Enable a single interrupt. The interrupt mask register
	 * access needs locking.
1322
	 */
1323
	spin_lock_irq(&rt2x00dev->irqmask_lock);
1324

1325 1326 1327
	rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
	rt2x00_set_field32(&reg, irq_field, 0);
	rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1328

1329
	spin_unlock_irq(&rt2x00dev->irqmask_lock);
1330
}
1331

1332 1333 1334 1335
static void rt2400pci_txstatus_tasklet(unsigned long data)
{
	struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
	u32 reg;
1336 1337

	/*
1338
	 * Handle all tx queues.
1339
	 */
1340 1341 1342
	rt2400pci_txdone(rt2x00dev, QID_ATIM);
	rt2400pci_txdone(rt2x00dev, QID_AC_VO);
	rt2400pci_txdone(rt2x00dev, QID_AC_VI);
1343 1344

	/*
1345
	 * Enable all TXDONE interrupts again.
1346
	 */
1347 1348
	if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) {
		spin_lock_irq(&rt2x00dev->irqmask_lock);
1349

1350 1351 1352 1353 1354
		rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
		rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, 0);
		rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, 0);
		rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, 0);
		rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1355

1356 1357
		spin_unlock_irq(&rt2x00dev->irqmask_lock);
	}
1358 1359 1360 1361 1362 1363
}

static void rt2400pci_tbtt_tasklet(unsigned long data)
{
	struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
	rt2x00lib_beacondone(rt2x00dev);
1364 1365
	if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
		rt2400pci_enable_interrupt(rt2x00dev, CSR8_TBCN_EXPIRE);
1366 1367 1368 1369 1370
}

static void rt2400pci_rxdone_tasklet(unsigned long data)
{
	struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
1371 1372
	if (rt2x00pci_rxdone(rt2x00dev))
		tasklet_schedule(&rt2x00dev->rxdone_tasklet);
1373
	else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
1374
		rt2400pci_enable_interrupt(rt2x00dev, CSR8_RXDONE);
1375 1376
}

1377 1378 1379
static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
{
	struct rt2x00_dev *rt2x00dev = dev_instance;
1380
	u32 reg, mask;
1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394

	/*
	 * Get the interrupt sources & saved to local variable.
	 * Write register value back to clear pending interrupts.
	 */
	rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
	rt2x00pci_register_write(rt2x00dev, CSR7, reg);

	if (!reg)
		return IRQ_NONE;

	if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
		return IRQ_HANDLED;

1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416
	mask = reg;

	/*
	 * Schedule tasklets for interrupt handling.
	 */
	if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
		tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);

	if (rt2x00_get_field32(reg, CSR7_RXDONE))
		tasklet_schedule(&rt2x00dev->rxdone_tasklet);

	if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) ||
	    rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) ||
	    rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) {
		tasklet_schedule(&rt2x00dev->txstatus_tasklet);
		/*
		 * Mask out all txdone interrupts.
		 */
		rt2x00_set_field32(&mask, CSR8_TXDONE_TXRING, 1);
		rt2x00_set_field32(&mask, CSR8_TXDONE_ATIMRING, 1);
		rt2x00_set_field32(&mask, CSR8_TXDONE_PRIORING, 1);
	}
1417

1418 1419 1420 1421
	/*
	 * Disable all interrupts for which a tasklet was scheduled right now,
	 * the tasklet will reenable the appropriate interrupts.
	 */
1422
	spin_lock(&rt2x00dev->irqmask_lock);
1423

1424 1425 1426 1427
	rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
	reg |= mask;
	rt2x00pci_register_write(rt2x00dev, CSR8, reg);

1428
	spin_unlock(&rt2x00dev->irqmask_lock);
1429 1430 1431 1432



	return IRQ_HANDLED;
1433 1434
}

1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464
/*
 * Device probe functions.
 */
static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
{
	struct eeprom_93cx6 eeprom;
	u32 reg;
	u16 word;
	u8 *mac;

	rt2x00pci_register_read(rt2x00dev, CSR21, &reg);

	eeprom.data = rt2x00dev;
	eeprom.register_read = rt2400pci_eepromregister_read;
	eeprom.register_write = rt2400pci_eepromregister_write;
	eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
	    PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
	eeprom.reg_data_in = 0;
	eeprom.reg_data_out = 0;
	eeprom.reg_data_clock = 0;
	eeprom.reg_chip_select = 0;

	eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
			       EEPROM_SIZE / sizeof(u16));

	/*
	 * Start validation of the data that has been read.
	 */
	mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
	if (!is_valid_ether_addr(mac)) {
Joe Perches's avatar
Joe Perches committed
1465
		eth_random_addr(mac);
1466
		EEPROM(rt2x00dev, "MAC: %pM\n", mac);
1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493
	}

	rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
	if (word == 0xffff) {
		ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
		return -EINVAL;
	}

	return 0;
}

static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
{
	u32 reg;
	u16 value;
	u16 eeprom;

	/*
	 * Read EEPROM word for configuration.
	 */
	rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);

	/*
	 * Identify RF chipset.
	 */
	value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
	rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1494 1495
	rt2x00_set_chip(rt2x00dev, RT2460, value,
			rt2x00_get_field32(reg, CSR0_REVISION));
1496

1497
	if (!rt2x00_rf(rt2x00dev, RF2420) && !rt2x00_rf(rt2x00dev, RF2421)) {
1498 1499 1500 1501 1502 1503 1504
		ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
		return -ENODEV;
	}

	/*
	 * Identify default antenna configuration.
	 */
1505
	rt2x00dev->default_ant.tx =
1506
	    rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1507
	rt2x00dev->default_ant.rx =
1508 1509
	    rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);

1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520
	/*
	 * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
	 * I am not 100% sure about this, but the legacy drivers do not
	 * indicate antenna swapping in software is required when
	 * diversity is enabled.
	 */
	if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
		rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
	if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
		rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;

1521 1522 1523
	/*
	 * Store led mode, for correct led behaviour.
	 */
1524
#ifdef CONFIG_RT2X00_LIB_LEDS
1525 1526
	value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);

1527
	rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
1528 1529 1530
	if (value == LED_MODE_TXRX_ACTIVITY ||
	    value == LED_MODE_DEFAULT ||
	    value == LED_MODE_ASUS)
1531 1532
		rt2400pci_init_led(rt2x00dev, &rt2x00dev->led_qual,
				   LED_TYPE_ACTIVITY);
1533
#endif /* CONFIG_RT2X00_LIB_LEDS */
1534 1535 1536 1537 1538

	/*
	 * Detect if this device has an hardware controlled radio.
	 */
	if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1539
		__set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
1540 1541 1542 1543

	/*
	 * Check if the BBP tuning should be enabled.
	 */
1544
	if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1545
		__set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
1546 1547 1548 1549 1550 1551 1552 1553

	return 0;
}

/*
 * RF value list for RF2420 & RF2421
 * Supports: 2.4 GHz
 */
1554
static const struct rf_channel rf_vals_b[] = {
1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570
	{ 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
	{ 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
	{ 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
	{ 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
	{ 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
	{ 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
	{ 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
	{ 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
	{ 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
	{ 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
	{ 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
	{ 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
	{ 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
	{ 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
};

1571
static int rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1572 1573
{
	struct hw_mode_spec *spec = &rt2x00dev->spec;
1574 1575
	struct channel_info *info;
	char *tx_power;
1576 1577 1578 1579 1580
	unsigned int i;

	/*
	 * Initialize all hw fields.
	 */
1581
	rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1582 1583 1584
			       IEEE80211_HW_SIGNAL_DBM |
			       IEEE80211_HW_SUPPORTS_PS |
			       IEEE80211_HW_PS_NULLFUNC_STACK;
1585

1586
	SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
1587 1588 1589 1590 1591 1592 1593
	SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
				rt2x00_eeprom_addr(rt2x00dev,
						   EEPROM_MAC_ADDR_0));

	/*
	 * Initialize hw_mode information.
	 */
1594 1595
	spec->supported_bands = SUPPORT_BAND_2GHZ;
	spec->supported_rates = SUPPORT_RATE_CCK;
1596

1597 1598 1599 1600 1601 1602
	spec->num_channels = ARRAY_SIZE(rf_vals_b);
	spec->channels = rf_vals_b;

	/*
	 * Create channel information array
	 */
1603
	info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
1604 1605 1606 1607 1608 1609
	if (!info)
		return -ENOMEM;

	spec->channels_info = info;

	tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1610 1611 1612 1613
	for (i = 0; i < 14; i++) {
		info[i].max_power = TXPOWER_FROM_DEV(MAX_TXPOWER);
		info[i].default_power1 = TXPOWER_FROM_DEV(tx_power[i]);
	}
1614 1615

	return 0;
1616 1617 1618 1619 1620
}

static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
{
	int retval;
1621
	u32 reg;
1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633

	/*
	 * Allocate eeprom data.
	 */
	retval = rt2400pci_validate_eeprom(rt2x00dev);
	if (retval)
		return retval;

	retval = rt2400pci_init_eeprom(rt2x00dev);
	if (retval)
		return retval;

1634 1635 1636 1637 1638
	/*
	 * Enable rfkill polling by setting GPIO direction of the
	 * rfkill switch GPIO pin correctly.
	 */
	rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
1639
	rt2x00_set_field32(&reg, GPIOCSR_DIR0, 1);
1640 1641
	rt2x00pci_register_write(rt2x00dev, GPIOCSR, reg);

1642 1643 1644
	/*
	 * Initialize hw specifications.
	 */
1645 1646 1647
	retval = rt2400pci_probe_hw_mode(rt2x00dev);
	if (retval)
		return retval;
1648 1649

	/*
1650
	 * This device requires the atim queue and DMA-mapped skbs.
1651
	 */
1652 1653 1654
	__set_bit(REQUIRE_ATIM_QUEUE, &rt2x00dev->cap_flags);
	__set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
	__set_bit(REQUIRE_SW_SEQNO, &rt2x00dev->cap_flags);
1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666

	/*
	 * Set the rssi offset.
	 */
	rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;

	return 0;
}

/*
 * IEEE80211 stack callback functions.
 */
1667 1668
static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
			     struct ieee80211_vif *vif, u16 queue,
1669 1670 1671 1672 1673 1674 1675 1676 1677
			     const struct ieee80211_tx_queue_params *params)
{
	struct rt2x00_dev *rt2x00dev = hw->priv;

	/*
	 * We don't support variating cw_min and cw_max variables
	 * per queue. So by default we only configure the TX queue,
	 * and ignore all other configurations.
	 */
1678
	if (queue != 0)
1679 1680
		return -EINVAL;

1681
	if (rt2x00mac_conf_tx(hw, vif, queue, params))
1682 1683 1684 1685 1686
		return -EINVAL;

	/*
	 * Write configuration to register.
	 */
1687 1688
	rt2400pci_config_cw(rt2x00dev,
			    rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1689 1690 1691 1692

	return 0;
}

1693 1694
static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw,
			     struct ieee80211_vif *vif)
1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718
{
	struct rt2x00_dev *rt2x00dev = hw->priv;
	u64 tsf;
	u32 reg;

	rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
	tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
	rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
	tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);

	return tsf;
}

static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
{
	struct rt2x00_dev *rt2x00dev = hw->priv;
	u32 reg;

	rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
	return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
}

static const struct ieee80211_ops rt2400pci_mac80211_ops = {
	.tx			= rt2x00mac_tx,
1719 1720
	.start			= rt2x00mac_start,
	.stop			= rt2x00mac_stop,
1721 1722 1723
	.add_interface		= rt2x00mac_add_interface,
	.remove_interface	= rt2x00mac_remove_interface,
	.config			= rt2x00mac_config,
1724
	.configure_filter	= rt2x00mac_configure_filter,
1725 1726
	.sw_scan_start		= rt2x00mac_sw_scan_start,
	.sw_scan_complete	= rt2x00mac_sw_scan_complete,
1727
	.get_stats		= rt2x00mac_get_stats,
1728
	.bss_info_changed	= rt2x00mac_bss_info_changed,
1729 1730 1731
	.conf_tx		= rt2400pci_conf_tx,
	.get_tsf		= rt2400pci_get_tsf,
	.tx_last_beacon		= rt2400pci_tx_last_beacon,
1732
	.rfkill_poll		= rt2x00mac_rfkill_poll,
1733
	.flush			= rt2x00mac_flush,
1734 1735
	.set_antenna		= rt2x00mac_set_antenna,
	.get_antenna		= rt2x00mac_get_antenna,
1736
	.get_ringparam		= rt2x00mac_get_ringparam,
1737
	.tx_frames_pending	= rt2x00mac_tx_frames_pending,
1738 1739 1740 1741
};

static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
	.irq_handler		= rt2400pci_interrupt,
1742 1743 1744
	.txstatus_tasklet	= rt2400pci_txstatus_tasklet,
	.tbtt_tasklet		= rt2400pci_tbtt_tasklet,
	.rxdone_tasklet		= rt2400pci_rxdone_tasklet,
1745 1746 1747
	.probe_hw		= rt2400pci_probe_hw,
	.initialize		= rt2x00pci_initialize,
	.uninitialize		= rt2x00pci_uninitialize,
1748 1749
	.get_entry_state	= rt2400pci_get_entry_state,
	.clear_entry		= rt2400pci_clear_entry,
1750 1751 1752 1753 1754
	.set_device_state	= rt2400pci_set_device_state,
	.rfkill_poll		= rt2400pci_rfkill_poll,
	.link_stats		= rt2400pci_link_stats,
	.reset_tuner		= rt2400pci_reset_tuner,
	.link_tuner		= rt2400pci_link_tuner,
1755 1756 1757
	.start_queue		= rt2400pci_start_queue,
	.kick_queue		= rt2400pci_kick_queue,
	.stop_queue		= rt2400pci_stop_queue,
1758
	.flush_queue		= rt2x00pci_flush_queue,
1759
	.write_tx_desc		= rt2400pci_write_tx_desc,
1760
	.write_beacon		= rt2400pci_write_beacon,
1761
	.fill_rxdone		= rt2400pci_fill_rxdone,
1762
	.config_filter		= rt2400pci_config_filter,
1763
	.config_intf		= rt2400pci_config_intf,
1764
	.config_erp		= rt2400pci_config_erp,
1765
	.config_ant		= rt2400pci_config_ant,
1766 1767 1768
	.config			= rt2400pci_config,
};

1769
static const struct data_queue_desc rt2400pci_queue_rx = {
1770
	.entry_num		= 24,
1771 1772
	.data_size		= DATA_FRAME_SIZE,
	.desc_size		= RXD_DESC_SIZE,
1773
	.priv_size		= sizeof(struct queue_entry_priv_pci),
1774 1775 1776
};

static const struct data_queue_desc rt2400pci_queue_tx = {
1777
	.entry_num		= 24,
1778 1779
	.data_size		= DATA_FRAME_SIZE,
	.desc_size		= TXD_DESC_SIZE,
1780
	.priv_size		= sizeof(struct queue_entry_priv_pci),
1781 1782 1783
};

static const struct data_queue_desc rt2400pci_queue_bcn = {
1784
	.entry_num		= 1,
1785 1786
	.data_size		= MGMT_FRAME_SIZE,
	.desc_size		= TXD_DESC_SIZE,
1787
	.priv_size		= sizeof(struct queue_entry_priv_pci),
1788 1789 1790
};

static const struct data_queue_desc rt2400pci_queue_atim = {
1791
	.entry_num		= 8,
1792 1793
	.data_size		= DATA_FRAME_SIZE,
	.desc_size		= TXD_DESC_SIZE,
1794
	.priv_size		= sizeof(struct queue_entry_priv_pci),
1795 1796
};

1797
static const struct rt2x00_ops rt2400pci_ops = {
1798 1799 1800 1801 1802
	.name			= KBUILD_MODNAME,
	.max_ap_intf		= 1,
	.eeprom_size		= EEPROM_SIZE,
	.rf_size		= RF_SIZE,
	.tx_queues		= NUM_TX_QUEUES,
1803
	.extra_tx_headroom	= 0,
1804 1805 1806 1807 1808 1809
	.rx			= &rt2400pci_queue_rx,
	.tx			= &rt2400pci_queue_tx,
	.bcn			= &rt2400pci_queue_bcn,
	.atim			= &rt2400pci_queue_atim,
	.lib			= &rt2400pci_rt2x00_ops,
	.hw			= &rt2400pci_mac80211_ops,
1810
#ifdef CONFIG_RT2X00_LIB_DEBUGFS
1811
	.debugfs		= &rt2400pci_rt2x00debug,
1812 1813 1814 1815 1816 1817
#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
};

/*
 * RT2400pci module information.
 */
1818
static DEFINE_PCI_DEVICE_TABLE(rt2400pci_device_table) = {
1819
	{ PCI_DEVICE(0x1814, 0x0101) },
1820 1821 1822
	{ 0, }
};

1823

1824 1825 1826 1827 1828 1829 1830
MODULE_AUTHOR(DRV_PROJECT);
MODULE_VERSION(DRV_VERSION);
MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
MODULE_LICENSE("GPL");

1831 1832 1833 1834 1835 1836
static int rt2400pci_probe(struct pci_dev *pci_dev,
			   const struct pci_device_id *id)
{
	return rt2x00pci_probe(pci_dev, &rt2400pci_ops);
}

1837
static struct pci_driver rt2400pci_driver = {
1838
	.name		= KBUILD_MODNAME,
1839
	.id_table	= rt2400pci_device_table,
1840
	.probe		= rt2400pci_probe,
1841
	.remove		= rt2x00pci_remove,
1842 1843 1844 1845
	.suspend	= rt2x00pci_suspend,
	.resume		= rt2x00pci_resume,
};

1846
module_pci_driver(rt2400pci_driver);