This patch enables support for internal wm8940's PLL and proper
divider to set proper value for 256x fs clock.

This approach is more flexible and replaces hardcoded clock
values and makes the codec work with the simple-card driver.
Card drivers calling set_pll() and set_clkdiv() directly are
unaffected.

For the reference - code in this commit is based on:
51b2bb3f
("ASoC: wm8974: configure pll and mclk divider automatically")
Signed-off-by: Lukasz Majewski <lukma@denx.de>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20221216094624.3849278-2-lukma@denx.deSigned-off-by: Mark Brown <broonie@kernel.org>