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Luke Nelson authored
In BPF, 32-bit ALU operations should zero-extend their results into the 64-bit registers. The current BPF JIT on RISC-V emits incorrect instructions that perform sign extension only (e.g., addw, subw) on 32-bit add, sub, lsh, rsh, arsh, and neg. This behavior diverges from the interpreter and JITs for other architectures. This patch fixes the bugs by performing zero extension on the destination register of 32-bit ALU operations. Fixes: 2353ecc6 ("bpf, riscv: add BPF JIT for RV64G") Cc: Xi Wang <xi.wang@gmail.com> Signed-off-by:
Luke Nelson <luke.r.nels@gmail.com> Acked-by:
Song Liu <songliubraving@fb.com> Acked-by:
Björn Töpel <bjorn.topel@gmail.com> Reviewed-by:
Palmer Dabbelt <palmer@sifive.com> Signed-off-by:
Alexei Starovoitov <ast@kernel.org>
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