drivers/clk/tegra/clk-tegra-periph.c · 3d0f4e5f7a7c9ef2d8504f2b42f9c4d3233ba707 · Kirill Smelkov / linux

Thierry Reding authored Apr 20, 2015

The dpaux clock is derived from pll_p_out0 (pll_p), not clk_m.
Signed-off-by: Thierry Reding <treding@nvidia.com>

3d0f4e5f

clk-tegra-periph.c 43.7 KB