Although the DisplayPort spec explicitly calls out the 1.62/2.7/5.4/8.1
link rates, the value of LINK_BW_SET is calculated.  The DisplayPort
spec says "Main-Link Bandwidth Setting = Value x 0.27Gbps/lane".

A bridge that we're looking to upstream uses 6.75Gbps rate (value 0x19)
[1], and that precludes it from using these functions.

This 6.75Gbps rate is defined in the spec as (credit to Ville for posting this):
  A MyDP Source device, upon reading the MAX_LINK_RATE register of the
  downstream DPRX programmed to 19h (which can be the case only for a
  MyDP-to-Legacy or MyDP-to-DP lane count converter) can program the
  LINK_BW_SET register (DPCD Address 00100h) to 19h to enable 6.75Gbps/lane."

So to avoid failing on legitimate rates in the future, this patch calculates thevalues according to spec instead of restricting these values to one of the
DP_LINK_BW_* #defines.

No functional change for the well-defined values, but we lose the
warning (and return the correct value) for ill-defined bw values.
Signed-off-by: Sean Paul <seanpaul@chromium.org>

[1] https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/1689251/2/drivers/gpu/drm/bridge/analogix/anx7625.c#636Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20190717160148.256826-1-sean@poorly.run