• Vladimir Oltean's avatar
    net: mscc: ocelot: optimize ocelot_mm_irq() · 7bf4a5b0
    Vladimir Oltean authored
    The MAC Merge IRQ of all ports is shared with the PTP TX timestamp IRQ
    of all ports, which means that currently, when a PTP TX timestamp is
    generated, felix_irq_handler() also polls for the MAC Merge layer status
    of all ports, looking for changes. This makes the kernel do more work,
    and under certain circumstances may make ptp4l require a
    tx_timestamp_timeout argument higher than before.
    
    Changes to the MAC Merge layer status are only to be expected under
    certain conditions - its TX direction needs to be enabled - so we can
    check early if that is the case, and omit register access otherwise.
    
    Make ocelot_mm_update_port_status() skip register access if
    mm->tx_enabled is unset, and also call it once more, outside IRQ
    context, from ocelot_port_set_mm(), when mm->tx_enabled transitions from
    true to false, because an IRQ is also expected in that case.
    
    Also, a port may have its MAC Merge layer enabled but it may not have
    generated the interrupt. In that case, there's no point in writing to
    DEV_MM_STATUS to acknowledge that IRQ. We can reduce the number of
    register writes per port with MM enabled by keeping an "ack" variable
    which writes the "write-one-to-clear" bits. Those are 3 in number:
    PRMPT_ACTIVE_STICKY, UNEXP_RX_PFRM_STICKY and UNEXP_TX_PFRM_STICKY.
    The other fields in DEV_MM_STATUS are read-only and it doesn't matter
    what is written to them, so writing zero is just fine.
    Signed-off-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
    Reviewed-by: default avatarSimon Horman <simon.horman@corigine.com>
    Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
    Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
    7bf4a5b0
ocelot.h 35.7 KB