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  • Kirill Smelkov
  • linux
  • Repository
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  • linux
  • arch
  • x86
  • kernel
  • cpu
  • microcode
  • intel.c
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  • Ashok Raj's avatar
    x86/microcode/intel: Writeback and invalidate caches before updating microcode · 91df9fdf
    Ashok Raj authored Feb 28, 2018
    
    
    Updating microcode is less error prone when caches have been flushed and
    depending on what exactly the microcode is updating. For example, some
    of the issues around certain Broadwell parts can be addressed by doing a
    full cache flush.
    
    [ Borislav: Massage it and use native_wbinvd() in both cases. ]
    
    Signed-off-by: default avatarAshok Raj <ashok.raj@intel.com>
    Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
    Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
    Tested-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
    Tested-by: default avatarAshok Raj <ashok.raj@intel.com>
    Cc: Arjan Van De Ven <arjan.van.de.ven@intel.com>
    Link: http://lkml.kernel.org/r/1519352533-15992-3-git-send-email-ashok.raj@intel.com
    Link: https://lkml.kernel.org/r/20180228102846.13447-4-bp@alien8.de
    91df9fdf
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