• Charles Keepax's avatar
    spi: spi-cadence: Avoid read of RX FIFO before its ready · a84c11e1
    Charles Keepax authored
    Recent changes to cdns_spi_irq introduced some issues.
    
    Firstly, when writing the end of a longer transaction, the code in
    cdns_spi_irq will write data into the TX FIFO, then immediately
    fall into the if (!xspi->tx_bytes) path and attempt to read data
    from the RX FIFO. However this required waiting for the TX FIFO to
    empty before the RX data was ready.
    
    Secondly, the variable trans_cnt is now rather inaccurately named
    since in cases, where the watermark is set to 1, trans_cnt will be
    1 but the count of bytes transferred would be much longer.
    
    Finally, when setting up the transaction we set the watermark to 50%
    of the FIFO if the transaction is great than 50% of the FIFO. However,
    there is no need to split a tranaction that is smaller than the
    whole FIFO, so anything up to the FIFO size can be done in a single
    transaction.
    
    Tidy up the code a little, to avoid repeatedly calling
    cdns_spi_read_rx_fifo with a count of 1, and correct the three issues
    noted above.
    
    Fixes: b1b90514 ("spi: spi-cadence: Add support for Slave mode")
    Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com
    Link: https://lore.kernel.org/r/20230509164153.3907694-1-ckeepax@opensource.cirrus.com
    Signed-off-by: Mark Brown <broonie@kernel.org
    a84c11e1
spi-cadence.c 24.3 KB