The field PLLDIVVALUE of register PHY_CTRL_1 selects the reference clock source
for the PHY:
00 = sysclock uses 19.2 MHz
01 = sysclock uses 24 MHz
10 = sysclock uses 26 MHz
11 = sysclock uses 27 MHz

The reset value for this field is 10 according to the reference manual, and
even though this reset value works for mx53, it does not work for mx51.

So instead of relying on the reset value for the PLLDIVVALUE field, explicitly
set it to 01 so that a 24MHz clock can be selected for the PHY and allowing both
mx51 and mx53 to have USB OTG port functional.

Succesfully tested 'g_ether' on a imx51-babbage and on a imx53-qsb boards.
Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>