• Chris Wilson's avatar
    drm/i915: Add a delay between interrupt and inspecting the final seqno (ilk) · f8973c21
    Chris Wilson authored
    On Ironlake, there is no command nor register to ensure that the write
    from a MI_STORE command is completed (and coherent on the CPU) before the
    command parser continues. This means that the ordering between the seqno
    write and the subsequent user interrupt is undefined (like gen6+). So to
    ensure that the seqno write is completed after the final user interrupt
    we need to delay the read sufficiently to allow the write to complete.
    This delay is undefined by the bspec, and empirically requires 75us even
    though a register read combined with a clflush is less than 500ns. Hence,
    the delay is due to an on-chip buffer rather than the latency of the write
    to memory.
    
    Note that the render ring controls this by filling the PIPE_CONTROL fifo
    with stalling commands that force the earliest pipe-control with the
    seqno to be completed before the command parser continues. Given that we
    need a barrier operation for BSD, we may as well forgo the extra
    per-batch latency by using a common per-interrupt barrier.
    
    Studying the impact of adding the usleep shows that in both sequences of
    and individual synchronous no-op batches is negligible for the media
    engine (where the write now is unordered with the interrupt). Converting
    the render engine over from the current glutton of pie-controls over to
    the per-interrupt delays speeds up both the sequential and individual
    synchronous no-ops by 20% and 60%, respectively. This speed up holds
    even when looking at the throughput of small copies (4KiB->4MiB), both
    serial and synchronous, by about 20%. This is because despite adding a
    significant delay to the interrupt, in all likelihood we will see the
    seqno write without having to apply the barrier (only in the rare corner
    cases where the write is delayed on the last required is the delay
    necessary).
    
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94307
    Testcase: igt/gem_sync #ilk
    Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
    Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
    Link: http://patchwork.freedesktop.org/patch/msgid/1467390209-3576-12-git-send-email-chris@chris-wilson.co.uk
    f8973c21
intel_ringbuffer.c 86.8 KB