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Commit 03da89c5 authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo
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perf vendor events intel: Update Goldmont events to V12 

Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Link: https://lkml.kernel.org/r/20180118234518.GA27753@tassilo.jf.intel.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 97d00f2d
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tools/perf/pmu-events/arch/x86/goldmont/cache.json
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tools/perf/pmu-events/arch/x86/goldmont/memory.json
View file @ 03da89c5
[
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved - as another core is in the process of modifying the data.",
"EventCode": "0xC3",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"SampleAfterValue": "200003",
"BriefDescription": "Machine clears due to memory ordering issue"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
......@@ -30,5 +20,275 @@
"EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
"SampleAfterValue": "200003",
"BriefDescription": "Store uops that split a page (Precise event capable)"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts machine clears due to memory ordering issues. This occurs when a snoop request happens and the machine is uncertain if memory ordering will be preserved as another core is in the process of modifying the data.",
"EventCode": "0xC3",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"SampleAfterValue": "200003",
"BriefDescription": "Machine clears due to memory ordering issue"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x20000032b7 ",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts data read, code read, and read for ownership (RFO) requests (demand & prefetch) that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x2000000022 ",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts reads for ownership (RFO) requests (demand & prefetch) that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts data reads (demand & prefetch) that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x2000003091",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts data reads (demand & prefetch) that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x2000003010 ",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts data reads generated by L1 or L2 prefetchers that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts requests to the uncore subsystem that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x2000008000 ",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts requests to the uncore subsystem that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x2000004800 ",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts any data writes to uncacheable write combining (USWC) memory region that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x2000004000 ",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts partial cache line data writes to uncacheable write combining (USWC) memory region that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x2000002000 ",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts data cache line reads generated by hardware L1 data cache prefetcher that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x2000001000 ",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts data cache lines requests by software prefetch instructions that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x2000000800 ",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts full cache line data writes to uncacheable write combining (USWC) memory region and full cache-line non-temporal writes that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts bus lock and split lock requests that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x2000000400 ",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts bus lock and split lock requests that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts code reads in uncacheable (UC) memory region that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x2000000200 ",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.UC_CODE_RD.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts code reads in uncacheable (UC) memory region that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x2000000100 ",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts the number of demand write requests (RFO) generated by a write to partial data cache line, including the writes to uncacheable (UC) and write through (WT), and write protected (WP) types of memory that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x2000000080 ",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand data partial reads, including data in uncacheable (UC) or uncacheable write combining (USWC) memory types that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x2000000020 ",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts reads for ownership (RFO) requests generated by L2 prefetcher that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x2000000010 ",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts data cacheline reads generated by hardware L2 cache prefetcher that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x2000000008 ",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6",
"SampleAfterValue": "100007",
"BriefDescription": "Counts the number of writeback transactions caused by L1 or L2 cache evictions that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x2000000004 ",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand instruction cacheline and I-side prefetch requests that miss the instruction cache that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x2000000002 ",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand reads for ownership (RFO) requests generated by a write to full data cache line that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache and targets non-DRAM system address. Requires MSR_OFFCORE_RESP[0,1] to specify request type and response. (duplicated for both MSRs)",
"EventCode": "0xB7",
"MSRValue": "0x2000000001 ",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.NON_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"SampleAfterValue": "100007",
"BriefDescription": "Counts demand cacheable data reads of full cache lines that miss the L2 cache and targets non-DRAM system address.",
"Offcore": "1"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/goldmont/other.json
View file @ 03da89c5
[
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count.",
"EventCode": "0xCA",
"PublicDescription": "Counts cycles that fetch is stalled due to any reason. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes. This will include cycles due to an ITLB miss, ICache miss and other events.",
"EventCode": "0x86",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL",
"UMask": "0x0",
"EventName": "FETCH_STALL.ALL",
"SampleAfterValue": "200003",
"BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend"
"BriefDescription": "Cycles code-fetch stalled due to any reason."
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.",
"EventCode": "0xCA",
"PublicDescription": "Counts cycles that fetch is stalled due to an outstanding ITLB miss. That is, the decoder queue is able to accept bytes, but the fetch unit is unable to provide bytes due to an ITLB miss. Note: this event is not the same as page walk cycles to retrieve an instruction translation.",
"EventCode": "0x86",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY",
"UMask": "0x1",
"EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES",
"SampleAfterValue": "200003",
"BriefDescription": "Unfilled issue slots per cycle to recover"
"BriefDescription": "Cycles code-fetch stalled due to an outstanding ITLB miss."
},
{
"CollectPEBSRecord": "1",
......@@ -29,6 +29,26 @@
"SampleAfterValue": "200003",
"BriefDescription": "Unfilled issue slots per cycle"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed because of a full resource in the backend. Including but not limited to resources such as the Re-order Buffer (ROB), reservation stations (RS), load/store buffers, physical registers, or any other needed machine resource that is currently unavailable. Note that uops must be available for consumption in order for this event to fire. If a uop is not available (Instruction Queue is empty), this event will not count.",
"EventCode": "0xCA",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL",
"SampleAfterValue": "200003",
"BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by the backend because allocation is stalled waiting for a mispredicted jump to retire or other branch-like conditions (e.g. the event is relevant during certain microcode flows). Counts all issue slots blocked while within this window including slots where uops were not available in the Instruction Queue.",
"EventCode": "0xCA",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY",
"SampleAfterValue": "200003",
"BriefDescription": "Unfilled issue slots per cycle to recover"
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts hardware interrupts received by the processor.",
......@@ -36,8 +56,18 @@
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "HW_INTERRUPTS.RECEIVED",
"SampleAfterValue": "203",
"BriefDescription": "Hardware interrupts received"
},
{
"CollectPEBSRecord": "2",
"PublicDescription": "Counts the number of core cycles during which interrupts are masked (disabled). Increments by 1 each core cycle that EFLAGS.IF is 0, regardless of whether interrupts are pending or not.",
"EventCode": "0xCB",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "HW_INTERRUPTS.MASKED",
"SampleAfterValue": "200003",
"BriefDescription": "Hardware interrupts received (Precise event capable)"
"BriefDescription": "Cycles hardware interrupts are masked"
},
{
"CollectPEBSRecord": "2",
......@@ -47,6 +77,6 @@
"UMask": "0x4",
"EventName": "HW_INTERRUPTS.PENDING_AND_MASKED",
"SampleAfterValue": "200003",
"BriefDescription": "Cycles pending interrupts are masked (Precise event capable)"
"BriefDescription": "Cycles pending interrupts are masked"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/goldmont/pipeline.json
View file @ 03da89c5
[
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts branch instructions retired for all branch types. This is an architectural performance event.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x0",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "200003",
"BriefDescription": "Retired branch instructions (Precise event capable)"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x7e",
"EventName": "BR_INST_RETIRED.JCC",
"SampleAfterValue": "200003",
"BriefDescription": "Retired conditional branch instructions (Precise event capable)"
"PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event.",
"EventCode": "0x00",
"Counter": "Fixed counter 0",
"UMask": "0x1",
"EventName": "INST_RETIRED.ANY",
"SampleAfterValue": "2000003",
"BriefDescription": "Instructions retired (Fixed event)"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0xfe",
"EventName": "BR_INST_RETIRED.TAKEN_JCC",
"SampleAfterValue": "200003",
"BriefDescription": "Retired conditional branch instructions that were taken (Precise event capable)"
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. You cannot collect a PEBs record for this event.",
"EventCode": "0x00",
"Counter": "Fixed counter 1",
"UMask": "0x2",
"EventName": "CPU_CLK_UNHALTED.CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Core cycles when core is not halted (Fixed event)"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts near CALL branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0xf9",
"EventName": "BR_INST_RETIRED.CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Retired near call instructions (Precise event capable)"
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. This event uses fixed counter 2. You cannot collect a PEBs record for this event.",
"EventCode": "0x00",
"Counter": "Fixed counter 2",
"UMask": "0x3",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"SampleAfterValue": "2000003",
"BriefDescription": "Reference cycles when core is not halted (Fixed event)"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts near relative CALL branch instructions retired.",
"EventCode": "0xC4",
"PublicDescription": "Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time. The forward might occur subsequently when the data is available.",
"EventCode": "0x03",
"Counter": "0,1,2,3",
"UMask": "0xfd",
"EventName": "BR_INST_RETIRED.REL_CALL",
"UMask": "0x1",
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
"SampleAfterValue": "200003",
"BriefDescription": "Retired near relative call instructions (Precise event capable)"
"BriefDescription": "Loads blocked due to store data not ready (Precise event capable)"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts near indirect CALL branch instructions retired.",
"EventCode": "0xC4",
"PublicDescription": "Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted.",
"EventCode": "0x03",
"Counter": "0,1,2,3",
"UMask": "0xfb",
"EventName": "BR_INST_RETIRED.IND_CALL",
"UMask": "0x2",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"SampleAfterValue": "200003",
"BriefDescription": "Retired near indirect call instructions (Precise event capable)"
"BriefDescription": "Loads blocked due to store forward restriction (Precise event capable)"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts near return branch instructions retired.",
"EventCode": "0xC4",
"PublicDescription": "Counts loads that block because their address modulo 4K matches a pending store.",
"EventCode": "0x03",
"Counter": "0,1,2,3",
"UMask": "0xf7",
"EventName": "BR_INST_RETIRED.RETURN",
"UMask": "0x4",
"EventName": "LD_BLOCKS.4K_ALIAS",
"SampleAfterValue": "200003",
"BriefDescription": "Retired near return instructions (Precise event capable)"
"BriefDescription": "Loads blocked because address has 4k partial address false dependence (Precise event capable)"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts near indirect call or near indirect jmp branch instructions retired.",
"EventCode": "0xC4",
"PublicDescription": "Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB).",
"EventCode": "0x03",
"Counter": "0,1,2,3",
"UMask": "0xeb",
"EventName": "BR_INST_RETIRED.NON_RETURN_IND",
"UMask": "0x8",
"EventName": "LD_BLOCKS.UTLB_MISS",
"SampleAfterValue": "200003",
"BriefDescription": "Retired instructions of near indirect Jmp or call (Precise event capable)"
"BriefDescription": "Loads blocked because address in not in the UTLB (Precise event capable)"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts far branch instructions retired. This includes far jump, far call and return, and Interrupt call and return.",
"EventCode": "0xC4",
"PublicDescription": "Counts anytime a load that retires is blocked for any reason.",
"EventCode": "0x03",
"Counter": "0,1,2,3",
"UMask": "0xbf",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"UMask": "0x10",
"EventName": "LD_BLOCKS.ALL_BLOCK",
"SampleAfterValue": "200003",
"BriefDescription": "Retired far branch instructions (Precise event capable)"
"BriefDescription": "Loads blocked (Precise event capable)"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts mispredicted branch instructions retired including all branch types.",
"EventCode": "0xC5",
"CollectPEBSRecord": "1",
"PublicDescription": "Counts uops issued by the front end and allocated into the back end of the machine. This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear.",
"EventCode": "0x0E",
"Counter": "0,1,2,3",
"UMask": "0x0",
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "200003",
"BriefDescription": "Retired mispredicted branch instructions (Precise event capable)"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition).",
"EventCode": "0xC5",
"Counter": "0,1,2,3",
"UMask": "0x7e",
"EventName": "BR_MISP_RETIRED.JCC",
"EventName": "UOPS_ISSUED.ANY",
"SampleAfterValue": "200003",
"BriefDescription": "Retired mispredicted conditional branch instructions (Precise event capable)"
"BriefDescription": "Uops issued to the back end per cycle"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken.",
"EventCode": "0xC5",
"CollectPEBSRecord": "1",
"PublicDescription": "Core cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter.",
"EventCode": "0x3C",
"Counter": "0,1,2,3",
"UMask": "0xfe",
"EventName": "BR_MISP_RETIRED.TAKEN_JCC",
"SampleAfterValue": "200003",
"BriefDescription": "Retired mispredicted conditional branch instructions that were taken (Precise event capable)"
"UMask": "0x0",
"EventName": "CPU_CLK_UNHALTED.CORE_P",
"SampleAfterValue": "2000003",
"BriefDescription": "Core cycles when core is not halted"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted.",
"EventCode": "0xC5",
"CollectPEBSRecord": "1",
"PublicDescription": "Reference cycles when core is not halted. This event uses a programmable general purpose performance counter.",
"EventCode": "0x3C",
"Counter": "0,1,2,3",
"UMask": "0xfb",
"EventName": "BR_MISP_RETIRED.IND_CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Retired mispredicted near indirect call instructions (Precise event capable)"
"UMask": "0x1",
"EventName": "CPU_CLK_UNHALTED.REF",
"SampleAfterValue": "2000003",
"BriefDescription": "Reference cycles when core is not halted"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted.",
"EventCode": "0xC5",
"CollectPEBSRecord": "1",
"PublicDescription": "This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources. When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all. Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots. These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots. A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock. The low uop issue rate for a stream of INC instructions is considered to be a back end issue.",
"EventCode": "0x9C",
"Counter": "0,1,2,3",
"UMask": "0xf7",
"EventName": "BR_MISP_RETIRED.RETURN",
"UMask": "0x0",
"EventName": "UOPS_NOT_DELIVERED.ANY",
"SampleAfterValue": "200003",
"BriefDescription": "Retired mispredicted near return instructions (Precise event capable)"
"BriefDescription": "Uops requested but not-delivered to the back-end per cycle"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted.",
"EventCode": "0xC5",
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.",
"EventCode": "0xC0",
"Counter": "0,1,2,3",
"UMask": "0xeb",
"EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
"SampleAfterValue": "200003",
"BriefDescription": "Retired mispredicted instructions of near indirect Jmp or near indirect call. (Precise event capable)"
"UMask": "0x0",
"EventName": "INST_RETIRED.ANY_P",
"SampleAfterValue": "2000003",
"BriefDescription": "Instructions retired (Precise event capable)"
},
{
"PEBS": "2",
......@@ -186,9 +154,41 @@
"SampleAfterValue": "2000003",
"BriefDescription": "MS uops retired (Precise event capable)"
},
{
"PEBS": "2",
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of floating point divide uops retired.",
"EventCode": "0xC2",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "UOPS_RETIRED.FPDIV",
"SampleAfterValue": "2000003",
"BriefDescription": "Floating point divide uops retired. (Precise Event Capable)"
},
{
"PEBS": "2",
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of integer divide uops retired.",
"EventCode": "0xC2",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "UOPS_RETIRED.IDIV",
"SampleAfterValue": "2000003",
"BriefDescription": "Integer divide uops retired. (Precise Event Capable)"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel? architecture processors.",
"PublicDescription": "Counts machine clears for any reason.",
"EventCode": "0xC3",
"Counter": "0,1,2,3",
"UMask": "0x0",
"EventName": "MACHINE_CLEARS.ALL",
"SampleAfterValue": "200003",
"BriefDescription": "All machine clears"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel architecture processors.",
"EventCode": "0xC3",
"Counter": "0,1,2,3",
"UMask": "0x1",
......@@ -217,217 +217,239 @@
"BriefDescription": "Machine clears due to memory disambiguation"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts machine clears for any reason.",
"EventCode": "0xC3",
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts branch instructions retired for all branch types. This is an architectural performance event.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x0",
"EventName": "MACHINE_CLEARS.ALL",
"EventName": "BR_INST_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "200003",
"BriefDescription": "All machine clears"
"BriefDescription": "Retired branch instructions (Precise event capable)"
},
{
"PEBS": "2",
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The event continues counting during hardware interrupts, traps, and inside interrupt handlers. This is an architectural performance event. This event uses a (_P)rogrammable general purpose performance counter. *This event is Precise Event capable: The EventingRIP field in the PEBS record is precise to the address of the instruction which caused the event. Note: Because PEBS records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.",
"EventCode": "0xC0",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was taken and when it was not taken.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x0",
"EventName": "INST_RETIRED.ANY_P",
"SampleAfterValue": "2000003",
"BriefDescription": "Instructions retired (Precise event capable)"
"UMask": "0x7e",
"EventName": "BR_INST_RETIRED.JCC",
"SampleAfterValue": "200003",
"BriefDescription": "Retired conditional branch instructions (Precise event capable)"
},
{
"PEBS": "2",
"CollectPEBSRecord": "1",
"PublicDescription": "This event used to measure front-end inefficiencies. I.e. when front-end of the machine is not delivering uops to the back-end and the back-end has is not stalled. This event can be used to identify if the machine is truly front-end bound. When this event occurs, it is an indication that the front-end of the machine is operating at less than its theoretical peak performance. Background: We can think of the processor pipeline as being divided into 2 broader parts: Front-end and Back-end. Front-end is responsible for fetching the instruction, decoding into uops in machine understandable format and putting them into a uop queue to be consumed by back end. The back-end then takes these uops, allocates the required resources. When all resources are ready, uops are executed. If the back-end is not ready to accept uops from the front-end, then we do not want to count these as front-end bottlenecks. However, whenever we have bottlenecks in the back-end, we will have allocation unit stalls and eventually forcing the front-end to wait until the back-end is ready to receive more uops. This event counts only when back-end is requesting more uops and front-end is not able to provide them. When 3 uops are requested and no uops are delivered, the event counts 3. When 3 are requested, and only 1 is delivered, the event counts 2. When only 2 are delivered, the event counts 1. Alternatively stated, the event will not count if 3 uops are delivered, or if the back end is stalled and not requesting any uops at all. Counts indicate missed opportunities for the front-end to deliver a uop to the back end. Some examples of conditions that cause front-end efficiencies are: ICache misses, ITLB misses, and decoder restrictions that limit the front-end bandwidth. Known Issues: Some uops require multiple allocation slots. These uops will not be charged as a front end 'not delivered' opportunity, and will be regarded as a back end problem. For example, the INC instruction has one uop that requires 2 issue slots. A stream of INC instructions will not count as UOPS_NOT_DELIVERED, even though only one instruction can be issued per clock. The low uop issue rate for a stream of INC instructions is considered to be a back end issue.",
"EventCode": "0x9C",
"PublicDescription": "Counts the number of taken branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x0",
"EventName": "UOPS_NOT_DELIVERED.ANY",
"UMask": "0x80",
"EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES",
"SampleAfterValue": "200003",
"BriefDescription": "Uops requested but not-delivered to the back-end per cycle"
"BriefDescription": "Retired taken branch instructions (Precise event capable)"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts uops issued by the front end and allocated into the back end of the machine. This event counts uops that retire as well as uops that were speculatively executed but didn't retire. The sort of speculative uops that might be counted includes, but is not limited to those uops issued in the shadow of a miss-predicted branch, those uops that are inserted during an assist (such as for a denormal floating point result), and (previously allocated) uops that might be canceled during a machine clear.",
"EventCode": "0x0E",
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts far branch instructions retired. This includes far jump, far call and return, and Interrupt call and return.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x0",
"EventName": "UOPS_ISSUED.ANY",
"UMask": "0xbf",
"EventName": "BR_INST_RETIRED.FAR_BRANCH",
"SampleAfterValue": "200003",
"BriefDescription": "Uops issued to the back end per cycle"
"BriefDescription": "Retired far branch instructions (Precise event capable)"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts core cycles if either divide unit is busy.",
"EventCode": "0xCD",
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts near indirect call or near indirect jmp branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x0",
"EventName": "CYCLES_DIV_BUSY.ALL",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles a divider is busy"
"UMask": "0xeb",
"EventName": "BR_INST_RETIRED.NON_RETURN_IND",
"SampleAfterValue": "200003",
"BriefDescription": "Retired instructions of near indirect Jmp or call (Precise event capable)"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts core cycles the integer divide unit is busy.",
"EventCode": "0xCD",
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts near return branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "CYCLES_DIV_BUSY.IDIV",
"UMask": "0xf7",
"EventName": "BR_INST_RETIRED.RETURN",
"SampleAfterValue": "200003",
"BriefDescription": "Cycles the integer divide unit is busy"
"BriefDescription": "Retired near return instructions (Precise event capable)"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts core cycles the floating point divide unit is busy.",
"EventCode": "0xCD",
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts near CALL branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "CYCLES_DIV_BUSY.FPDIV",
"UMask": "0xf9",
"EventName": "BR_INST_RETIRED.CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Cycles the FP divide unit is busy"
"BriefDescription": "Retired near call instructions (Precise event capable)"
},
{
"PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event.",
"EventCode": "0x00",
"Counter": "Fixed counter 1",
"UMask": "0x1",
"EventName": "INST_RETIRED.ANY",
"SampleAfterValue": "2000003",
"BriefDescription": "Instructions retired (Fixed event)"
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts near indirect CALL branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0xfb",
"EventName": "BR_INST_RETIRED.IND_CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Retired near indirect call instructions (Precise event capable)"
},
{
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. You cannot collect a PEBs record for this event.",
"EventCode": "0x00",
"Counter": "Fixed counter 2",
"UMask": "0x2",
"EventName": "CPU_CLK_UNHALTED.CORE",
"SampleAfterValue": "2000003",
"BriefDescription": "Core cycles when core is not halted (Fixed event)"
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts near relative CALL branch instructions retired.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0xfd",
"EventName": "BR_INST_RETIRED.REL_CALL",
"SampleAfterValue": "200003",
"BriefDescription": "Retired near relative call instructions (Precise event capable)"
},
{
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. This event uses fixed counter 2. You cannot collect a PEBs record for this event.",
"EventCode": "0x00",
"Counter": "Fixed counter 3",
"UMask": "0x3",
"EventName": "CPU_CLK_UNHALTED.REF_TSC",
"SampleAfterValue": "2000003",
"BriefDescription": "Reference cycles when core is not halted (Fixed event)"
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were taken and does not count when the Jcc branch instruction were not taken.",
"EventCode": "0xC4",
"Counter": "0,1,2,3",
"UMask": "0xfe",
"EventName": "BR_INST_RETIRED.TAKEN_JCC",
"SampleAfterValue": "200003",
"BriefDescription": "Retired conditional branch instructions that were taken (Precise event capable)"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Core cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter.",
"EventCode": "0x3C",
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts mispredicted branch instructions retired including all branch types.",
"EventCode": "0xC5",
"Counter": "0,1,2,3",
"UMask": "0x0",
"EventName": "CPU_CLK_UNHALTED.CORE_P",
"SampleAfterValue": "2000003",
"BriefDescription": "Core cycles when core is not halted"
"EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
"SampleAfterValue": "200003",
"BriefDescription": "Retired mispredicted branch instructions (Precise event capable)"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Reference cycles when core is not halted. This event uses a (_P)rogrammable general purpose performance counter.",
"EventCode": "0x3C",
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired, including both when the branch was supposed to be taken and when it was not supposed to be taken (but the processor predicted the opposite condition).",
"EventCode": "0xC5",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "CPU_CLK_UNHALTED.REF",
"SampleAfterValue": "2000003",
"BriefDescription": "Reference cycles when core is not halted"
"UMask": "0x7e",
"EventName": "BR_MISP_RETIRED.JCC",
"SampleAfterValue": "200003",
"BriefDescription": "Retired mispredicted conditional branch instructions (Precise event capable)"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call, Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns.",
"EventCode": "0xE6",
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts mispredicted branch instructions retired that were near indirect call or near indirect jmp, where the target address taken was not what the processor predicted.",
"EventCode": "0xC5",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "BACLEARS.ALL",
"UMask": "0xeb",
"EventName": "BR_MISP_RETIRED.NON_RETURN_IND",
"SampleAfterValue": "200003",
"BriefDescription": "BACLEARs asserted for any branch type"
"BriefDescription": "Retired mispredicted instructions of near indirect Jmp or near indirect call. (Precise event capable)"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts BACLEARS on return instructions.",
"EventCode": "0xE6",
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts mispredicted near RET branch instructions retired, where the return address taken was not what the processor predicted.",
"EventCode": "0xC5",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "BACLEARS.RETURN",
"UMask": "0xf7",
"EventName": "BR_MISP_RETIRED.RETURN",
"SampleAfterValue": "200003",
"BriefDescription": "BACLEARs asserted for return branch"
"BriefDescription": "Retired mispredicted near return instructions (Precise event capable)"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches.",
"EventCode": "0xE6",
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts mispredicted near indirect CALL branch instructions retired, where the target address taken was not what the processor predicted.",
"EventCode": "0xC5",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "BACLEARS.COND",
"UMask": "0xfb",
"EventName": "BR_MISP_RETIRED.IND_CALL",
"SampleAfterValue": "200003",
"BriefDescription": "BACLEARs asserted for conditional branch"
"BriefDescription": "Retired mispredicted near indirect call instructions (Precise event capable)"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts anytime a load that retires is blocked for any reason.",
"EventCode": "0x03",
"PublicDescription": "Counts mispredicted retired Jcc (Jump on Conditional Code/Jump if Condition is Met) branch instructions retired that were supposed to be taken but the processor predicted that it would not be taken.",
"EventCode": "0xC5",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "LD_BLOCKS.ALL_BLOCK",
"UMask": "0xfe",
"EventName": "BR_MISP_RETIRED.TAKEN_JCC",
"SampleAfterValue": "200003",
"BriefDescription": "Loads blocked (Precise event capable)"
"BriefDescription": "Retired mispredicted conditional branch instructions that were taken (Precise event capable)"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts loads blocked because they are unable to find their physical address in the micro TLB (UTLB).",
"EventCode": "0x03",
"CollectPEBSRecord": "1",
"PublicDescription": "Counts core cycles if either divide unit is busy.",
"EventCode": "0xCD",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "LD_BLOCKS.UTLB_MISS",
"UMask": "0x0",
"EventName": "CYCLES_DIV_BUSY.ALL",
"SampleAfterValue": "2000003",
"BriefDescription": "Cycles a divider is busy"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts core cycles the integer divide unit is busy.",
"EventCode": "0xCD",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "CYCLES_DIV_BUSY.IDIV",
"SampleAfterValue": "200003",
"BriefDescription": "Loads blocked because address in not in the UTLB (Precise event capable)"
"BriefDescription": "Cycles the integer divide unit is busy"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts a load blocked from using a store forward because of an address/size mismatch, only one of the loads blocked from each store will be counted.",
"EventCode": "0x03",
"CollectPEBSRecord": "1",
"PublicDescription": "Counts core cycles the floating point divide unit is busy.",
"EventCode": "0xCD",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "LD_BLOCKS.STORE_FORWARD",
"EventName": "CYCLES_DIV_BUSY.FPDIV",
"SampleAfterValue": "200003",
"BriefDescription": "Loads blocked due to store forward restriction (Precise event capable)"
"BriefDescription": "Cycles the FP divide unit is busy"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts a load blocked from using a store forward, but did not occur because the store data was not available at the right time. The forward might occur subsequently when the data is available.",
"EventCode": "0x03",
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of times a BACLEAR is signaled for any reason, including, but not limited to indirect branch/call, Jcc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditional branch/call, and returns.",
"EventCode": "0xE6",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "LD_BLOCKS.DATA_UNKNOWN",
"EventName": "BACLEARS.ALL",
"SampleAfterValue": "200003",
"BriefDescription": "Loads blocked due to store data not ready (Precise event capable)"
"BriefDescription": "BACLEARs asserted for any branch type"
},
{
"PEBS": "2",
"CollectPEBSRecord": "2",
"PublicDescription": "Counts loads that block because their address modulo 4K matches a pending store.",
"EventCode": "0x03",
"CollectPEBSRecord": "1",
"PublicDescription": "Counts BACLEARS on return instructions.",
"EventCode": "0xE6",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "LD_BLOCKS.4K_ALIAS",
"UMask": "0x8",
"EventName": "BACLEARS.RETURN",
"SampleAfterValue": "200003",
"BriefDescription": "Loads blocked because address has 4k partial address false dependence (Precise event capable)"
"BriefDescription": "BACLEARs asserted for return branch"
},
{
"PEBS": "2",
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of taken branch instructions retired.",
"EventCode": "0xC4",
"PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional Code/Jump if Condition is Met) branches.",
"EventCode": "0xE6",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES",
"UMask": "0x10",
"EventName": "BACLEARS.COND",
"SampleAfterValue": "200003",
"BriefDescription": "Retired taken branch instructions (Precise event capable)"
"BriefDescription": "BACLEARs asserted for conditional branch"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json
View file @ 03da89c5
[
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts every core cycle when a Data-side (walks due to a data operation) page walk is in progress.",
"EventCode": "0x05",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
"SampleAfterValue": "200003",
"BriefDescription": "Duration of D-side page-walks in cycles"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progress.",
"EventCode": "0x05",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
"SampleAfterValue": "200003",
"BriefDescription": "Duration of I-side pagewalks in cycles"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetch.",
"EventCode": "0x05",
"Counter": "0,1,2,3",
"UMask": "0x3",
"EventName": "PAGE_WALKS.CYCLES",
"SampleAfterValue": "200003",
"BriefDescription": "Duration of page-walks in cycles"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of times the machine was unable to find a translation in the Instruction Translation Lookaside Buffer (ITLB) for a linear address of an instruction fetch. It counts when new translation are filled into the ITLB. The event is speculative in nature, but will not count translations (page walks) that are begun and not finished, or translations that are finished but not filled into the ITLB.",
......@@ -41,35 +71,5 @@
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS",
"SampleAfterValue": "200003",
"BriefDescription": "Memory uops retired that missed the DTLB (Precise event capable)"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts every core cycle when a Data-side (walks due to a data operation) page walk is in progress.",
"EventCode": "0x05",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "PAGE_WALKS.D_SIDE_CYCLES",
"SampleAfterValue": "200003",
"BriefDescription": "Duration of D-side page-walks in cycles"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts every core cycle when a Instruction-side (walks due to an instruction fetch) page walk is in progress.",
"EventCode": "0x05",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "PAGE_WALKS.I_SIDE_CYCLES",
"SampleAfterValue": "200003",
"BriefDescription": "Duration of I-side pagewalks in cycles"
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts every core cycle a page-walk is in progress due to either a data memory operation or an instruction fetch.",
"EventCode": "0x05",
"Counter": "0,1,2,3",
"UMask": "0x3",
"EventName": "PAGE_WALKS.CYCLES",
"SampleAfterValue": "200003",
"BriefDescription": "Duration of page-walks in cycles"
}
]
\ No newline at end of file
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