Commit 0cd75e4f authored by Hsuan Hung's avatar Hsuan Hung Committed by Kalle Valo

rtw89: 8852c: add settings to decrease the effect of DC

Modify NBI and PD boost settings according to different primary channels.
This setting can decrease the false alarm induced by DC.
Signed-off-by: default avatarHsuan Hung <hsuan8331@realtek.com>
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220506120216.58567-2-pkshih@realtek.com
parent 84dc992e
...@@ -3822,6 +3822,8 @@ ...@@ -3822,6 +3822,8 @@
#define B_CHBW_MOD_SBW GENMASK(13, 12) #define B_CHBW_MOD_SBW GENMASK(13, 12)
#define B_CHBW_MOD_PRICH GENMASK(11, 8) #define B_CHBW_MOD_PRICH GENMASK(11, 8)
#define B_ANT_RX_SEG0 GENMASK(3, 0) #define B_ANT_RX_SEG0 GENMASK(3, 0)
#define R_PD_BOOST_EN 0x49E8
#define B_PD_BOOST_EN BIT(7)
#define R_P1_BACKOFF_IBADC_V1 0x49F0 #define R_P1_BACKOFF_IBADC_V1 0x49F0
#define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26) #define B_P1_BACKOFF_IBADC_V1 GENMASK(31, 26)
#define R_BK_FC0_INV_V1 0x4A1C #define R_BK_FC0_INV_V1 0x4A1C
...@@ -3840,6 +3842,12 @@ ...@@ -3840,6 +3842,12 @@
#define B_PATH1_BT_BACKOFF_V1 GENMASK(23, 0) #define B_PATH1_BT_BACKOFF_V1 GENMASK(23, 0)
#define R_PATH0_FRC_FIR_TYPE_V1 0x4C00 #define R_PATH0_FRC_FIR_TYPE_V1 0x4C00
#define B_PATH0_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0) #define B_PATH0_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)
#define R_PATH0_NOTCH 0x4C14
#define B_PATH0_NOTCH_EN BIT(12)
#define B_PATH0_NOTCH_VAL GENMASK(11, 0)
#define R_PATH0_NOTCH2 0x4C20
#define B_PATH0_NOTCH2_EN BIT(12)
#define B_PATH0_NOTCH2_VAL GENMASK(11, 0)
#define R_PATH0_5MDET 0x4C4C #define R_PATH0_5MDET 0x4C4C
#define B_PATH0_5MDET_EN BIT(12) #define B_PATH0_5MDET_EN BIT(12)
#define B_PATH0_5MDET_SB2 BIT(8) #define B_PATH0_5MDET_SB2 BIT(8)
...@@ -3847,6 +3855,12 @@ ...@@ -3847,6 +3855,12 @@
#define B_PATH0_5MDET_TH GENMASK(5, 0) #define B_PATH0_5MDET_TH GENMASK(5, 0)
#define R_PATH1_FRC_FIR_TYPE_V1 0x4CC4 #define R_PATH1_FRC_FIR_TYPE_V1 0x4CC4
#define B_PATH1_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0) #define B_PATH1_FRC_FIR_TYPE_MSK_V1 GENMASK(1, 0)
#define R_PATH1_NOTCH 0x4CD8
#define B_PATH1_NOTCH_EN BIT(12)
#define B_PATH1_NOTCH_VAL GENMASK(11, 0)
#define R_PATH1_NOTCH2 0x4CE4
#define B_PATH1_NOTCH2_EN BIT(12)
#define B_PATH1_NOTCH2_VAL GENMASK(11, 0)
#define R_PATH1_5MDET 0x4D10 #define R_PATH1_5MDET 0x4D10
#define B_PATH1_5MDET_EN BIT(12) #define B_PATH1_5MDET_EN BIT(12)
#define B_PATH1_5MDET_SB2 BIT(8) #define B_PATH1_5MDET_SB2 BIT(8)
......
...@@ -1381,19 +1381,72 @@ static void rtw8852c_set_nbi_tone_idx(struct rtw89_dev *rtwdev, ...@@ -1381,19 +1381,72 @@ static void rtw8852c_set_nbi_tone_idx(struct rtw89_dev *rtwdev,
} }
} }
static void rtw8852c_spur_notch(struct rtw89_dev *rtwdev, u32 val,
enum rtw89_phy_idx phy_idx)
{
u32 notch;
u32 notch2;
if (phy_idx == RTW89_PHY_0) {
notch = R_PATH0_NOTCH;
notch2 = R_PATH0_NOTCH2;
} else {
notch = R_PATH1_NOTCH;
notch2 = R_PATH1_NOTCH2;
}
rtw89_phy_write32_mask(rtwdev, notch,
B_PATH0_NOTCH_VAL | B_PATH0_NOTCH_EN, val);
rtw89_phy_write32_set(rtwdev, notch, B_PATH0_NOTCH_EN);
rtw89_phy_write32_mask(rtwdev, notch2,
B_PATH0_NOTCH2_VAL | B_PATH0_NOTCH2_EN, val);
rtw89_phy_write32_set(rtwdev, notch2, B_PATH0_NOTCH2_EN);
}
static void rtw8852c_spur_elimination(struct rtw89_dev *rtwdev, static void rtw8852c_spur_elimination(struct rtw89_dev *rtwdev,
struct rtw89_channel_params *param, struct rtw89_channel_params *param,
u8 pri_ch_idx,
enum rtw89_phy_idx phy_idx) enum rtw89_phy_idx phy_idx)
{ {
rtw8852c_set_csi_tone_idx(rtwdev, param, phy_idx); rtw8852c_set_csi_tone_idx(rtwdev, param, phy_idx);
if (phy_idx == RTW89_PHY_0) { if (phy_idx == RTW89_PHY_0) {
rtw8852c_set_nbi_tone_idx(rtwdev, param, RF_PATH_A); if (param->bandwidth == RTW89_CHANNEL_WIDTH_160 &&
if (!rtwdev->dbcc_en) (pri_ch_idx == RTW89_SC_20_LOWER ||
rtw8852c_set_nbi_tone_idx(rtwdev, param, RF_PATH_B); pri_ch_idx == RTW89_SC_20_UP3X)) {
rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_0);
if (!rtwdev->dbcc_en)
rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1);
} else if (param->bandwidth == RTW89_CHANNEL_WIDTH_160 &&
(pri_ch_idx == RTW89_SC_20_UPPER ||
pri_ch_idx == RTW89_SC_20_LOW3X)) {
rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_0);
if (!rtwdev->dbcc_en)
rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1);
} else {
rtw8852c_set_nbi_tone_idx(rtwdev, param, RF_PATH_A);
if (!rtwdev->dbcc_en)
rtw8852c_set_nbi_tone_idx(rtwdev, param,
RF_PATH_B);
}
} else { } else {
rtw8852c_set_nbi_tone_idx(rtwdev, param, RF_PATH_B); if (param->bandwidth == RTW89_CHANNEL_WIDTH_160 &&
(pri_ch_idx == RTW89_SC_20_LOWER ||
pri_ch_idx == RTW89_SC_20_UP3X)) {
rtw8852c_spur_notch(rtwdev, 0xe7f, RTW89_PHY_1);
} else if (param->bandwidth == RTW89_CHANNEL_WIDTH_160 &&
(pri_ch_idx == RTW89_SC_20_UPPER ||
pri_ch_idx == RTW89_SC_20_LOW3X)) {
rtw8852c_spur_notch(rtwdev, 0x280, RTW89_PHY_1);
} else {
rtw8852c_set_nbi_tone_idx(rtwdev, param, RF_PATH_B);
}
} }
if (pri_ch_idx == RTW89_SC_20_UP3X || pri_ch_idx == RTW89_SC_20_LOW3X)
rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 0, phy_idx);
else
rtw89_phy_write32_idx(rtwdev, R_PD_BOOST_EN, B_PD_BOOST_EN, 1, phy_idx);
} }
static void rtw8852c_5m_mask(struct rtw89_dev *rtwdev, static void rtw8852c_5m_mask(struct rtw89_dev *rtwdev,
...@@ -1664,7 +1717,7 @@ static void rtw8852c_set_channel_bb(struct rtw89_dev *rtwdev, ...@@ -1664,7 +1717,7 @@ static void rtw8852c_set_channel_bb(struct rtw89_dev *rtwdev,
B_PD_ARBITER_OFF, 0x1, phy_idx); B_PD_ARBITER_OFF, 0x1, phy_idx);
} }
rtw8852c_spur_elimination(rtwdev, param, phy_idx); rtw8852c_spur_elimination(rtwdev, param, pri_ch_idx, phy_idx);
rtw8852c_ctrl_btg(rtwdev, param->band_type == RTW89_BAND_2G); rtw8852c_ctrl_btg(rtwdev, param->band_type == RTW89_BAND_2G);
rtw8852c_5m_mask(rtwdev, param, phy_idx); rtw8852c_5m_mask(rtwdev, param, phy_idx);
......
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