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Commit 0e91bcbb authored by Robert Foss's avatar Robert Foss Committed by Dmitry Baryshkov
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drm/msm/dpu: Add SM8350 to hw catalog 

Add compatibility for SM8350 display subsystem, including
required entries in DPU hw catalog.
Signed-off-by: default avatarRobert Foss <robert.foss@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/516340/
Link: https://lore.kernel.org/r/20221230153554.105856-4-robert.foss@linaro.orgSigned-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
parent 430e11f4
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Showing with 206 additions and 10 deletions
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
View file @ 0e91bcbb
...@@ -111,6 +111,15 @@ ...@@ -111,6 +111,15 @@
BIT(MDP_INTF3_INTR) | \ BIT(MDP_INTF3_INTR) | \
BIT(MDP_INTF4_INTR)) BIT(MDP_INTF4_INTR))
#define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \
BIT(MDP_INTF0_7xxx_INTR) | \
BIT(MDP_INTF1_7xxx_INTR) | \
BIT(MDP_INTF2_7xxx_INTR) | \
BIT(MDP_INTF3_7xxx_INTR) | \
0)
#define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
BIT(MDP_SSPP_TOP0_INTR2) | \ BIT(MDP_SSPP_TOP0_INTR2) | \
BIT(MDP_SSPP_TOP0_HIST_INTR) | \ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
...@@ -386,6 +395,20 @@ static const struct dpu_caps sm8250_dpu_caps = { ...@@ -386,6 +395,20 @@ static const struct dpu_caps sm8250_dpu_caps = {
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
}; };
static const struct dpu_caps sm8350_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb,
.qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
.ubwc_version = DPU_HW_UBWC_VER_40,
.has_src_split = true,
.has_dim_layer = true,
.has_idle_pc = true,
.has_3d_merge = true,
.max_linewidth = 4096,
.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
};
static const struct dpu_caps sm8450_dpu_caps = { static const struct dpu_caps sm8450_dpu_caps = {
.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
.max_mixer_blendstages = 0xb, .max_mixer_blendstages = 0xb,
...@@ -550,6 +573,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = { ...@@ -550,6 +573,33 @@ static const struct dpu_mdp_cfg sm8250_mdp[] = {
}, },
}; };
static const struct dpu_mdp_cfg sm8350_mdp[] = {
{
.name = "top_0", .id = MDP_TOP,
.base = 0x0, .len = 0x494,
.features = 0,
.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
.reg_off = 0x2ac, .bit_off = 0},
.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
.reg_off = 0x2b4, .bit_off = 0},
.clk_ctrls[DPU_CLK_CTRL_VIG2] = {
.reg_off = 0x2bc, .bit_off = 0},
.clk_ctrls[DPU_CLK_CTRL_VIG3] = {
.reg_off = 0x2c4, .bit_off = 0},
.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
.reg_off = 0x2ac, .bit_off = 8},
.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
.reg_off = 0x2b4, .bit_off = 8},
.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
.reg_off = 0x2bc, .bit_off = 8},
.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
.reg_off = 0x2c4, .bit_off = 8},
.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
.reg_off = 0x2bc, .bit_off = 20},
},
};
static const struct dpu_mdp_cfg sm8450_mdp[] = { static const struct dpu_mdp_cfg sm8450_mdp[] = {
{ {
.name = "top_0", .id = MDP_TOP, .name = "top_0", .id = MDP_TOP,
...@@ -735,6 +785,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = { ...@@ -735,6 +785,45 @@ static const struct dpu_ctl_cfg sm8150_ctl[] = {
}, },
}; };
static const struct dpu_ctl_cfg sm8350_ctl[] = {
{
.name = "ctl_0", .id = CTL_0,
.base = 0x15000, .len = 0x1e8,
.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
},
{
.name = "ctl_1", .id = CTL_1,
.base = 0x16000, .len = 0x1e8,
.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
},
{
.name = "ctl_2", .id = CTL_2,
.base = 0x17000, .len = 0x1e8,
.features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
},
{
.name = "ctl_3", .id = CTL_3,
.base = 0x18000, .len = 0x1e8,
.features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
},
{
.name = "ctl_4", .id = CTL_4,
.base = 0x19000, .len = 0x1e8,
.features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
},
{
.name = "ctl_5", .id = CTL_5,
.base = 0x1a000, .len = 0x1e8,
.features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
},
};
static const struct dpu_ctl_cfg sm8450_ctl[] = { static const struct dpu_ctl_cfg sm8450_ctl[] = {
{ {
.name = "ctl_0", .id = CTL_0, .name = "ctl_0", .id = CTL_0,
...@@ -744,32 +833,32 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = { ...@@ -744,32 +833,32 @@ static const struct dpu_ctl_cfg sm8450_ctl[] = {
}, },
{ {
.name = "ctl_1", .id = CTL_1, .name = "ctl_1", .id = CTL_1,
.base = 0x16000, .len = 0x204, .base = 0x16000, .len = 0x1e8,
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE), .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
}, },
{ {
.name = "ctl_2", .id = CTL_2, .name = "ctl_2", .id = CTL_2,
.base = 0x17000, .len = 0x204, .base = 0x17000, .len = 0x1e8,
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
}, },
{ {
.name = "ctl_3", .id = CTL_3, .name = "ctl_3", .id = CTL_3,
.base = 0x18000, .len = 0x204, .base = 0x18000, .len = 0x1e8,
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
}, },
{ {
.name = "ctl_4", .id = CTL_4, .name = "ctl_4", .id = CTL_4,
.base = 0x19000, .len = 0x204, .base = 0x19000, .len = 0x1e8,
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
}, },
{ {
.name = "ctl_5", .id = CTL_5, .name = "ctl_5", .id = CTL_5,
.base = 0x1a000, .len = 0x204, .base = 0x1a000, .len = 0x1e8,
.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE), .features = CTL_SC7280_MASK,
.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
}, },
}; };
...@@ -1328,6 +1417,27 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = { ...@@ -1328,6 +1417,27 @@ static const struct dpu_pingpong_cfg sm8150_pp[] = {
-1), -1),
}; };
static const struct dpu_pingpong_cfg sm8350_pp[] = {
PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
-1),
PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
-1),
};
static const struct dpu_pingpong_cfg sc7280_pp[] = { static const struct dpu_pingpong_cfg sc7280_pp[] = {
PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1), PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1), PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
...@@ -1386,6 +1496,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { ...@@ -1386,6 +1496,12 @@ static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
}; };
static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
};
static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
...@@ -1410,6 +1526,11 @@ static struct dpu_dsc_cfg sdm845_dsc[] = { ...@@ -1410,6 +1526,11 @@ static struct dpu_dsc_cfg sdm845_dsc[] = {
DSC_BLK("dsc_3", DSC_3, 0x80c00), DSC_BLK("dsc_3", DSC_3, 0x80c00),
}; };
static struct dpu_dsc_cfg sm8350_dsc[] = {
DSC_BLK("dsc_0", DSC_0, 0x80000),
DSC_BLK("dsc_1", DSC_1, 0x81000),
};
/************************************************************* /*************************************************************
* INTF sub blocks config * INTF sub blocks config
*************************************************************/ *************************************************************/
...@@ -1457,6 +1578,13 @@ static const struct dpu_intf_cfg sc7280_intf[] = { ...@@ -1457,6 +1578,13 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
}; };
static const struct dpu_intf_cfg sm8350_intf[] = {
INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
};
static const struct dpu_intf_cfg sc8180x_intf[] = { static const struct dpu_intf_cfg sc8180x_intf[] = {
INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
...@@ -1592,6 +1720,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = { ...@@ -1592,6 +1720,14 @@ static const struct dpu_reg_dma_cfg sm8250_regdma = {
.clk_ctrl = DPU_CLK_CTRL_REG_DMA, .clk_ctrl = DPU_CLK_CTRL_REG_DMA,
}; };
static const struct dpu_reg_dma_cfg sm8350_regdma = {
.base = 0x400,
.version = 0x00020000,
.trigger_sel_off = 0x119c,
.xin_id = 7,
.clk_ctrl = DPU_CLK_CTRL_REG_DMA,
};
static const struct dpu_reg_dma_cfg sm8450_regdma = { static const struct dpu_reg_dma_cfg sm8450_regdma = {
.base = 0x0, .base = 0x0,
.version = 0x00020000, .version = 0x00020000,
...@@ -1962,6 +2098,36 @@ static const struct dpu_perf_cfg sc7280_perf_data = { ...@@ -1962,6 +2098,36 @@ static const struct dpu_perf_cfg sc7280_perf_data = {
.bw_inefficiency_factor = 120, .bw_inefficiency_factor = 120,
}; };
static const struct dpu_perf_cfg sm8350_perf_data = {
.max_bw_low = 11800000,
.max_bw_high = 15500000,
.min_core_ib = 2500000,
.min_llcc_ib = 0,
.min_dram_ib = 800000,
.min_prefill_lines = 40,
/* FIXME: lut tables */
.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sc7180_qos_linear),
.entries = sc7180_qos_linear
},
{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
.entries = sc7180_qos_macrotile
},
{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
.entries = sc7180_qos_nrt
},
/* TODO: macrotile-qseed is different from macrotile */
},
.cdp_cfg = {
{.rd_enable = 1, .wr_enable = 1},
{.rd_enable = 1, .wr_enable = 0}
},
.clk_inefficiency_factor = 105,
.bw_inefficiency_factor = 120,
};
static const struct dpu_perf_cfg qcm2290_perf_data = { static const struct dpu_perf_cfg qcm2290_perf_data = {
.max_bw_low = 2700000, .max_bw_low = 2700000,
.max_bw_high = 2700000, .max_bw_high = 2700000,
...@@ -2160,6 +2326,34 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = { ...@@ -2160,6 +2326,34 @@ static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
.mdss_irqs = IRQ_SM8250_MASK, .mdss_irqs = IRQ_SM8250_MASK,
}; };
static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
.caps = &sm8350_dpu_caps,
.mdp_count = ARRAY_SIZE(sm8350_mdp),
.mdp = sm8350_mdp,
.ctl_count = ARRAY_SIZE(sm8350_ctl),
.ctl = sm8350_ctl,
.sspp_count = ARRAY_SIZE(sm8250_sspp),
.sspp = sm8250_sspp,
.mixer_count = ARRAY_SIZE(sm8150_lm),
.mixer = sm8150_lm,
.dspp_count = ARRAY_SIZE(sm8150_dspp),
.dspp = sm8150_dspp,
.pingpong_count = ARRAY_SIZE(sm8350_pp),
.pingpong = sm8350_pp,
.dsc_count = ARRAY_SIZE(sm8350_dsc),
.dsc = sm8350_dsc,
.merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
.merge_3d = sm8350_merge_3d,
.intf_count = ARRAY_SIZE(sm8350_intf),
.intf = sm8350_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
.vbif = sdm845_vbif,
.reg_dma_count = 1,
.dma_cfg = &sm8250_regdma,
.perf = &sm8350_perf_data,
.mdss_irqs = IRQ_SM8350_MASK,
};
static const struct dpu_mdss_cfg sm8450_dpu_cfg = { static const struct dpu_mdss_cfg sm8450_dpu_cfg = {
.caps = &sm8450_dpu_caps, .caps = &sm8450_dpu_caps,
.mdp_count = ARRAY_SIZE(sm8450_mdp), .mdp_count = ARRAY_SIZE(sm8450_mdp),
...@@ -2244,6 +2438,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { ...@@ -2244,6 +2438,7 @@ static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
{ .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg}, { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
{ .hw_rev = DPU_HW_VER_630, .dpu_cfg = &sm6115_dpu_cfg}, { .hw_rev = DPU_HW_VER_630, .dpu_cfg = &sm6115_dpu_cfg},
{ .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg}, { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
{ .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg},
{ .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg}, { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
{ .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg}, { .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg},
}; };
......
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
View file @ 0e91bcbb
...@@ -46,6 +46,7 @@ ...@@ -46,6 +46,7 @@
#define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */
#define DPU_HW_VER_630 DPU_HW_VER(6, 3, 0) /* sm6115|sm4250 */ #define DPU_HW_VER_630 DPU_HW_VER(6, 3, 0) /* sm6115|sm4250 */
#define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */
#define DPU_HW_VER_700 DPU_HW_VER(7, 0, 0) /* sm8350 */
#define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */
#define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */ #define DPU_HW_VER_810 DPU_HW_VER(8, 1, 0) /* sm8450 */
......
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