Commit 0f8d2a2b authored by Ville Syrjälä's avatar Ville Syrjälä

drm/i915: Rename i915_{save,restore}_state()

i915_{save,restore}_state() are actually all about the display.
Currently they are split into display part + SWF part. But since
the SWF part is also related to the display let's just move that
part into its own thing and flip the roles around so that the
current display part is the main function.
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201005171441.26612-1-ville.syrjala@linux.intel.comReviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent f13c2a00
...@@ -1119,7 +1119,7 @@ static int i915_drm_suspend(struct drm_device *dev) ...@@ -1119,7 +1119,7 @@ static int i915_drm_suspend(struct drm_device *dev)
i915_ggtt_suspend(&dev_priv->ggtt); i915_ggtt_suspend(&dev_priv->ggtt);
i915_save_state(dev_priv); i915_save_display(dev_priv);
opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold; opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
intel_opregion_suspend(dev_priv, opregion_target_state); intel_opregion_suspend(dev_priv, opregion_target_state);
...@@ -1232,7 +1232,7 @@ static int i915_drm_resume(struct drm_device *dev) ...@@ -1232,7 +1232,7 @@ static int i915_drm_resume(struct drm_device *dev)
intel_csr_ucode_resume(dev_priv); intel_csr_ucode_resume(dev_priv);
i915_restore_state(dev_priv); i915_restore_display(dev_priv);
intel_pps_unlock_regs_wa(dev_priv); intel_pps_unlock_regs_wa(dev_priv);
intel_init_pch_refclk(dev_priv); intel_init_pch_refclk(dev_priv);
......
...@@ -32,45 +32,10 @@ ...@@ -32,45 +32,10 @@
#include "i915_reg.h" #include "i915_reg.h"
#include "i915_suspend.h" #include "i915_suspend.h"
static void i915_save_display(struct drm_i915_private *dev_priv) static void intel_save_swf(struct drm_i915_private *dev_priv)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
/* Display arbitration control */
if (INTEL_GEN(dev_priv) <= 4)
dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
if (IS_GEN(dev_priv, 4))
pci_read_config_word(pdev, GCDGMBUS,
&dev_priv->regfile.saveGCDGMBUS);
}
static void i915_restore_display(struct drm_i915_private *dev_priv)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
if (IS_GEN(dev_priv, 4))
pci_write_config_word(pdev, GCDGMBUS,
dev_priv->regfile.saveGCDGMBUS);
/* Display arbitration */
if (INTEL_GEN(dev_priv) <= 4)
I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
/* only restore FBC info on the platform that supports FBC*/
intel_fbc_global_disable(dev_priv);
intel_vga_redisable(dev_priv);
intel_gmbus_reset(dev_priv);
}
int i915_save_state(struct drm_i915_private *dev_priv)
{ {
int i; int i;
i915_save_display(dev_priv);
/* Scratch space */ /* Scratch space */
if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) { if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
for (i = 0; i < 7; i++) { for (i = 0; i < 7; i++) {
...@@ -90,16 +55,12 @@ int i915_save_state(struct drm_i915_private *dev_priv) ...@@ -90,16 +55,12 @@ int i915_save_state(struct drm_i915_private *dev_priv)
for (i = 0; i < 3; i++) for (i = 0; i < 3; i++)
dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i)); dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
} }
return 0;
} }
int i915_restore_state(struct drm_i915_private *dev_priv) static void intel_restore_swf(struct drm_i915_private *dev_priv)
{ {
int i; int i;
i915_restore_display(dev_priv);
/* Scratch space */ /* Scratch space */
if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) { if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
for (i = 0; i < 7; i++) { for (i = 0; i < 7; i++) {
...@@ -119,6 +80,41 @@ int i915_restore_state(struct drm_i915_private *dev_priv) ...@@ -119,6 +80,41 @@ int i915_restore_state(struct drm_i915_private *dev_priv)
for (i = 0; i < 3; i++) for (i = 0; i < 3; i++)
I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]); I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
} }
}
void i915_save_display(struct drm_i915_private *dev_priv)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
/* Display arbitration control */
if (INTEL_GEN(dev_priv) <= 4)
dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
return 0; if (IS_GEN(dev_priv, 4))
pci_read_config_word(pdev, GCDGMBUS,
&dev_priv->regfile.saveGCDGMBUS);
intel_save_swf(dev_priv);
}
void i915_restore_display(struct drm_i915_private *dev_priv)
{
struct pci_dev *pdev = dev_priv->drm.pdev;
intel_restore_swf(dev_priv);
if (IS_GEN(dev_priv, 4))
pci_write_config_word(pdev, GCDGMBUS,
dev_priv->regfile.saveGCDGMBUS);
/* Display arbitration */
if (INTEL_GEN(dev_priv) <= 4)
I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
/* only restore FBC info on the platform that supports FBC*/
intel_fbc_global_disable(dev_priv);
intel_vga_redisable(dev_priv);
intel_gmbus_reset(dev_priv);
} }
...@@ -8,7 +8,7 @@ ...@@ -8,7 +8,7 @@
struct drm_i915_private; struct drm_i915_private;
int i915_save_state(struct drm_i915_private *i915); void i915_save_display(struct drm_i915_private *i915);
int i915_restore_state(struct drm_i915_private *i915); void i915_restore_display(struct drm_i915_private *i915);
#endif /* __I915_SUSPEND_H__ */ #endif /* __I915_SUSPEND_H__ */
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