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Commit 129e1c96 authored by Felipe Balbi's avatar Felipe Balbi Committed by Bjorn Andersson
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arm64: dts: qcom: sm8150: add SPI nodes 

Add missing SPI nodes for SM8150.
Signed-off-by: default avatarFelipe Balbi <felipe.balbi@microsoft.com>
Reviewed-by: default avatarCaleb Connolly <caleb@connolly.tech>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Link: https://lore.kernel.org/r/20210416103225.1872145-1-balbi@kernel.orgSigned-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 98b43386
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arch/arm64/boot/dts/qcom/sm8150.dtsi
View file @ 129e1c96
......@@ -941,6 +941,21 @@ i2c0: i2c@880000 {
status = "disabled";
};
spi0: spi@880000 {
compatible = "qcom,geni-spi";
reg = <0 0x880000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@884000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00884000 0 0x4000>;
......@@ -954,6 +969,21 @@ i2c1: i2c@884000 {
status = "disabled";
};
spi1: spi@884000 {
compatible = "qcom,geni-spi";
reg = <0 0x884000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@888000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00888000 0 0x4000>;
......@@ -967,6 +997,21 @@ i2c2: i2c@888000 {
status = "disabled";
};
spi2: spi@888000 {
compatible = "qcom,geni-spi";
reg = <0 0x888000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c3: i2c@88c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0088c000 0 0x4000>;
......@@ -980,6 +1025,21 @@ i2c3: i2c@88c000 {
status = "disabled";
};
spi3: spi@88c000 {
compatible = "qcom,geni-spi";
reg = <0 0x88c000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi3_default>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c4: i2c@890000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00890000 0 0x4000>;
......@@ -993,6 +1053,21 @@ i2c4: i2c@890000 {
status = "disabled";
};
spi4: spi@890000 {
compatible = "qcom,geni-spi";
reg = <0 0x890000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi4_default>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c5: i2c@894000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00894000 0 0x4000>;
......@@ -1006,6 +1081,21 @@ i2c5: i2c@894000 {
status = "disabled";
};
spi5: spi@894000 {
compatible = "qcom,geni-spi";
reg = <0 0x894000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c6: i2c@898000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00898000 0 0x4000>;
......@@ -1019,6 +1109,21 @@ i2c6: i2c@898000 {
status = "disabled";
};
spi6: spi@898000 {
compatible = "qcom,geni-spi";
reg = <0 0x898000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi6_default>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c7: i2c@89c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0089c000 0 0x4000>;
......@@ -1032,6 +1137,20 @@ i2c7: i2c@89c000 {
status = "disabled";
};
spi7: spi@89c000 {
compatible = "qcom,geni-spi";
reg = <0 0x89c000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi7_default>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
gpi_dma1: dma-controller@a00000 {
......@@ -1082,6 +1201,21 @@ i2c8: i2c@a80000 {
status = "disabled";
};
spi8: spi@a80000 {
compatible = "qcom,geni-spi";
reg = <0 0xa80000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi8_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c9: i2c@a84000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a84000 0 0x4000>;
......@@ -1095,6 +1229,21 @@ i2c9: i2c@a84000 {
status = "disabled";
};
spi9: spi@a84000 {
compatible = "qcom,geni-spi";
reg = <0 0xa84000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi9_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c10: i2c@a88000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a88000 0 0x4000>;
......@@ -1108,6 +1257,21 @@ i2c10: i2c@a88000 {
status = "disabled";
};
spi10: spi@a88000 {
compatible = "qcom,geni-spi";
reg = <0 0xa88000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi10_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c11: i2c@a8c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00a8c000 0 0x4000>;
......@@ -1121,6 +1285,21 @@ i2c11: i2c@a8c000 {
status = "disabled";
};
spi11: spi@a8c000 {
compatible = "qcom,geni-spi";
reg = <0 0xa8c000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi11_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
uart2: serial@a90000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x00a90000 0x0 0x4000>;
......@@ -1143,6 +1322,21 @@ i2c12: i2c@a90000 {
status = "disabled";
};
spi12: spi@a90000 {
compatible = "qcom,geni-spi";
reg = <0 0xa90000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi12_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c16: i2c@94000 {
compatible = "qcom,geni-i2c";
reg = <0 0x0094000 0 0x4000>;
......@@ -1155,6 +1349,21 @@ i2c16: i2c@94000 {
#size-cells = <0>;
status = "disabled";
};
spi16: spi@a94000 {
compatible = "qcom,geni-spi";
reg = <0 0xa94000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi16_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
gpi_dma2: dma-controller@c00000 {
......@@ -1206,6 +1415,21 @@ i2c17: i2c@c80000 {
status = "disabled";
};
spi17: spi@c80000 {
compatible = "qcom,geni-spi";
reg = <0 0xc80000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi17_default>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c18: i2c@c84000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00c84000 0 0x4000>;
......@@ -1219,6 +1443,21 @@ i2c18: i2c@c84000 {
status = "disabled";
};
spi18: spi@c84000 {
compatible = "qcom,geni-spi";
reg = <0 0xc84000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi18_default>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c19: i2c@c88000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00c88000 0 0x4000>;
......@@ -1232,6 +1471,21 @@ i2c19: i2c@c88000 {
status = "disabled";
};
spi19: spi@c88000 {
compatible = "qcom,geni-spi";
reg = <0 0xc88000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi19_default>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c13: i2c@c8c000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00c8c000 0 0x4000>;
......@@ -1245,6 +1499,21 @@ i2c13: i2c@c8c000 {
status = "disabled";
};
spi13: spi@c8c000 {
compatible = "qcom,geni-spi";
reg = <0 0xc8c000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi13_default>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c14: i2c@c90000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00c90000 0 0x4000>;
......@@ -1258,6 +1527,21 @@ i2c14: i2c@c90000 {
status = "disabled";
};
spi14: spi@c90000 {
compatible = "qcom,geni-spi";
reg = <0 0xc90000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi14_default>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c15: i2c@c94000 {
compatible = "qcom,geni-i2c";
reg = <0 0x00c94000 0 0x4000>;
......@@ -1270,6 +1554,21 @@ i2c15: i2c@c94000 {
#size-cells = <0>;
status = "disabled";
};
spi15: spi@c94000 {
compatible = "qcom,geni-spi";
reg = <0 0xc94000 0 0x4000>;
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
pinctrl-names = "default";
pinctrl-0 = <&qup_spi15_default>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <50000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
config_noc: interconnect@1500000 {
......@@ -1616,6 +1915,13 @@ config {
};
};
qup_spi0_default: qup-spi0-default {
pins = "gpio0", "gpio1", "gpio2", "gpio3";
function = "qup0";
drive-strength = <6>;
bias-disable;
};
qup_i2c1_default: qup-i2c1-default {
mux {
pins = "gpio114", "gpio115";
......@@ -1629,6 +1935,13 @@ config {
};
};
qup_spi1_default: qup-spi1-default {
pins = "gpio114", "gpio115", "gpio116", "gpio117";
function = "qup1";
drive-strength = <6>;
bias-disable;
};
qup_i2c2_default: qup-i2c2-default {
mux {
pins = "gpio126", "gpio127";
......@@ -1642,6 +1955,13 @@ config {
};
};
qup_spi2_default: qup-spi2-default {
pins = "gpio126", "gpio127", "gpio128", "gpio129";
function = "qup2";
drive-strength = <6>;
bias-disable;
};
qup_i2c3_default: qup-i2c3-default {
mux {
pins = "gpio144", "gpio145";
......@@ -1655,6 +1975,13 @@ config {
};
};
qup_spi3_default: qup-spi3-default {
pins = "gpio144", "gpio145", "gpio146", "gpio147";
function = "qup3";
drive-strength = <6>;
bias-disable;
};
qup_i2c4_default: qup-i2c4-default {
mux {
pins = "gpio51", "gpio52";
......@@ -1668,6 +1995,13 @@ config {
};
};
qup_spi4_default: qup-spi4-default {
pins = "gpio51", "gpio52", "gpio53", "gpio54";
function = "qup4";
drive-strength = <6>;
bias-disable;
};
qup_i2c5_default: qup-i2c5-default {
mux {
pins = "gpio121", "gpio122";
......@@ -1681,6 +2015,13 @@ config {
};
};
qup_spi5_default: qup-spi5-default {
pins = "gpio119", "gpio120", "gpio121", "gpio122";
function = "qup5";
drive-strength = <6>;
bias-disable;
};
qup_i2c6_default: qup-i2c6-default {
mux {
pins = "gpio6", "gpio7";
......@@ -1694,6 +2035,13 @@ config {
};
};
qup_spi6_default: qup-spi6_default {
pins = "gpio4", "gpio5", "gpio6", "gpio7";
function = "qup6";
drive-strength = <6>;
bias-disable;
};
qup_i2c7_default: qup-i2c7-default {
mux {
pins = "gpio98", "gpio99";
......@@ -1707,6 +2055,13 @@ config {
};
};
qup_spi7_default: qup-spi7_default {
pins = "gpio98", "gpio99", "gpio100", "gpio101";
function = "qup7";
drive-strength = <6>;
bias-disable;
};
qup_i2c8_default: qup-i2c8-default {
mux {
pins = "gpio88", "gpio89";
......@@ -1720,6 +2075,13 @@ config {
};
};
qup_spi8_default: qup-spi8-default {
pins = "gpio88", "gpio89", "gpio90", "gpio91";
function = "qup8";
drive-strength = <6>;
bias-disable;
};
qup_i2c9_default: qup-i2c9-default {
mux {
pins = "gpio39", "gpio40";
......@@ -1733,6 +2095,13 @@ config {
};
};
qup_spi9_default: qup-spi9-default {
pins = "gpio39", "gpio40", "gpio41", "gpio42";
function = "qup9";
drive-strength = <6>;
bias-disable;
};
qup_i2c10_default: qup-i2c10-default {
mux {
pins = "gpio9", "gpio10";
......@@ -1746,6 +2115,13 @@ config {
};
};
qup_spi10_default: qup-spi10-default {
pins = "gpio9", "gpio10", "gpio11", "gpio12";
function = "qup10";
drive-strength = <6>;
bias-disable;
};
qup_i2c11_default: qup-i2c11-default {
mux {
pins = "gpio94", "gpio95";
......@@ -1759,6 +2135,13 @@ config {
};
};
qup_spi11_default: qup-spi11-default {
pins = "gpio92", "gpio93", "gpio94", "gpio95";
function = "qup11";
drive-strength = <6>;
bias-disable;
};
qup_i2c12_default: qup-i2c12-default {
mux {
pins = "gpio83", "gpio84";
......@@ -1772,6 +2155,13 @@ config {
};
};
qup_spi12_default: qup-spi12-default {
pins = "gpio83", "gpio84", "gpio85", "gpio86";
function = "qup12";
drive-strength = <6>;
bias-disable;
};
qup_i2c13_default: qup-i2c13-default {
mux {
pins = "gpio43", "gpio44";
......@@ -1785,6 +2175,13 @@ config {
};
};
qup_spi13_default: qup-spi13-default {
pins = "gpio43", "gpio44", "gpio45", "gpio46";
function = "qup13";
drive-strength = <6>;
bias-disable;
};
qup_i2c14_default: qup-i2c14-default {
mux {
pins = "gpio47", "gpio48";
......@@ -1798,6 +2195,13 @@ config {
};
};
qup_spi14_default: qup-spi14-default {
pins = "gpio47", "gpio48", "gpio49", "gpio50";
function = "qup14";
drive-strength = <6>;
bias-disable;
};
qup_i2c15_default: qup-i2c15-default {
mux {
pins = "gpio27", "gpio28";
......@@ -1811,6 +2215,13 @@ config {
};
};
qup_spi15_default: qup-spi15-default {
pins = "gpio27", "gpio28", "gpio29", "gpio30";
function = "qup15";
drive-strength = <6>;
bias-disable;
};
qup_i2c16_default: qup-i2c16-default {
mux {
pins = "gpio86", "gpio85";
......@@ -1824,6 +2235,13 @@ config {
};
};
qup_spi16_default: qup-spi16-default {
pins = "gpio83", "gpio84", "gpio85", "gpio86";
function = "qup16";
drive-strength = <6>;
bias-disable;
};
qup_i2c17_default: qup-i2c17-default {
mux {
pins = "gpio55", "gpio56";
......@@ -1837,6 +2255,13 @@ config {
};
};
qup_spi17_default: qup-spi17-default {
pins = "gpio55", "gpio56", "gpio57", "gpio58";
function = "qup17";
drive-strength = <6>;
bias-disable;
};
qup_i2c18_default: qup-i2c18-default {
mux {
pins = "gpio23", "gpio24";
......@@ -1850,6 +2275,13 @@ config {
};
};
qup_spi18_default: qup-spi18-default {
pins = "gpio23", "gpio24", "gpio25", "gpio26";
function = "qup18";
drive-strength = <6>;
bias-disable;
};
qup_i2c19_default: qup-i2c19-default {
mux {
pins = "gpio57", "gpio58";
......@@ -1862,6 +2294,13 @@ config {
bias-disable;
};
};
qup_spi19_default: qup-spi19-default {
pins = "gpio55", "gpio56", "gpio57", "gpio58";
function = "qup19";
drive-strength = <6>;
bias-disable;
};
};
remoteproc_mpss: remoteproc@4080000 {
......
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