Commit 198fa4bc authored by Bard Liao's avatar Bard Liao Committed by Mark Brown

ASoC: SOF: intel: add snd_sof_dsp_check_sdw_irq ops

SoundWire IRQ status checks are platform-dependent, add new ops structure
to provide abstraction.
Signed-off-by: default avatarBard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: default avatarRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20210723115451.7245-6-yung-chuan.liao@linux.intel.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 2f1315ae
...@@ -349,6 +349,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = { ...@@ -349,6 +349,7 @@ const struct sof_intel_dsp_desc cnl_chip_info = {
.ssp_base_offset = CNL_SSP_BASE_OFFSET, .ssp_base_offset = CNL_SSP_BASE_OFFSET,
.sdw_shim_base = SDW_SHIM_BASE, .sdw_shim_base = SDW_SHIM_BASE,
.sdw_alh_base = SDW_ALH_BASE, .sdw_alh_base = SDW_ALH_BASE,
.check_sdw_irq = hda_common_check_sdw_irq,
}; };
EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); EXPORT_SYMBOL_NS(cnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
...@@ -367,5 +368,6 @@ const struct sof_intel_dsp_desc jsl_chip_info = { ...@@ -367,5 +368,6 @@ const struct sof_intel_dsp_desc jsl_chip_info = {
.ssp_base_offset = CNL_SSP_BASE_OFFSET, .ssp_base_offset = CNL_SSP_BASE_OFFSET,
.sdw_shim_base = SDW_SHIM_BASE, .sdw_shim_base = SDW_SHIM_BASE,
.sdw_alh_base = SDW_ALH_BASE, .sdw_alh_base = SDW_ALH_BASE,
.check_sdw_irq = hda_common_check_sdw_irq,
}; };
EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); EXPORT_SYMBOL_NS(jsl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
...@@ -222,7 +222,7 @@ static int hda_sdw_exit(struct snd_sof_dev *sdev) ...@@ -222,7 +222,7 @@ static int hda_sdw_exit(struct snd_sof_dev *sdev)
return 0; return 0;
} }
static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
{ {
struct sof_intel_hda_dev *hdev; struct sof_intel_hda_dev *hdev;
bool ret = false; bool ret = false;
...@@ -248,6 +248,17 @@ static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev) ...@@ -248,6 +248,17 @@ static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
return ret; return ret;
} }
static bool hda_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
{
const struct sof_intel_dsp_desc *chip;
chip = get_chip_info(sdev->pdata);
if (chip && chip->check_sdw_irq)
return chip->check_sdw_irq(sdev);
return false;
}
static irqreturn_t hda_dsp_sdw_thread(int irq, void *context) static irqreturn_t hda_dsp_sdw_thread(int irq, void *context)
{ {
return sdw_intel_thread(irq, context); return sdw_intel_thread(irq, context);
......
...@@ -691,6 +691,7 @@ int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd); ...@@ -691,6 +691,7 @@ int hda_dsp_trace_trigger(struct snd_sof_dev *sdev, int cmd);
int hda_sdw_startup(struct snd_sof_dev *sdev); int hda_sdw_startup(struct snd_sof_dev *sdev);
void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable); void hda_sdw_int_enable(struct snd_sof_dev *sdev, bool enable);
void hda_sdw_process_wakeen(struct snd_sof_dev *sdev); void hda_sdw_process_wakeen(struct snd_sof_dev *sdev);
bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev);
#else #else
...@@ -736,6 +737,12 @@ static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev) ...@@ -736,6 +737,12 @@ static inline bool hda_sdw_check_wakeen_irq(struct snd_sof_dev *sdev)
static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev) static inline void hda_sdw_process_wakeen(struct snd_sof_dev *sdev)
{ {
} }
static inline bool hda_common_check_sdw_irq(struct snd_sof_dev *sdev)
{
return false;
}
#endif #endif
/* common dai driver */ /* common dai driver */
......
...@@ -144,5 +144,6 @@ const struct sof_intel_dsp_desc icl_chip_info = { ...@@ -144,5 +144,6 @@ const struct sof_intel_dsp_desc icl_chip_info = {
.ssp_base_offset = CNL_SSP_BASE_OFFSET, .ssp_base_offset = CNL_SSP_BASE_OFFSET,
.sdw_shim_base = SDW_SHIM_BASE, .sdw_shim_base = SDW_SHIM_BASE,
.sdw_alh_base = SDW_ALH_BASE, .sdw_alh_base = SDW_ALH_BASE,
.check_sdw_irq = hda_common_check_sdw_irq,
}; };
EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); EXPORT_SYMBOL_NS(icl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
...@@ -166,6 +166,7 @@ struct sof_intel_dsp_desc { ...@@ -166,6 +166,7 @@ struct sof_intel_dsp_desc {
int ssp_base_offset; /* base address of the SSPs */ int ssp_base_offset; /* base address of the SSPs */
u32 sdw_shim_base; u32 sdw_shim_base;
u32 sdw_alh_base; u32 sdw_alh_base;
bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
}; };
extern const struct snd_sof_dsp_ops sof_tng_ops; extern const struct snd_sof_dsp_ops sof_tng_ops;
......
...@@ -139,6 +139,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = { ...@@ -139,6 +139,7 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
.ssp_base_offset = CNL_SSP_BASE_OFFSET, .ssp_base_offset = CNL_SSP_BASE_OFFSET,
.sdw_shim_base = SDW_SHIM_BASE, .sdw_shim_base = SDW_SHIM_BASE,
.sdw_alh_base = SDW_ALH_BASE, .sdw_alh_base = SDW_ALH_BASE,
.check_sdw_irq = hda_common_check_sdw_irq,
}; };
EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
...@@ -157,6 +158,7 @@ const struct sof_intel_dsp_desc tglh_chip_info = { ...@@ -157,6 +158,7 @@ const struct sof_intel_dsp_desc tglh_chip_info = {
.ssp_base_offset = CNL_SSP_BASE_OFFSET, .ssp_base_offset = CNL_SSP_BASE_OFFSET,
.sdw_shim_base = SDW_SHIM_BASE, .sdw_shim_base = SDW_SHIM_BASE,
.sdw_alh_base = SDW_ALH_BASE, .sdw_alh_base = SDW_ALH_BASE,
.check_sdw_irq = hda_common_check_sdw_irq,
}; };
EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
...@@ -175,6 +177,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = { ...@@ -175,6 +177,7 @@ const struct sof_intel_dsp_desc ehl_chip_info = {
.ssp_base_offset = CNL_SSP_BASE_OFFSET, .ssp_base_offset = CNL_SSP_BASE_OFFSET,
.sdw_shim_base = SDW_SHIM_BASE, .sdw_shim_base = SDW_SHIM_BASE,
.sdw_alh_base = SDW_ALH_BASE, .sdw_alh_base = SDW_ALH_BASE,
.check_sdw_irq = hda_common_check_sdw_irq,
}; };
EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); EXPORT_SYMBOL_NS(ehl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
...@@ -193,5 +196,6 @@ const struct sof_intel_dsp_desc adls_chip_info = { ...@@ -193,5 +196,6 @@ const struct sof_intel_dsp_desc adls_chip_info = {
.ssp_base_offset = CNL_SSP_BASE_OFFSET, .ssp_base_offset = CNL_SSP_BASE_OFFSET,
.sdw_shim_base = SDW_SHIM_BASE, .sdw_shim_base = SDW_SHIM_BASE,
.sdw_alh_base = SDW_ALH_BASE, .sdw_alh_base = SDW_ALH_BASE,
.check_sdw_irq = hda_common_check_sdw_irq,
}; };
EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); EXPORT_SYMBOL_NS(adls_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
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