arm64: dts: ti: k3-j7200: Enable PCIe nodes at the board level

PCIe node defined in the top-level J7200 SoC dtsi file is incomplete
and will not be functional unless it is extended with a SerDes PHY.

As the PHY and mode is only known at the board integration level, this
node should only be enabled when provided with this information.

Disable the PCIe node in the dtsi files and only enable when it is
actually pinned out on a given board.
Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240124183659.149119-1-afd@ti.comSigned-off-by: Vignesh Raghavendra <vigneshr@ti.com>

arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts

@@ -382,6 +382,7 @@ serdes0_qsgmii_link: phy@1 {
 };
 
 &pcie1_rc {
+	status = "okay";
 	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
 	phys = <&serdes0_pcie_link>;
 	phy-names = "pcie-phy";

arch/arm64/boot/dts/ti/k3-j7200-main.dtsi

@@ -770,6 +770,7 @@ pcie1_rc: pcie@2910000 {
 		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
 			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
 		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+		status = "disabled";
 	};
 
 	pcie1_ep: pcie-ep@2910000 {