Commit 1d14bcff authored by Rohit Agarwal's avatar Rohit Agarwal Committed by Bjorn Andersson

arm64: dts: qcom: sm8550: Update the RPMHPD bindings entry

Update the RPMHPD bindings entry as per the new generic bindings defined
in rpmhpd.h for SM8550 SoC.
Signed-off-by: default avatarRohit Agarwal <quic_rohiagar@quicinc.com>
Link: https://lore.kernel.org/r/1689840545-5094-5-git-send-email-quic_rohiagar@quicinc.comSigned-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 8ed9de79
......@@ -15,6 +15,7 @@
#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/soc/qcom,gpr.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
......@@ -1989,8 +1990,8 @@ remoteproc_mpss: remoteproc@4080000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd SM8550_CX>,
<&rpmhpd SM8550_MSS>;
power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MSS>;
power-domain-names = "cx", "mss";
interconnects = <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>;
......@@ -2368,7 +2369,7 @@ sdhc_2: mmc@8804000 {
iommus = <&apps_smmu 0x540 0>;
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
power-domains = <&rpmhpd SM8550_CX>;
power-domains = <&rpmhpd RPMHPD_CX>;
operating-points-v2 = <&sdhc2_opp_table>;
interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
......@@ -2412,7 +2413,7 @@ videocc: clock-controller@aaf0000 {
reg = <0 0x0aaf0000 0 0x10000>;
clocks = <&bi_tcxo_div2>,
<&gcc GCC_VIDEO_AHB_CLK>;
power-domains = <&rpmhpd SM8550_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
......@@ -2471,7 +2472,7 @@ mdss_mdp: display-controller@ae01000 {
"core",
"vsync";
power-domains = <&rpmhpd SM8550_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
assigned-clock-rates = <19200000>;
......@@ -2560,7 +2561,7 @@ mdss_dp0: displayport-controller@ae90000 {
#sound-dai-cells = <0>;
operating-points-v2 = <&dp_opp_table>;
power-domains = <&rpmhpd SM8550_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
status = "disabled";
......@@ -2628,7 +2629,7 @@ mdss_dsi0: dsi@ae94000 {
"iface",
"bus";
power-domains = <&rpmhpd SM8550_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
......@@ -2723,7 +2724,7 @@ mdss_dsi1: dsi@ae96000 {
"iface",
"bus";
power-domains = <&rpmhpd SM8550_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
......@@ -2798,7 +2799,7 @@ dispcc: clock-controller@af00000 {
<0>,
<0>, /* dp3 */
<0>;
power-domains = <&rpmhpd SM8550_MMCX>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
#clock-cells = <1>;
#reset-cells = <1>;
......@@ -3933,8 +3934,8 @@ remoteproc_adsp: remoteproc@30000000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd SM8550_LCX>,
<&rpmhpd SM8550_LMX>;
power-domains = <&rpmhpd RPMHPD_LCX>,
<&rpmhpd RPMHPD_LMX>;
power-domain-names = "lcx", "lmx";
interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC 0 &mc_virt SLAVE_EBI1 0>;
......@@ -4065,9 +4066,9 @@ remoteproc_cdsp: remoteproc@32300000 {
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd SM8550_CX>,
<&rpmhpd SM8550_MXC>,
<&rpmhpd SM8550_NSP>;
power-domains = <&rpmhpd RPMHPD_CX>,
<&rpmhpd RPMHPD_MXC>,
<&rpmhpd RPMHPD_NSP>;
power-domain-names = "cx", "mxc", "nsp";
interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment