Commit 1d82ef65 authored by Ville Syrjälä's avatar Ville Syrjälä

drm/i915: Pimp icl+ sagv pre/post update

Add some debugs on what exactly we're doing to the QGV point mask
in the icl+ sagv pre/post plane update hooks. Currently we're just
guessing.

v2: s/u32/u16/ for consistency with the mask sizes (Stan)
Reviewed-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220218064039.12834-5-ville.syrjala@linux.intel.com
parent f2578791
...@@ -3814,26 +3814,22 @@ static void icl_sagv_pre_plane_update(struct intel_atomic_state *state) ...@@ -3814,26 +3814,22 @@ static void icl_sagv_pre_plane_update(struct intel_atomic_state *state)
intel_atomic_get_old_bw_state(state); intel_atomic_get_old_bw_state(state);
const struct intel_bw_state *new_bw_state = const struct intel_bw_state *new_bw_state =
intel_atomic_get_new_bw_state(state); intel_atomic_get_new_bw_state(state);
u32 new_mask; u16 old_mask, new_mask;
if (!new_bw_state) if (!new_bw_state)
return; return;
/* old_mask = old_bw_state->qgv_points_mask;
* Nothing to mask
*/
if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
return;
new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask; new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
/* if (old_mask == new_mask)
* If new mask is zero - means there is nothing to mask,
* we can only unmask, which should be done in unmask.
*/
if (!new_mask)
return; return;
WARN_ON(!new_bw_state->base.changed);
drm_dbg_kms(&dev_priv->drm, "Restricting QGV points: 0x%x -> 0x%x\n",
old_mask, new_mask);
/* /*
* Restrict required qgv points before updating the configuration. * Restrict required qgv points before updating the configuration.
* According to BSpec we can't mask and unmask qgv points at the same * According to BSpec we can't mask and unmask qgv points at the same
...@@ -3850,18 +3846,21 @@ static void icl_sagv_post_plane_update(struct intel_atomic_state *state) ...@@ -3850,18 +3846,21 @@ static void icl_sagv_post_plane_update(struct intel_atomic_state *state)
intel_atomic_get_old_bw_state(state); intel_atomic_get_old_bw_state(state);
const struct intel_bw_state *new_bw_state = const struct intel_bw_state *new_bw_state =
intel_atomic_get_new_bw_state(state); intel_atomic_get_new_bw_state(state);
u32 new_mask = 0; u16 old_mask, new_mask;
if (!new_bw_state) if (!new_bw_state)
return; return;
/* old_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
* Nothing to unmask new_mask = new_bw_state->qgv_points_mask;
*/
if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask) if (old_mask == new_mask)
return; return;
new_mask = new_bw_state->qgv_points_mask; WARN_ON(!new_bw_state->base.changed);
drm_dbg_kms(&dev_priv->drm, "Relaxing QGV points: 0x%x -> 0x%x\n",
old_mask, new_mask);
/* /*
* Allow required qgv points after updating the configuration. * Allow required qgv points after updating the configuration.
......
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