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Commit 27c77943 authored by David S. Miller's avatar David S. Miller
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Merge branch 'hns3-cleanups' 

Guangbin Huang says:

====================
net: hns3: add some cleanups

This series includes some cleanups for the HNS3 ethernet driver.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 49f9df5b 52d89333
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Showing with 1260 additions and 630 deletions
drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
View file @ 27c77943
......@@ -695,7 +695,7 @@ static int hns3_dbg_queue_map(struct hnae3_handle *h, char *buf, int len)
sprintf(result[j++], "%u", i);
sprintf(result[j++], "%u",
h->ae_algo->ops->get_global_queue_id(h, i));
sprintf(result[j++], "%u",
sprintf(result[j++], "%d",
priv->ring[i].tqp_vector->vector_irq);
hns3_dbg_fill_content(content, sizeof(content), queue_map_items,
(const char **)result,
......
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
View file @ 27c77943
......@@ -971,8 +971,7 @@ static u32 hns3_tx_spare_space(struct hns3_enet_ring *ring)
/* The free tx buffer is divided into two part, so pick the
* larger one.
*/
return (ntc > (tx_spare->len - ntu) ? ntc :
(tx_spare->len - ntu)) - 1;
return max(ntc, tx_spare->len - ntu) - 1;
}
static void hns3_tx_spare_update(struct hns3_enet_ring *ring)
......
drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
View file @ 27c77943
......@@ -298,33 +298,8 @@ static int hns3_lp_run_test(struct net_device *ndev, enum hnae3_loop mode)
return ret_val;
}
/**
* hns3_self_test - self test
* @ndev: net device
* @eth_test: test cmd
* @data: test result
*/
static void hns3_self_test(struct net_device *ndev,
struct ethtool_test *eth_test, u64 *data)
static void hns3_set_selftest_param(struct hnae3_handle *h, int (*st_param)[2])
{
struct hns3_nic_priv *priv = netdev_priv(ndev);
struct hnae3_handle *h = priv->ae_handle;
int st_param[HNS3_SELF_TEST_TYPE_NUM][2];
bool if_running = netif_running(ndev);
int test_index = 0;
u32 i;
if (hns3_nic_resetting(ndev)) {
netdev_err(ndev, "dev resetting!");
return;
}
/* Only do offline selftest, or pass by default */
if (eth_test->flags != ETH_TEST_FL_OFFLINE)
return;
netif_dbg(h, drv, ndev, "self test start");
st_param[HNAE3_LOOP_APP][0] = HNAE3_LOOP_APP;
st_param[HNAE3_LOOP_APP][1] =
h->flags & HNAE3_SUPPORT_APP_LOOPBACK;
......@@ -341,6 +316,18 @@ static void hns3_self_test(struct net_device *ndev,
st_param[HNAE3_LOOP_PHY][0] = HNAE3_LOOP_PHY;
st_param[HNAE3_LOOP_PHY][1] =
h->flags & HNAE3_SUPPORT_PHY_LOOPBACK;
}
static void hns3_selftest_prepare(struct net_device *ndev,
bool if_running, int (*st_param)[2])
{
struct hns3_nic_priv *priv = netdev_priv(ndev);
struct hnae3_handle *h = priv->ae_handle;
if (netif_msg_ifdown(h))
netdev_info(ndev, "self test start\n");
hns3_set_selftest_param(h, st_param);
if (if_running)
ndev->netdev_ops->ndo_stop(ndev);
......@@ -359,6 +346,35 @@ static void hns3_self_test(struct net_device *ndev,
h->ae_algo->ops->halt_autoneg(h, true);
set_bit(HNS3_NIC_STATE_TESTING, &priv->state);
}
static void hns3_selftest_restore(struct net_device *ndev, bool if_running)
{
struct hns3_nic_priv *priv = netdev_priv(ndev);
struct hnae3_handle *h = priv->ae_handle;
clear_bit(HNS3_NIC_STATE_TESTING, &priv->state);
if (h->ae_algo->ops->halt_autoneg)
h->ae_algo->ops->halt_autoneg(h, false);
#if IS_ENABLED(CONFIG_VLAN_8021Q)
if (h->ae_algo->ops->enable_vlan_filter)
h->ae_algo->ops->enable_vlan_filter(h, true);
#endif
if (if_running)
ndev->netdev_ops->ndo_open(ndev);
if (netif_msg_ifdown(h))
netdev_info(ndev, "self test end\n");
}
static void hns3_do_selftest(struct net_device *ndev, int (*st_param)[2],
struct ethtool_test *eth_test, u64 *data)
{
int test_index = 0;
u32 i;
for (i = 0; i < HNS3_SELF_TEST_TYPE_NUM; i++) {
enum hnae3_loop loop_type = (enum hnae3_loop)st_param[i][0];
......@@ -377,21 +393,32 @@ static void hns3_self_test(struct net_device *ndev,
test_index++;
}
}
clear_bit(HNS3_NIC_STATE_TESTING, &priv->state);
if (h->ae_algo->ops->halt_autoneg)
h->ae_algo->ops->halt_autoneg(h, false);
/**
* hns3_nic_self_test - self test
* @ndev: net device
* @eth_test: test cmd
* @data: test result
*/
static void hns3_self_test(struct net_device *ndev,
struct ethtool_test *eth_test, u64 *data)
{
int st_param[HNS3_SELF_TEST_TYPE_NUM][2];
bool if_running = netif_running(ndev);
#if IS_ENABLED(CONFIG_VLAN_8021Q)
if (h->ae_algo->ops->enable_vlan_filter)
h->ae_algo->ops->enable_vlan_filter(h, true);
#endif
if (hns3_nic_resetting(ndev)) {
netdev_err(ndev, "dev resetting!");
return;
}
if (if_running)
ndev->netdev_ops->ndo_open(ndev);
/* Only do offline selftest, or pass by default */
if (eth_test->flags != ETH_TEST_FL_OFFLINE)
return;
netif_dbg(h, drv, ndev, "self test end\n");
hns3_selftest_prepare(ndev, if_running, st_param);
hns3_do_selftest(ndev, st_param, eth_test, data);
hns3_selftest_restore(ndev, if_running);
}
static void hns3_update_limit_promisc_mode(struct net_device *netdev,
......
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
View file @ 27c77943
......@@ -104,26 +104,30 @@ static int hclge_dcb_common_validate(struct hclge_dev *hdev, u8 num_tc,
return 0;
}
static int hclge_ets_validate(struct hclge_dev *hdev, struct ieee_ets *ets,
u8 *tc, bool *changed)
static u8 hclge_ets_tc_changed(struct hclge_dev *hdev, struct ieee_ets *ets,
bool *changed)
{
bool has_ets_tc = false;
u32 total_ets_bw = 0;
u8 max_tc = 0;
int ret;
u8 max_tc_id = 0;
u8 i;
for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
if (ets->prio_tc[i] != hdev->tm_info.prio_tc[i])
*changed = true;
if (ets->prio_tc[i] > max_tc)
max_tc = ets->prio_tc[i];
if (ets->prio_tc[i] > max_tc_id)
max_tc_id = ets->prio_tc[i];
}
ret = hclge_dcb_common_validate(hdev, max_tc + 1, ets->prio_tc);
if (ret)
return ret;
/* return max tc number, max tc id need to plus 1 */
return max_tc_id + 1;
}
static int hclge_ets_sch_mode_validate(struct hclge_dev *hdev,
struct ieee_ets *ets, bool *changed)
{
bool has_ets_tc = false;
u32 total_ets_bw = 0;
u8 i;
for (i = 0; i < hdev->tc_max; i++) {
switch (ets->tc_tsa[i]) {
......@@ -148,7 +152,26 @@ static int hclge_ets_validate(struct hclge_dev *hdev, struct ieee_ets *ets,
if (has_ets_tc && total_ets_bw != BW_PERCENT)
return -EINVAL;
*tc = max_tc + 1;
return 0;
}
static int hclge_ets_validate(struct hclge_dev *hdev, struct ieee_ets *ets,
u8 *tc, bool *changed)
{
u8 tc_num;
int ret;
tc_num = hclge_ets_tc_changed(hdev, ets, changed);
ret = hclge_dcb_common_validate(hdev, tc_num, ets->prio_tc);
if (ret)
return ret;
ret = hclge_ets_sch_mode_validate(hdev, ets, changed);
if (ret)
return ret;
*tc = tc_num;
if (*tc != hdev->tm_info.num_tc)
*changed = true;
......
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
View file @ 27c77943
......@@ -926,26 +926,45 @@ static int hclge_dbg_dump_tm_nodes(struct hclge_dev *hdev, char *buf, int len)
return 0;
}
static const struct hclge_dbg_item tm_pri_items[] = {
{ "ID", 4 },
{ "MODE", 2 },
{ "DWRR", 2 },
{ "C_IR_B", 2 },
{ "C_IR_U", 2 },
{ "C_IR_S", 2 },
{ "C_BS_B", 2 },
{ "C_BS_S", 2 },
{ "C_FLAG", 2 },
{ "C_RATE(Mbps)", 2 },
{ "P_IR_B", 2 },
{ "P_IR_U", 2 },
{ "P_IR_S", 2 },
{ "P_BS_B", 2 },
{ "P_BS_S", 2 },
{ "P_FLAG", 2 },
{ "P_RATE(Mbps)", 0 }
};
static int hclge_dbg_dump_tm_pri(struct hclge_dev *hdev, char *buf, int len)
{
struct hclge_tm_shaper_para c_shaper_para;
struct hclge_tm_shaper_para p_shaper_para;
u8 pri_num, sch_mode, weight;
char *sch_mode_str;
int pos = 0;
int ret;
u8 i;
char data_str[ARRAY_SIZE(tm_pri_items)][HCLGE_DBG_DATA_STR_LEN];
struct hclge_tm_shaper_para c_shaper_para, p_shaper_para;
char *result[ARRAY_SIZE(tm_pri_items)], *sch_mode_str;
char content[HCLGE_DBG_TM_INFO_LEN];
u8 pri_num, sch_mode, weight, i, j;
int pos, ret;
ret = hclge_tm_get_pri_num(hdev, &pri_num);
if (ret)
return ret;
pos += scnprintf(buf + pos, len - pos,
"ID MODE DWRR C_IR_B C_IR_U C_IR_S C_BS_B ");
pos += scnprintf(buf + pos, len - pos,
"C_BS_S C_FLAG C_RATE(Mbps) P_IR_B P_IR_U ");
pos += scnprintf(buf + pos, len - pos,
"P_IR_S P_BS_B P_BS_S P_FLAG P_RATE(Mbps)\n");
for (i = 0; i < ARRAY_SIZE(tm_pri_items); i++)
result[i] = &data_str[i][0];
hclge_dbg_fill_content(content, sizeof(content), tm_pri_items,
NULL, ARRAY_SIZE(tm_pri_items));
pos = scnprintf(buf, len, "%s", content);
for (i = 0; i < pri_num; i++) {
ret = hclge_tm_get_pri_sch_mode(hdev, i, &sch_mode);
......@@ -971,21 +990,16 @@ static int hclge_dbg_dump_tm_pri(struct hclge_dev *hdev, char *buf, int len)
sch_mode_str = sch_mode & HCLGE_TM_TX_SCHD_DWRR_MSK ? "dwrr" :
"sp";
pos += scnprintf(buf + pos, len - pos,
"%04u %4s %3u %3u %3u %3u ",
i, sch_mode_str, weight, c_shaper_para.ir_b,
c_shaper_para.ir_u, c_shaper_para.ir_s);
pos += scnprintf(buf + pos, len - pos,
"%3u %3u %1u %6u ",
c_shaper_para.bs_b, c_shaper_para.bs_s,
c_shaper_para.flag, c_shaper_para.rate);
pos += scnprintf(buf + pos, len - pos,
"%3u %3u %3u %3u %3u ",
p_shaper_para.ir_b, p_shaper_para.ir_u,
p_shaper_para.ir_s, p_shaper_para.bs_b,
p_shaper_para.bs_s);
pos += scnprintf(buf + pos, len - pos, "%1u %6u\n",
p_shaper_para.flag, p_shaper_para.rate);
j = 0;
sprintf(result[j++], "%04u", i);
sprintf(result[j++], "%4s", sch_mode_str);
sprintf(result[j++], "%3u", weight);
hclge_dbg_fill_shaper_content(&c_shaper_para, result, &j);
hclge_dbg_fill_shaper_content(&p_shaper_para, result, &j);
hclge_dbg_fill_content(content, sizeof(content), tm_pri_items,
(const char **)result,
ARRAY_SIZE(tm_pri_items));
pos += scnprintf(buf + pos, len - pos, "%s", content);
}
return 0;
......
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
View file @ 27c77943
......@@ -4,468 +4,895 @@
#include "hclge_err.h"
static const struct hclge_hw_error hclge_imp_tcm_ecc_int[] = {
{ .int_msk = BIT(1), .msg = "imp_itcm0_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(3), .msg = "imp_itcm1_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(5), .msg = "imp_itcm2_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(7), .msg = "imp_itcm3_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(9), .msg = "imp_dtcm0_mem0_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(11), .msg = "imp_dtcm0_mem1_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(13), .msg = "imp_dtcm1_mem0_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(15), .msg = "imp_dtcm1_mem1_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(17), .msg = "imp_itcm4_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(1),
.msg = "imp_itcm0_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(3),
.msg = "imp_itcm1_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(5),
.msg = "imp_itcm2_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(7),
.msg = "imp_itcm3_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(9),
.msg = "imp_dtcm0_mem0_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(11),
.msg = "imp_dtcm0_mem1_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(13),
.msg = "imp_dtcm1_mem0_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(15),
.msg = "imp_dtcm1_mem1_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(17),
.msg = "imp_itcm4_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_cmdq_nic_mem_ecc_int[] = {
{ .int_msk = BIT(1), .msg = "cmdq_nic_rx_depth_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(3), .msg = "cmdq_nic_tx_depth_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(5), .msg = "cmdq_nic_rx_tail_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(7), .msg = "cmdq_nic_tx_tail_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(9), .msg = "cmdq_nic_rx_head_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(11), .msg = "cmdq_nic_tx_head_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(13), .msg = "cmdq_nic_rx_addr_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(15), .msg = "cmdq_nic_tx_addr_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(17), .msg = "cmdq_rocee_rx_depth_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(19), .msg = "cmdq_rocee_tx_depth_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(21), .msg = "cmdq_rocee_rx_tail_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(23), .msg = "cmdq_rocee_tx_tail_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(25), .msg = "cmdq_rocee_rx_head_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(27), .msg = "cmdq_rocee_tx_head_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(29), .msg = "cmdq_rocee_rx_addr_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(31), .msg = "cmdq_rocee_tx_addr_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(1),
.msg = "cmdq_nic_rx_depth_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(3),
.msg = "cmdq_nic_tx_depth_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(5),
.msg = "cmdq_nic_rx_tail_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(7),
.msg = "cmdq_nic_tx_tail_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(9),
.msg = "cmdq_nic_rx_head_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(11),
.msg = "cmdq_nic_tx_head_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(13),
.msg = "cmdq_nic_rx_addr_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(15),
.msg = "cmdq_nic_tx_addr_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(17),
.msg = "cmdq_rocee_rx_depth_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(19),
.msg = "cmdq_rocee_tx_depth_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(21),
.msg = "cmdq_rocee_rx_tail_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(23),
.msg = "cmdq_rocee_tx_tail_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(25),
.msg = "cmdq_rocee_rx_head_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(27),
.msg = "cmdq_rocee_tx_head_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(29),
.msg = "cmdq_rocee_rx_addr_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(31),
.msg = "cmdq_rocee_tx_addr_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_tqp_int_ecc_int[] = {
{ .int_msk = BIT(6), .msg = "tqp_int_cfg_even_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(7), .msg = "tqp_int_cfg_odd_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(8), .msg = "tqp_int_ctrl_even_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(9), .msg = "tqp_int_ctrl_odd_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(10), .msg = "tx_que_scan_int_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(11), .msg = "rx_que_scan_int_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(6),
.msg = "tqp_int_cfg_even_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(7),
.msg = "tqp_int_cfg_odd_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(8),
.msg = "tqp_int_ctrl_even_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(9),
.msg = "tqp_int_ctrl_odd_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(10),
.msg = "tx_que_scan_int_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(11),
.msg = "rx_que_scan_int_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_msix_sram_ecc_int[] = {
{ .int_msk = BIT(1), .msg = "msix_nic_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(3), .msg = "msix_rocee_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(1),
.msg = "msix_nic_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(3),
.msg = "msix_rocee_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_igu_int[] = {
{ .int_msk = BIT(0), .msg = "igu_rx_buf0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "igu_rx_buf1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "igu_rx_buf0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "igu_rx_buf1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_igu_egu_tnl_int[] = {
{ .int_msk = BIT(0), .msg = "rx_buf_overflow",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(1), .msg = "rx_stp_fifo_overflow",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "rx_stp_fifo_underflow",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "tx_buf_overflow",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(4), .msg = "tx_buf_underrun",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "rx_stp_buf_overflow",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "rx_buf_overflow",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(1),
.msg = "rx_stp_fifo_overflow",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "rx_stp_fifo_underflow",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "tx_buf_overflow",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(4),
.msg = "tx_buf_underrun",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "rx_stp_buf_overflow",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ncsi_err_int[] = {
{ .int_msk = BIT(1), .msg = "ncsi_tx_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(1),
.msg = "ncsi_tx_ecc_mbit_err",
.reset_level = HNAE3_NONE_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ppp_mpf_abnormal_int_st1[] = {
{ .int_msk = BIT(0), .msg = "vf_vlan_ad_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(1), .msg = "umv_mcast_group_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "umv_key_mem0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "umv_key_mem1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(4), .msg = "umv_key_mem2_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "umv_key_mem3_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(6), .msg = "umv_ad_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(7), .msg = "rss_tc_mode_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(8), .msg = "rss_idt_mem0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(9), .msg = "rss_idt_mem1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(10), .msg = "rss_idt_mem2_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(11), .msg = "rss_idt_mem3_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(12), .msg = "rss_idt_mem4_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(13), .msg = "rss_idt_mem5_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(14), .msg = "rss_idt_mem6_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(15), .msg = "rss_idt_mem7_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(16), .msg = "rss_idt_mem8_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(17), .msg = "rss_idt_mem9_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(18), .msg = "rss_idt_mem10_ecc_m1bit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(19), .msg = "rss_idt_mem11_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(20), .msg = "rss_idt_mem12_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(21), .msg = "rss_idt_mem13_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(22), .msg = "rss_idt_mem14_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(23), .msg = "rss_idt_mem15_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(24), .msg = "port_vlan_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(25), .msg = "mcast_linear_table_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(26), .msg = "mcast_result_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(27), .msg = "flow_director_ad_mem0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(28), .msg = "flow_director_ad_mem1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(29), .msg = "rx_vlan_tag_memory_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(30), .msg = "Tx_UP_mapping_config_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "vf_vlan_ad_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(1),
.msg = "umv_mcast_group_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "umv_key_mem0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "umv_key_mem1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(4),
.msg = "umv_key_mem2_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "umv_key_mem3_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(6),
.msg = "umv_ad_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(7),
.msg = "rss_tc_mode_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(8),
.msg = "rss_idt_mem0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(9),
.msg = "rss_idt_mem1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(10),
.msg = "rss_idt_mem2_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(11),
.msg = "rss_idt_mem3_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(12),
.msg = "rss_idt_mem4_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(13),
.msg = "rss_idt_mem5_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(14),
.msg = "rss_idt_mem6_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(15),
.msg = "rss_idt_mem7_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(16),
.msg = "rss_idt_mem8_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(17),
.msg = "rss_idt_mem9_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(18),
.msg = "rss_idt_mem10_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(19),
.msg = "rss_idt_mem11_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(20),
.msg = "rss_idt_mem12_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(21),
.msg = "rss_idt_mem13_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(22),
.msg = "rss_idt_mem14_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(23),
.msg = "rss_idt_mem15_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(24),
.msg = "port_vlan_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(25),
.msg = "mcast_linear_table_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(26),
.msg = "mcast_result_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(27),
.msg = "flow_director_ad_mem0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(28),
.msg = "flow_director_ad_mem1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(29),
.msg = "rx_vlan_tag_memory_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(30),
.msg = "Tx_UP_mapping_config_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ppp_pf_abnormal_int[] = {
{ .int_msk = BIT(0), .msg = "tx_vlan_tag_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(1), .msg = "rss_list_tc_unassigned_queue_err",
.reset_level = HNAE3_NONE_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "tx_vlan_tag_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(1),
.msg = "rss_list_tc_unassigned_queue_err",
.reset_level = HNAE3_NONE_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ppp_mpf_abnormal_int_st3[] = {
{ .int_msk = BIT(0), .msg = "hfs_fifo_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(1), .msg = "rslt_descr_fifo_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "tx_vlan_tag_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "FD_CN0_memory_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(4), .msg = "FD_CN1_memory_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "GRO_AD_memory_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "hfs_fifo_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(1),
.msg = "rslt_descr_fifo_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "tx_vlan_tag_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "FD_CN0_memory_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(4),
.msg = "FD_CN1_memory_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "GRO_AD_memory_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_tm_sch_rint[] = {
{ .int_msk = BIT(1), .msg = "tm_sch_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "tm_sch_port_shap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "tm_sch_port_shap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(4), .msg = "tm_sch_pg_pshap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "tm_sch_pg_pshap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(6), .msg = "tm_sch_pg_cshap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(7), .msg = "tm_sch_pg_cshap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(8), .msg = "tm_sch_pri_pshap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(9), .msg = "tm_sch_pri_pshap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(10), .msg = "tm_sch_pri_cshap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(11), .msg = "tm_sch_pri_cshap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(12), .msg = "tm_sch_port_shap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(13), .msg = "tm_sch_port_shap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(14), .msg = "tm_sch_pg_pshap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(15), .msg = "tm_sch_pg_pshap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(16), .msg = "tm_sch_pg_cshap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(17), .msg = "tm_sch_pg_cshap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(18), .msg = "tm_sch_pri_pshap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(19), .msg = "tm_sch_pri_pshap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(20), .msg = "tm_sch_pri_cshap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(21), .msg = "tm_sch_pri_cshap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(22), .msg = "tm_sch_rq_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(23), .msg = "tm_sch_rq_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(24), .msg = "tm_sch_nq_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(25), .msg = "tm_sch_nq_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(26), .msg = "tm_sch_roce_up_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(27), .msg = "tm_sch_roce_up_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(28), .msg = "tm_sch_rcb_byte_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(29), .msg = "tm_sch_rcb_byte_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(30), .msg = "tm_sch_ssu_byte_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(31), .msg = "tm_sch_ssu_byte_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(1),
.msg = "tm_sch_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "tm_sch_port_shap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "tm_sch_port_shap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(4),
.msg = "tm_sch_pg_pshap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "tm_sch_pg_pshap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(6),
.msg = "tm_sch_pg_cshap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(7),
.msg = "tm_sch_pg_cshap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(8),
.msg = "tm_sch_pri_pshap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(9),
.msg = "tm_sch_pri_pshap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(10),
.msg = "tm_sch_pri_cshap_sub_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(11),
.msg = "tm_sch_pri_cshap_sub_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(12),
.msg = "tm_sch_port_shap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(13),
.msg = "tm_sch_port_shap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(14),
.msg = "tm_sch_pg_pshap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(15),
.msg = "tm_sch_pg_pshap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(16),
.msg = "tm_sch_pg_cshap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(17),
.msg = "tm_sch_pg_cshap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(18),
.msg = "tm_sch_pri_pshap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(19),
.msg = "tm_sch_pri_pshap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(20),
.msg = "tm_sch_pri_cshap_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(21),
.msg = "tm_sch_pri_cshap_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(22),
.msg = "tm_sch_rq_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(23),
.msg = "tm_sch_rq_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(24),
.msg = "tm_sch_nq_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(25),
.msg = "tm_sch_nq_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(26),
.msg = "tm_sch_roce_up_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(27),
.msg = "tm_sch_roce_up_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(28),
.msg = "tm_sch_rcb_byte_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(29),
.msg = "tm_sch_rcb_byte_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(30),
.msg = "tm_sch_ssu_byte_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(31),
.msg = "tm_sch_ssu_byte_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_qcn_fifo_rint[] = {
{ .int_msk = BIT(0), .msg = "qcn_shap_gp0_sch_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(1), .msg = "qcn_shap_gp0_sch_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "qcn_shap_gp1_sch_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "qcn_shap_gp1_sch_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(4), .msg = "qcn_shap_gp2_sch_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "qcn_shap_gp2_sch_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(6), .msg = "qcn_shap_gp3_sch_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(7), .msg = "qcn_shap_gp3_sch_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(8), .msg = "qcn_shap_gp0_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(9), .msg = "qcn_shap_gp0_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(10), .msg = "qcn_shap_gp1_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(11), .msg = "qcn_shap_gp1_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(12), .msg = "qcn_shap_gp2_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(13), .msg = "qcn_shap_gp2_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(14), .msg = "qcn_shap_gp3_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(15), .msg = "qcn_shap_gp3_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(16), .msg = "qcn_byte_info_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(17), .msg = "qcn_byte_info_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "qcn_shap_gp0_sch_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(1),
.msg = "qcn_shap_gp0_sch_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "qcn_shap_gp1_sch_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "qcn_shap_gp1_sch_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(4),
.msg = "qcn_shap_gp2_sch_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "qcn_shap_gp2_sch_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(6),
.msg = "qcn_shap_gp3_sch_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(7),
.msg = "qcn_shap_gp3_sch_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(8),
.msg = "qcn_shap_gp0_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(9),
.msg = "qcn_shap_gp0_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(10),
.msg = "qcn_shap_gp1_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(11),
.msg = "qcn_shap_gp1_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(12),
.msg = "qcn_shap_gp2_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(13),
.msg = "qcn_shap_gp2_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(14),
.msg = "qcn_shap_gp3_offset_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(15),
.msg = "qcn_shap_gp3_offset_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(16),
.msg = "qcn_byte_info_fifo_rd_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(17),
.msg = "qcn_byte_info_fifo_wr_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_qcn_ecc_rint[] = {
{ .int_msk = BIT(1), .msg = "qcn_byte_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "qcn_time_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "qcn_fb_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(7), .msg = "qcn_link_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(9), .msg = "qcn_rate_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(11), .msg = "qcn_tmplt_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(13), .msg = "qcn_shap_cfg_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(15), .msg = "qcn_gp0_barrel_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(17), .msg = "qcn_gp1_barrel_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(19), .msg = "qcn_gp2_barrel_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(21), .msg = "qcn_gp3_barral_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(1),
.msg = "qcn_byte_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "qcn_time_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "qcn_fb_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(7),
.msg = "qcn_link_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(9),
.msg = "qcn_rate_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(11),
.msg = "qcn_tmplt_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(13),
.msg = "qcn_shap_cfg_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(15),
.msg = "qcn_gp0_barrel_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(17),
.msg = "qcn_gp1_barrel_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(19),
.msg = "qcn_gp2_barrel_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(21),
.msg = "qcn_gp3_barral_mem_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_mac_afifo_tnl_int[] = {
{ .int_msk = BIT(0), .msg = "egu_cge_afifo_ecc_1bit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(1), .msg = "egu_cge_afifo_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "egu_lge_afifo_ecc_1bit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(3), .msg = "egu_lge_afifo_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(4), .msg = "cge_igu_afifo_ecc_1bit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(5), .msg = "cge_igu_afifo_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(6), .msg = "lge_igu_afifo_ecc_1bit_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(7), .msg = "lge_igu_afifo_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(8), .msg = "cge_igu_afifo_overflow_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(9), .msg = "lge_igu_afifo_overflow_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(10), .msg = "egu_cge_afifo_underrun_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(11), .msg = "egu_lge_afifo_underrun_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(12), .msg = "egu_ge_afifo_underrun_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(13), .msg = "ge_igu_afifo_overflow_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "egu_cge_afifo_ecc_1bit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(1),
.msg = "egu_cge_afifo_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "egu_lge_afifo_ecc_1bit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(3),
.msg = "egu_lge_afifo_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(4),
.msg = "cge_igu_afifo_ecc_1bit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(5),
.msg = "cge_igu_afifo_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(6),
.msg = "lge_igu_afifo_ecc_1bit_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(7),
.msg = "lge_igu_afifo_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(8),
.msg = "cge_igu_afifo_overflow_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(9),
.msg = "lge_igu_afifo_overflow_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(10),
.msg = "egu_cge_afifo_underrun_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(11),
.msg = "egu_lge_afifo_underrun_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(12),
.msg = "egu_ge_afifo_underrun_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(13),
.msg = "ge_igu_afifo_overflow_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st2[] = {
{ .int_msk = BIT(13), .msg = "rpu_rx_pkt_bit32_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(14), .msg = "rpu_rx_pkt_bit33_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(15), .msg = "rpu_rx_pkt_bit34_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(16), .msg = "rpu_rx_pkt_bit35_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(17), .msg = "rcb_tx_ring_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(18), .msg = "rcb_rx_ring_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(19), .msg = "rcb_tx_fbd_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(20), .msg = "rcb_rx_ebd_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(21), .msg = "rcb_tso_info_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(22), .msg = "rcb_tx_int_info_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(23), .msg = "rcb_rx_int_info_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(24), .msg = "tpu_tx_pkt_0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(25), .msg = "tpu_tx_pkt_1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(26), .msg = "rd_bus_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(27), .msg = "wr_bus_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(28), .msg = "reg_search_miss",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(29), .msg = "rx_q_search_miss",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(30), .msg = "ooo_ecc_err_detect",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(31), .msg = "ooo_ecc_err_multpl",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(13),
.msg = "rpu_rx_pkt_bit32_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(14),
.msg = "rpu_rx_pkt_bit33_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(15),
.msg = "rpu_rx_pkt_bit34_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(16),
.msg = "rpu_rx_pkt_bit35_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(17),
.msg = "rcb_tx_ring_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(18),
.msg = "rcb_rx_ring_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(19),
.msg = "rcb_tx_fbd_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(20),
.msg = "rcb_rx_ebd_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(21),
.msg = "rcb_tso_info_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(22),
.msg = "rcb_tx_int_info_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(23),
.msg = "rcb_rx_int_info_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(24),
.msg = "tpu_tx_pkt_0_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(25),
.msg = "tpu_tx_pkt_1_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(26),
.msg = "rd_bus_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(27),
.msg = "wr_bus_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(28),
.msg = "reg_search_miss",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(29),
.msg = "rx_q_search_miss",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(30),
.msg = "ooo_ecc_err_detect",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(31),
.msg = "ooo_ecc_err_multpl",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ppu_mpf_abnormal_int_st3[] = {
{ .int_msk = BIT(4), .msg = "gro_bd_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "gro_context_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(6), .msg = "rx_stash_cfg_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(7), .msg = "axi_rd_fbd_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(4),
.msg = "gro_bd_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "gro_context_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(6),
.msg = "rx_stash_cfg_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(7),
.msg = "axi_rd_fbd_ecc_mbit_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ppu_pf_abnormal_int[] = {
{ .int_msk = BIT(0), .msg = "over_8bd_no_fe",
.reset_level = HNAE3_FUNC_RESET },
{ .int_msk = BIT(1), .msg = "tso_mss_cmp_min_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(2), .msg = "tso_mss_cmp_max_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(3), .msg = "tx_rd_fbd_poison",
.reset_level = HNAE3_FUNC_RESET },
{ .int_msk = BIT(4), .msg = "rx_rd_ebd_poison",
.reset_level = HNAE3_FUNC_RESET },
{ .int_msk = BIT(5), .msg = "buf_wait_timeout",
.reset_level = HNAE3_NONE_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "over_8bd_no_fe",
.reset_level = HNAE3_FUNC_RESET
}, {
.int_msk = BIT(1),
.msg = "tso_mss_cmp_min_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(2),
.msg = "tso_mss_cmp_max_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(3),
.msg = "tx_rd_fbd_poison",
.reset_level = HNAE3_FUNC_RESET
}, {
.int_msk = BIT(4),
.msg = "rx_rd_ebd_poison",
.reset_level = HNAE3_FUNC_RESET
}, {
.int_msk = BIT(5),
.msg = "buf_wait_timeout",
.reset_level = HNAE3_NONE_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ssu_com_err_int[] = {
{ .int_msk = BIT(0), .msg = "buf_sum_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(1), .msg = "ppp_mb_num_err",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(2), .msg = "ppp_mbid_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "ppp_rlt_mac_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(4), .msg = "ppp_rlt_host_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "cks_edit_position_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(6), .msg = "cks_edit_condition_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(7), .msg = "vlan_edit_condition_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(8), .msg = "vlan_num_ot_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(9), .msg = "vlan_num_in_err",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "buf_sum_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(1),
.msg = "ppp_mb_num_err",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(2),
.msg = "ppp_mbid_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "ppp_rlt_mac_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(4),
.msg = "ppp_rlt_host_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "cks_edit_position_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(6),
.msg = "cks_edit_condition_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(7),
.msg = "vlan_edit_condition_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(8),
.msg = "vlan_num_ot_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(9),
.msg = "vlan_num_in_err",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
#define HCLGE_SSU_MEM_ECC_ERR(x) \
{ .int_msk = BIT(x), .msg = "ssu_mem" #x "_ecc_mbit_err", \
.reset_level = HNAE3_GLOBAL_RESET }
{ \
.int_msk = BIT(x), \
.msg = "ssu_mem" #x "_ecc_mbit_err", \
.reset_level = HNAE3_GLOBAL_RESET \
}
static const struct hclge_hw_error hclge_ssu_mem_ecc_err_int[] = {
HCLGE_SSU_MEM_ECC_ERR(0),
......@@ -504,131 +931,269 @@ static const struct hclge_hw_error hclge_ssu_mem_ecc_err_int[] = {
};
static const struct hclge_hw_error hclge_ssu_port_based_err_int[] = {
{ .int_msk = BIT(0), .msg = "roc_pkt_without_key_port",
.reset_level = HNAE3_FUNC_RESET },
{ .int_msk = BIT(1), .msg = "tpu_pkt_without_key_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "igu_pkt_without_key_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "roc_eof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(4), .msg = "tpu_eof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "igu_eof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(6), .msg = "roc_sof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(7), .msg = "tpu_sof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(8), .msg = "igu_sof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(11), .msg = "ets_rd_int_rx_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(12), .msg = "ets_wr_int_rx_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(13), .msg = "ets_rd_int_tx_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(14), .msg = "ets_wr_int_tx_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "roc_pkt_without_key_port",
.reset_level = HNAE3_FUNC_RESET
}, {
.int_msk = BIT(1),
.msg = "tpu_pkt_without_key_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "igu_pkt_without_key_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "roc_eof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(4),
.msg = "tpu_eof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "igu_eof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(6),
.msg = "roc_sof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(7),
.msg = "tpu_sof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(8),
.msg = "igu_sof_mis_match_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(11),
.msg = "ets_rd_int_rx_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(12),
.msg = "ets_wr_int_rx_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(13),
.msg = "ets_rd_int_tx_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(14),
.msg = "ets_wr_int_tx_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ssu_fifo_overflow_int[] = {
{ .int_msk = BIT(0), .msg = "ig_mac_inf_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(1), .msg = "ig_host_inf_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "ig_roc_buf_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "ig_host_data_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(4), .msg = "ig_host_key_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(5), .msg = "tx_qcn_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(6), .msg = "rx_qcn_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(7), .msg = "tx_pf_rd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(8), .msg = "rx_pf_rd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(9), .msg = "qm_eof_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(10), .msg = "mb_rlt_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(11), .msg = "dup_uncopy_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(12), .msg = "dup_cnt_rd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(13), .msg = "dup_cnt_drop_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(14), .msg = "dup_cnt_wrb_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(15), .msg = "host_cmd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(16), .msg = "mac_cmd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(17), .msg = "host_cmd_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(18), .msg = "mac_cmd_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(19), .msg = "dup_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(20), .msg = "out_queue_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(21), .msg = "bank2_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(22), .msg = "bank1_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(23), .msg = "bank0_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "ig_mac_inf_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(1),
.msg = "ig_host_inf_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "ig_roc_buf_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "ig_host_data_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(4),
.msg = "ig_host_key_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(5),
.msg = "tx_qcn_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(6),
.msg = "rx_qcn_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(7),
.msg = "tx_pf_rd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(8),
.msg = "rx_pf_rd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(9),
.msg = "qm_eof_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(10),
.msg = "mb_rlt_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(11),
.msg = "dup_uncopy_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(12),
.msg = "dup_cnt_rd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(13),
.msg = "dup_cnt_drop_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(14),
.msg = "dup_cnt_wrb_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(15),
.msg = "host_cmd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(16),
.msg = "mac_cmd_fifo_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(17),
.msg = "host_cmd_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(18),
.msg = "mac_cmd_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(19),
.msg = "dup_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(20),
.msg = "out_queue_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(21),
.msg = "bank2_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(22),
.msg = "bank1_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(23),
.msg = "bank0_bitmap_empty_int",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ssu_ets_tcg_int[] = {
{ .int_msk = BIT(0), .msg = "ets_rd_int_rx_tcg",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(1), .msg = "ets_wr_int_rx_tcg",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(2), .msg = "ets_rd_int_tx_tcg",
.reset_level = HNAE3_GLOBAL_RESET },
{ .int_msk = BIT(3), .msg = "ets_wr_int_tx_tcg",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "ets_rd_int_rx_tcg",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(1),
.msg = "ets_wr_int_rx_tcg",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(2),
.msg = "ets_rd_int_tx_tcg",
.reset_level = HNAE3_GLOBAL_RESET
}, {
.int_msk = BIT(3),
.msg = "ets_wr_int_tx_tcg",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_ssu_port_based_pf_int[] = {
{ .int_msk = BIT(0), .msg = "roc_pkt_without_key_port",
.reset_level = HNAE3_FUNC_RESET },
{ .int_msk = BIT(9), .msg = "low_water_line_err_port",
.reset_level = HNAE3_NONE_RESET },
{ .int_msk = BIT(10), .msg = "hi_water_line_err_port",
.reset_level = HNAE3_GLOBAL_RESET },
{ /* sentinel */ }
{
.int_msk = BIT(0),
.msg = "roc_pkt_without_key_port",
.reset_level = HNAE3_FUNC_RESET
}, {
.int_msk = BIT(9),
.msg = "low_water_line_err_port",
.reset_level = HNAE3_NONE_RESET
}, {
.int_msk = BIT(10),
.msg = "hi_water_line_err_port",
.reset_level = HNAE3_GLOBAL_RESET
}, {
/* sentinel */
}
};
static const struct hclge_hw_error hclge_rocee_qmm_ovf_err_int[] = {
{ .int_msk = 0, .msg = "rocee qmm ovf: sgid invalid err" },
{ .int_msk = 0x4, .msg = "rocee qmm ovf: sgid ovf err" },
{ .int_msk = 0x8, .msg = "rocee qmm ovf: smac invalid err" },
{ .int_msk = 0xC, .msg = "rocee qmm ovf: smac ovf err" },
{ .int_msk = 0x10, .msg = "rocee qmm ovf: cqc invalid err" },
{ .int_msk = 0x11, .msg = "rocee qmm ovf: cqc ovf err" },
{ .int_msk = 0x12, .msg = "rocee qmm ovf: cqc hopnum err" },
{ .int_msk = 0x13, .msg = "rocee qmm ovf: cqc ba0 err" },
{ .int_msk = 0x14, .msg = "rocee qmm ovf: srqc invalid err" },
{ .int_msk = 0x15, .msg = "rocee qmm ovf: srqc ovf err" },
{ .int_msk = 0x16, .msg = "rocee qmm ovf: srqc hopnum err" },
{ .int_msk = 0x17, .msg = "rocee qmm ovf: srqc ba0 err" },
{ .int_msk = 0x18, .msg = "rocee qmm ovf: mpt invalid err" },
{ .int_msk = 0x19, .msg = "rocee qmm ovf: mpt ovf err" },
{ .int_msk = 0x1A, .msg = "rocee qmm ovf: mpt hopnum err" },
{ .int_msk = 0x1B, .msg = "rocee qmm ovf: mpt ba0 err" },
{ .int_msk = 0x1C, .msg = "rocee qmm ovf: qpc invalid err" },
{ .int_msk = 0x1D, .msg = "rocee qmm ovf: qpc ovf err" },
{ .int_msk = 0x1E, .msg = "rocee qmm ovf: qpc hopnum err" },
{ .int_msk = 0x1F, .msg = "rocee qmm ovf: qpc ba0 err" },
{ /* sentinel */ }
{
.int_msk = 0,
.msg = "rocee qmm ovf: sgid invalid err"
}, {
.int_msk = 0x4,
.msg = "rocee qmm ovf: sgid ovf err"
}, {
.int_msk = 0x8,
.msg = "rocee qmm ovf: smac invalid err"
}, {
.int_msk = 0xC,
.msg = "rocee qmm ovf: smac ovf err"
}, {
.int_msk = 0x10,
.msg = "rocee qmm ovf: cqc invalid err"
}, {
.int_msk = 0x11,
.msg = "rocee qmm ovf: cqc ovf err"
}, {
.int_msk = 0x12,
.msg = "rocee qmm ovf: cqc hopnum err"
}, {
.int_msk = 0x13,
.msg = "rocee qmm ovf: cqc ba0 err"
}, {
.int_msk = 0x14,
.msg = "rocee qmm ovf: srqc invalid err"
}, {
.int_msk = 0x15,
.msg = "rocee qmm ovf: srqc ovf err"
}, {
.int_msk = 0x16,
.msg = "rocee qmm ovf: srqc hopnum err"
}, {
.int_msk = 0x17,
.msg = "rocee qmm ovf: srqc ba0 err"
}, {
.int_msk = 0x18,
.msg = "rocee qmm ovf: mpt invalid err"
}, {
.int_msk = 0x19,
.msg = "rocee qmm ovf: mpt ovf err"
}, {
.int_msk = 0x1A,
.msg = "rocee qmm ovf: mpt hopnum err"
}, {
.int_msk = 0x1B,
.msg = "rocee qmm ovf: mpt ba0 err"
}, {
.int_msk = 0x1C,
.msg = "rocee qmm ovf: qpc invalid err"
}, {
.int_msk = 0x1D,
.msg = "rocee qmm ovf: qpc ovf err"
}, {
.int_msk = 0x1E,
.msg = "rocee qmm ovf: qpc hopnum err"
}, {
.int_msk = 0x1F,
.msg = "rocee qmm ovf: qpc ba0 err"
}, {
/* sentinel */
}
};
static const struct hclge_hw_module_id hclge_hw_module_id_st[] = {
......@@ -1709,34 +2274,36 @@ static void hclge_handle_rocee_ras_error(struct hnae3_ae_dev *ae_dev)
static const struct hclge_hw_blk hw_blk[] = {
{
.msk = BIT(0), .name = "IGU_EGU",
.config_err_int = hclge_config_igu_egu_hw_err_int,
},
{
.msk = BIT(1), .name = "PPP",
.config_err_int = hclge_config_ppp_hw_err_int,
},
{
.msk = BIT(2), .name = "SSU",
.config_err_int = hclge_config_ssu_hw_err_int,
},
{
.msk = BIT(3), .name = "PPU",
.config_err_int = hclge_config_ppu_hw_err_int,
},
{
.msk = BIT(4), .name = "TM",
.config_err_int = hclge_config_tm_hw_err_int,
},
{
.msk = BIT(5), .name = "COMMON",
.config_err_int = hclge_config_common_hw_err_int,
},
{
.msk = BIT(8), .name = "MAC",
.config_err_int = hclge_config_mac_err_int,
},
{ /* sentinel */ }
.msk = BIT(0),
.name = "IGU_EGU",
.config_err_int = hclge_config_igu_egu_hw_err_int,
}, {
.msk = BIT(1),
.name = "PPP",
.config_err_int = hclge_config_ppp_hw_err_int,
}, {
.msk = BIT(2),
.name = "SSU",
.config_err_int = hclge_config_ssu_hw_err_int,
}, {
.msk = BIT(3),
.name = "PPU",
.config_err_int = hclge_config_ppu_hw_err_int,
}, {
.msk = BIT(4),
.name = "TM",
.config_err_int = hclge_config_tm_hw_err_int,
}, {
.msk = BIT(5),
.name = "COMMON",
.config_err_int = hclge_config_common_hw_err_int,
}, {
.msk = BIT(8),
.name = "MAC",
.config_err_int = hclge_config_mac_err_int,
}, {
/* sentinel */
}
};
static void hclge_config_all_msix_error(struct hclge_dev *hdev, bool enable)
......
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_ptp.h
View file @ 27c77943
......@@ -127,7 +127,7 @@ static inline struct hclge_dev *hclge_ptp_get_hdev(struct ptp_clock_info *info)
}
bool hclge_ptp_set_tx_info(struct hnae3_handle *handle, struct sk_buff *skb);
void hclge_ptp_clean_tx_hwts(struct hclge_dev *dev);
void hclge_ptp_clean_tx_hwts(struct hclge_dev *hdev);
void hclge_ptp_get_rx_hwts(struct hnae3_handle *handle, struct sk_buff *skb,
u32 nsec, u32 sec);
int hclge_ptp_get_cfg(struct hclge_dev *hdev, struct ifreq *ifr);
......
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