Commit 37e78949 authored by Parth Gajjar's avatar Parth Gajjar Committed by Michal Simek

arm64: zynqmp: Add mali-400 gpu node for zynqmp

Add mali-400 gpu node for zynqmp.
Enabled gpu node for xilinx boards.
Signed-off-by: default avatarParth Gajjar <parth.gajjar@amd.com>
Signed-off-by: default avatarVishal Sagar <vishal.sagar@amd.com>
Link: https://lore.kernel.org/r/20230321070619.29440-3-parth.gajjar@amd.comSigned-off-by: default avatarMichal Simek <michal.simek@amd.com>
parent 80550562
...@@ -95,6 +95,10 @@ &fpd_dma_chan8 { ...@@ -95,6 +95,10 @@ &fpd_dma_chan8 {
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>; clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
}; };
&gpu {
clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>;
};
&lpd_dma_chan1 { &lpd_dma_chan1 {
clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>; clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
}; };
......
...@@ -287,3 +287,7 @@ &gpio { ...@@ -287,3 +287,7 @@ &gpio {
"", "", "", "", "", /* 165 - 169 */ "", "", "", "", "", /* 165 - 169 */
"", "", "", ""; /* 170 - 173 */ "", "", "", ""; /* 170 - 173 */
}; };
&gpu {
status = "okay";
};
...@@ -108,6 +108,9 @@ &gpio { ...@@ -108,6 +108,9 @@ &gpio {
pinctrl-0 = <&pinctrl_gpio_default>; pinctrl-0 = <&pinctrl_gpio_default>;
}; };
&gpu {
status = "okay";
};
&i2c1 { &i2c1 {
status = "okay"; status = "okay";
......
...@@ -152,6 +152,10 @@ &gpio { ...@@ -152,6 +152,10 @@ &gpio {
status = "okay"; status = "okay";
}; };
&gpu {
status = "okay";
};
&i2c0 { &i2c0 {
clock-frequency = <400000>; clock-frequency = <400000>;
status = "okay"; status = "okay";
......
...@@ -161,6 +161,10 @@ &gpio { ...@@ -161,6 +161,10 @@ &gpio {
"", "", "", ""; "", "", "", "";
}; };
&gpu {
status = "okay";
};
&i2c1 { &i2c1 {
status = "okay"; status = "okay";
pinctrl-names = "default", "gpio"; pinctrl-names = "default", "gpio";
......
...@@ -216,6 +216,10 @@ &gpio { ...@@ -216,6 +216,10 @@ &gpio {
pinctrl-0 = <&pinctrl_gpio_default>; pinctrl-0 = <&pinctrl_gpio_default>;
}; };
&gpu {
status = "okay";
};
&i2c0 { &i2c0 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
......
...@@ -122,6 +122,10 @@ &gpio { ...@@ -122,6 +122,10 @@ &gpio {
status = "okay"; status = "okay";
}; };
&gpu {
status = "okay";
};
&i2c1 { &i2c1 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
......
...@@ -127,6 +127,10 @@ &gpio { ...@@ -127,6 +127,10 @@ &gpio {
status = "okay"; status = "okay";
}; };
&gpu {
status = "okay";
};
&i2c1 { &i2c1 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
......
...@@ -227,6 +227,10 @@ &gpio { ...@@ -227,6 +227,10 @@ &gpio {
pinctrl-0 = <&pinctrl_gpio_default>; pinctrl-0 = <&pinctrl_gpio_default>;
}; };
&gpu {
status = "okay";
};
&i2c0 { &i2c0 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
......
...@@ -187,6 +187,10 @@ &gpio { ...@@ -187,6 +187,10 @@ &gpio {
pinctrl-0 = <&pinctrl_gpio_default>; pinctrl-0 = <&pinctrl_gpio_default>;
}; };
&gpu {
status = "okay";
};
&i2c0 { &i2c0 {
status = "okay"; status = "okay";
clock-frequency = <400000>; clock-frequency = <400000>;
......
...@@ -411,6 +411,18 @@ gic: interrupt-controller@f9010000 { ...@@ -411,6 +411,18 @@ gic: interrupt-controller@f9010000 {
interrupts = <1 9 0xf04>; interrupts = <1 9 0xf04>;
}; };
gpu: gpu@fd4b0000 {
status = "disabled";
compatible = "xlnx,zynqmp-mali", "arm,mali-400";
reg = <0x0 0xfd4b0000 0x0 0x10000>;
interrupt-parent = <&gic>;
interrupts = <0 132 4>, <0 132 4>, <0 132 4>,
<0 132 4>, <0 132 4>, <0 132 4>;
interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1";
clock-names = "bus", "core";
power-domains = <&zynqmp_firmware PD_GPU>;
};
/* LPDDMA default allows only secured access. inorder to enable /* LPDDMA default allows only secured access. inorder to enable
* These dma channels, Users should ensure that these dma * These dma channels, Users should ensure that these dma
* Channels are allowed for non secure access. * Channels are allowed for non secure access.
......
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