Commit 39b2ca75 authored by Ravi Bangoria's avatar Ravi Bangoria Committed by Peter Zijlstra

perf/amd/ibs: Cascade pmu init functions' return value

IBS pmu initialization code ignores return value provided by
callee functions. Fix it.
Signed-off-by: default avatarRavi Bangoria <ravi.bangoria@amd.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220509044914.1473-2-ravi.bangoria@amd.com
parent f758bc5a
...@@ -777,9 +777,10 @@ static __init int perf_ibs_pmu_init(struct perf_ibs *perf_ibs, char *name) ...@@ -777,9 +777,10 @@ static __init int perf_ibs_pmu_init(struct perf_ibs *perf_ibs, char *name)
return ret; return ret;
} }
static __init void perf_event_ibs_init(void) static __init int perf_event_ibs_init(void)
{ {
struct attribute **attr = ibs_op_format_attrs; struct attribute **attr = ibs_op_format_attrs;
int ret;
/* /*
* Some chips fail to reset the fetch count when it is written; instead * Some chips fail to reset the fetch count when it is written; instead
...@@ -791,7 +792,9 @@ static __init void perf_event_ibs_init(void) ...@@ -791,7 +792,9 @@ static __init void perf_event_ibs_init(void)
if (boot_cpu_data.x86 == 0x19 && boot_cpu_data.x86_model < 0x10) if (boot_cpu_data.x86 == 0x19 && boot_cpu_data.x86_model < 0x10)
perf_ibs_fetch.fetch_ignore_if_zero_rip = 1; perf_ibs_fetch.fetch_ignore_if_zero_rip = 1;
perf_ibs_pmu_init(&perf_ibs_fetch, "ibs_fetch"); ret = perf_ibs_pmu_init(&perf_ibs_fetch, "ibs_fetch");
if (ret)
return ret;
if (ibs_caps & IBS_CAPS_OPCNT) { if (ibs_caps & IBS_CAPS_OPCNT) {
perf_ibs_op.config_mask |= IBS_OP_CNT_CTL; perf_ibs_op.config_mask |= IBS_OP_CNT_CTL;
...@@ -804,15 +807,35 @@ static __init void perf_event_ibs_init(void) ...@@ -804,15 +807,35 @@ static __init void perf_event_ibs_init(void)
perf_ibs_op.cnt_mask |= IBS_OP_MAX_CNT_EXT_MASK; perf_ibs_op.cnt_mask |= IBS_OP_MAX_CNT_EXT_MASK;
} }
perf_ibs_pmu_init(&perf_ibs_op, "ibs_op"); ret = perf_ibs_pmu_init(&perf_ibs_op, "ibs_op");
if (ret)
goto err_op;
ret = register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ibs");
if (ret)
goto err_nmi;
register_nmi_handler(NMI_LOCAL, perf_ibs_nmi_handler, 0, "perf_ibs");
pr_info("perf: AMD IBS detected (0x%08x)\n", ibs_caps); pr_info("perf: AMD IBS detected (0x%08x)\n", ibs_caps);
return 0;
err_nmi:
perf_pmu_unregister(&perf_ibs_op.pmu);
free_percpu(perf_ibs_op.pcpu);
perf_ibs_op.pcpu = NULL;
err_op:
perf_pmu_unregister(&perf_ibs_fetch.pmu);
free_percpu(perf_ibs_fetch.pcpu);
perf_ibs_fetch.pcpu = NULL;
return ret;
} }
#else /* defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) */ #else /* defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) */
static __init void perf_event_ibs_init(void) { } static __init int perf_event_ibs_init(void)
{
return 0;
}
#endif #endif
...@@ -1082,9 +1105,7 @@ static __init int amd_ibs_init(void) ...@@ -1082,9 +1105,7 @@ static __init int amd_ibs_init(void)
x86_pmu_amd_ibs_starting_cpu, x86_pmu_amd_ibs_starting_cpu,
x86_pmu_amd_ibs_dying_cpu); x86_pmu_amd_ibs_dying_cpu);
perf_event_ibs_init(); return perf_event_ibs_init();
return 0;
} }
/* Since we need the pci subsystem to init ibs we can't do this earlier: */ /* Since we need the pci subsystem to init ibs we can't do this earlier: */
......
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