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Commit 44b5814f authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'qcom-arm64-fixes-for-6.4' of... 

Merge tag 'qcom-arm64-fixes-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/fixes

Qualcomm ARM64 DeviceTree fixes for 6.4

Register scheme for SM8550 LLCC is corrected to avoid using the wrong
register offsets. SDRAM frequency for misidentified SC7180-lite boards
is handled. The datatype for Soundwire interval on SM8550 is corrected.

The resource controller on SC8280XP is added to the CPU cluster
power-domain to get notified to send cached sleep and wake votes before
going entering the lower power states.

SA8155P power-domains that differ from what's inherited from the SM8150
DeviceTree are adjusted to make the platform boot again.

Remoteproc firmware paths are corrected for Sony Xperia 10 IV.

Cache properties are adjusted across a range of platforms, to meet
changes in the binding.

Panel compatibles are corrected for Xiaomi Mi Pad 5 Pro, to match
binding. Invalid dai-cells are dropped from SC7280 devices, to match
binding.

The incorrect removal of "input-enable" from the LPASS pinctrl node of
SC8280XP was reverted, to get dmic pins in the correct state again.

The incorrect input-enable property is dropped from a msm8974, mdm9615
and apq8026 to resolve a range of DT validation warnings, incorrectly
picked up through the ARM64 tree.

* tag 'qcom-arm64-fixes-for-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  arm64: dts: qcom: sm8550: Use the correct LLCC register scheme
  arm64: dts: qcom: sc7180-lite: Fix SDRAM freq for misidentified sc7180-lite boards
  arm64: dts: qcom: sm8550: use uint16 for Soundwire interval
  arm64: dts: qcom: Split out SA8155P and use correct RPMh power domains
  arm64: dts: qcom: sm6375-pdx225: Fix remoteproc firmware paths
  arm64: dts: qcom: add missing cache properties
  arm64: dts: qcom: use decimal for cache level
  arm64: dts: qcom: fix indentation
  ARM: dts: qcom: msm8974: remove superfluous "input-enable"
  ARM: dts: qcom: mdm9615: remove superfluous "input-enable"
  ARM: dts: qcom: apq8026: remove superfluous "input-enable"
  arm64: dts: qcom: sm8250-xiaomi-elish-csot: fix panel compatible
  arm64: dts: qcom: sm8250-xiaomi-elish-boe: fix panel compatible
  arm64: dts: qcom: sc7280-qcard: drop incorrect dai-cells from WCD938x SDW
  arm64: dts: qcom: sc7280-idp: drop incorrect dai-cells from WCD938x SDW
  arm64: dts: qcom: sc8280xp: Flush RSC sleep & wake votes
  arm64: dts: qcom: sc8280xp: Revert "arm64: dts: qcom: sc8280xp: remove superfluous "input-enable""

Link: https://lore.kernel.org/r/20230601142659.2246348-1-andersson@kernel.orgSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents be02e1fc 661a4f08
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Showing with 322 additions and 112 deletions
arch/arm/boot/dts/qcom-apq8026-asus-sparrow.dts
View file @ 44b5814f
......@@ -268,7 +268,6 @@ bluetooth_default_state: bluetooth-default-state {
function = "gpio";
drive-strength = <8>;
bias-disable;
input-enable;
};
wlan_hostwake_default_state: wlan-hostwake-default-state {
......@@ -276,7 +275,6 @@ wlan_hostwake_default_state: wlan-hostwake-default-state {
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
wlan_regulator_default_state: wlan-regulator-default-state {
......
arch/arm/boot/dts/qcom-apq8026-huawei-sturgeon.dts
View file @ 44b5814f
......@@ -352,7 +352,6 @@ wlan_hostwake_default_state: wlan-hostwake-default-state {
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
wlan_regulator_default_state: wlan-regulator-default-state {
......
arch/arm/boot/dts/qcom-apq8026-lg-lenok.dts
View file @ 44b5814f
......@@ -307,7 +307,6 @@ bluetooth_default_state: bluetooth-default-state {
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
touch_pins: touch-state {
......@@ -317,7 +316,6 @@ irq-pins {
drive-strength = <8>;
bias-pull-down;
input-enable;
};
reset-pins {
......@@ -335,7 +333,6 @@ wlan_hostwake_default_state: wlan-hostwake-default-state {
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
wlan_regulator_default_state: wlan-regulator-default-state {
......
arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dts
View file @ 44b5814f
......@@ -49,7 +49,6 @@ gpioext1_pins: gpioext1-state {
gpioext1-pins {
pins = "gpio2";
function = "gpio";
input-enable;
bias-disable;
};
};
......
arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts
View file @ 44b5814f
......@@ -592,7 +592,6 @@ mpu6515_pin: mpu6515-state {
pins = "gpio73";
function = "gpio";
bias-disable;
input-enable;
};
touch_pin: touch-state {
......@@ -602,7 +601,6 @@ int-pins {
drive-strength = <2>;
bias-disable;
input-enable;
};
reset-pins {
......
arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi
View file @ 44b5814f
......@@ -433,7 +433,6 @@ ts_int_pin: touch-int-state {
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
sdc1_on: sdc1-on-state {
......
arch/arm/boot/dts/qcom-msm8974pro-oneplus-bacon.dts
View file @ 44b5814f
......@@ -461,7 +461,6 @@ int-pins {
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
reset-pins {
......
arch/arm/boot/dts/qcom-msm8974pro-samsung-klte.dts
View file @ 44b5814f
......@@ -704,7 +704,6 @@ hostwake-pins {
pins = "gpio75";
function = "gpio";
drive-strength = <16>;
input-enable;
};
devwake-pins {
......@@ -760,14 +759,12 @@ cmd-data-pins {
i2c_touchkey_pins: i2c-touchkey-state {
pins = "gpio95", "gpio96";
function = "gpio";
input-enable;
bias-pull-up;
};
i2c_led_gpioex_pins: i2c-led-gpioex-state {
pins = "gpio120", "gpio121";
function = "gpio";
input-enable;
bias-pull-down;
};
......@@ -781,7 +778,6 @@ gpioex_pin: gpioex-state {
wifi_pin: wifi-state {
pins = "gpio92";
function = "gpio";
input-enable;
bias-pull-down;
};
......
arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts
View file @ 44b5814f
......@@ -631,7 +631,6 @@ ts_int_pin: ts-int-pin-state {
function = "gpio";
drive-strength = <2>;
bias-disable;
input-enable;
};
bt_host_wake_pin: bt-host-wake-state {
......
arch/arm64/boot/dts/qcom/ipq5332.dtsi
View file @ 44b5814f
......@@ -73,6 +73,7 @@ CPU3: cpu@3 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View file @ 44b5814f
......@@ -83,7 +83,8 @@ CPU3: cpu@3 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <0x2>;
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View file @ 44b5814f
......@@ -66,7 +66,8 @@ CPU3: cpu@3 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <0x2>;
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/ipq9574.dtsi
View file @ 44b5814f
......@@ -72,6 +72,7 @@ CPU3: cpu@3 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/msm8916.dtsi
View file @ 44b5814f
......@@ -180,6 +180,7 @@ CPU3: cpu@3 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
idle-states {
......
arch/arm64/boot/dts/qcom/msm8953.dtsi
View file @ 44b5814f
......@@ -153,11 +153,13 @@ core3 {
L2_0: l2-cache-0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
L2_1: l2-cache-1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/msm8976.dtsi
View file @ 44b5814f
......@@ -193,11 +193,13 @@ big_cpu_sleep_1: cpu-sleep-1-1 {
l2_0: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
l2_1: l2-cache1 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/msm8994.dtsi
View file @ 44b5814f
......@@ -52,6 +52,7 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......@@ -88,6 +89,7 @@ CPU4: cpu@100 {
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/msm8996.dtsi
View file @ 44b5814f
......@@ -53,8 +53,9 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......@@ -83,8 +84,9 @@ CPU2: cpu@100 {
#cooling-cells = <2>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/msm8998.dtsi
View file @ 44b5814f
......@@ -146,6 +146,7 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......@@ -190,6 +191,7 @@ CPU4: cpu@100 {
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/qcm2290.dtsi
View file @ 44b5814f
......@@ -51,6 +51,7 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/qcs404.dtsi
View file @ 44b5814f
......@@ -95,6 +95,7 @@ CPU3: cpu@103 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
idle-states {
......
arch/arm64/boot/dts/qcom/qdu1000.dtsi
View file @ 44b5814f
......@@ -35,9 +35,13 @@ CPU0: cpu@0 {
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -54,6 +58,8 @@ CPU1: cpu@100 {
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -70,6 +76,8 @@ CPU2: cpu@200 {
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -86,6 +94,8 @@ CPU3: cpu@300 {
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sa8155p-adp.dts
View file @ 44b5814f
......@@ -7,7 +7,7 @@
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/gpio/gpio.h>
#include "sm8150.dtsi"
#include "sa8155p.dtsi"
#include "pmm8155au_1.dtsi"
#include "pmm8155au_2.dtsi"
......
arch/arm64/boot/dts/qcom/sa8155p.dtsi 0 → 100644
View file @ 44b5814f
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2023, Linaro Limited
*
* SA8155P is an automotive variant of SM8150, with some minor changes.
* Most notably, the RPMhPD setup differs: MMCX and LCX/LMX rails are gone,
* though the cmd-db doesn't reflect that and access attemps result in a bite.
*/
#include "sm8150.dtsi"
&dispcc {
power-domains = <&rpmhpd SA8155P_CX>;
};
&mdss_dsi0 {
power-domains = <&rpmhpd SA8155P_CX>;
};
&mdss_dsi1 {
power-domains = <&rpmhpd SA8155P_CX>;
};
&mdss_mdp {
power-domains = <&rpmhpd SA8155P_CX>;
};
&remoteproc_slpi {
power-domains = <&rpmhpd SA8155P_CX>,
<&rpmhpd SA8155P_MX>;
};
&rpmhpd {
/*
* The bindings were crafted such that SA8155P PDs match their
* SM8150 counterparts to make it more maintainable and only
* necessitate adjusting entries that actually differ
*/
compatible = "qcom,sa8155p-rpmhpd";
};
arch/arm64/boot/dts/qcom/sa8775p.dtsi
View file @ 44b5814f
......@@ -42,9 +42,13 @@ CPU0: cpu@0 {
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -58,6 +62,8 @@ CPU1: cpu@100 {
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -71,6 +77,8 @@ CPU2: cpu@200 {
next-level-cache = <&L2_2>;
L2_2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -84,6 +92,8 @@ CPU3: cpu@300 {
next-level-cache = <&L2_3>;
L2_3: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -97,9 +107,13 @@ CPU4: cpu@10000 {
next-level-cache = <&L2_4>;
L2_4: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_1>;
L3_1: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
......@@ -114,6 +128,8 @@ CPU5: cpu@10100 {
next-level-cache = <&L2_5>;
L2_5: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_1>;
};
};
......@@ -127,6 +143,8 @@ CPU6: cpu@10200 {
next-level-cache = <&L2_6>;
L2_6: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_1>;
};
};
......@@ -140,6 +158,8 @@ CPU7: cpu@10300 {
next-level-cache = <&L2_7>;
L2_7: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_1>;
};
};
......
arch/arm64/boot/dts/qcom/sc7180-lite.dtsi
View file @ 44b5814f
......@@ -16,3 +16,11 @@ &cpu6_opp11 {
&cpu6_opp12 {
opp-peak-kBps = <8532000 23347200>;
};
&cpu6_opp13 {
opp-peak-kBps = <8532000 23347200>;
};
&cpu6_opp14 {
opp-peak-kBps = <8532000 23347200>;
};
arch/arm64/boot/dts/qcom/sc7180.dtsi
View file @ 44b5814f
......@@ -92,10 +92,12 @@ &LITTLE_CPU_SLEEP_1
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -120,6 +122,7 @@ &LITTLE_CPU_SLEEP_1
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -144,6 +147,7 @@ &LITTLE_CPU_SLEEP_1
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -168,6 +172,7 @@ &LITTLE_CPU_SLEEP_1
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -192,6 +197,7 @@ &LITTLE_CPU_SLEEP_1
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -216,6 +222,7 @@ &LITTLE_CPU_SLEEP_1
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -240,6 +247,7 @@ &BIG_CPU_SLEEP_1
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -264,6 +272,7 @@ &BIG_CPU_SLEEP_1
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
View file @ 44b5814f
......@@ -480,7 +480,6 @@ &swr0 {
wcd_rx: codec@0,4 {
compatible = "sdw20217010d00";
reg = <0 4>;
#sound-dai-cells = <1>;
qcom,rx-port-mapping = <1 2 3 4 5>;
};
};
......@@ -491,7 +490,6 @@ &swr1 {
wcd_tx: codec@0,3 {
compatible = "sdw20217010d00";
reg = <0 3>;
#sound-dai-cells = <1>;
qcom,tx-port-mapping = <1 2 3 4>;
};
};
......
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi
View file @ 44b5814f
......@@ -414,7 +414,6 @@ &swr0 {
wcd_rx: codec@0,4 {
compatible = "sdw20217010d00";
reg = <0 4>;
#sound-dai-cells = <1>;
qcom,rx-port-mapping = <1 2 3 4 5>;
};
};
......@@ -423,7 +422,6 @@ &swr1 {
wcd_tx: codec@0,3 {
compatible = "sdw20217010d00";
reg = <0 3>;
#sound-dai-cells = <1>;
qcom,tx-port-mapping = <1 2 3 4>;
};
};
......
arch/arm64/boot/dts/qcom/sc7280.dtsi
View file @ 44b5814f
......@@ -182,10 +182,12 @@ &LITTLE_CPU_SLEEP_1
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -208,6 +210,7 @@ &LITTLE_CPU_SLEEP_1
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -230,6 +233,7 @@ &LITTLE_CPU_SLEEP_1
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -252,6 +256,7 @@ &LITTLE_CPU_SLEEP_1
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -274,6 +279,7 @@ &BIG_CPU_SLEEP_1
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -296,6 +302,7 @@ &BIG_CPU_SLEEP_1
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -318,6 +325,7 @@ &BIG_CPU_SLEEP_1
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -340,6 +348,7 @@ &BIG_CPU_SLEEP_1
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sc8280xp.dtsi
View file @ 44b5814f
......@@ -58,10 +58,12 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -83,6 +85,7 @@ CPU1: cpu@100 {
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -104,6 +107,7 @@ CPU2: cpu@200 {
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -125,6 +129,7 @@ CPU3: cpu@300 {
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -146,6 +151,7 @@ CPU4: cpu@400 {
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -167,6 +173,7 @@ CPU5: cpu@500 {
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -188,6 +195,7 @@ CPU6: cpu@600 {
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -209,6 +217,7 @@ CPU7: cpu@700 {
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -2726,6 +2735,7 @@ data-pins {
pins = "gpio7";
function = "dmic1_data";
drive-strength = <8>;
input-enable;
};
};
......@@ -2743,6 +2753,7 @@ data-pins {
function = "dmic1_data";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
};
......@@ -2758,6 +2769,7 @@ data-pins {
pins = "gpio9";
function = "dmic2_data";
drive-strength = <8>;
input-enable;
};
};
......@@ -2775,6 +2787,7 @@ data-pins {
function = "dmic2_data";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
};
......@@ -3982,6 +3995,7 @@ apps_rsc: rsc@18200000 {
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
<WAKE_TCS 3>, <CONTROL_TCS 1>;
label = "apps_rsc";
power-domains = <&CLUSTER_PD>;
apps_bcm_voter: bcm-voter {
compatible = "qcom,bcm-voter";
......
arch/arm64/boot/dts/qcom/sdm630.dtsi
View file @ 44b5814f
......@@ -63,6 +63,7 @@ &PERF_CLUSTER_SLEEP_1
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......@@ -127,6 +128,7 @@ &PWR_CLUSTER_SLEEP_1
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/sdm670.dtsi
View file @ 44b5814f
......@@ -41,8 +41,12 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
cache-level = <2>;
cache-unified;
L3_0: l3-cache {
compatible = "cache";
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -57,6 +61,8 @@ CPU1: cpu@100 {
next-level-cache = <&L2_100>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -71,6 +77,8 @@ CPU2: cpu@200 {
next-level-cache = <&L2_200>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -85,6 +93,8 @@ CPU3: cpu@300 {
next-level-cache = <&L2_300>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -99,6 +109,8 @@ CPU4: cpu@400 {
next-level-cache = <&L2_400>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -113,6 +125,8 @@ CPU5: cpu@500 {
next-level-cache = <&L2_500>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -127,6 +141,8 @@ CPU6: cpu@600 {
next-level-cache = <&L2_600>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -141,6 +157,8 @@ CPU7: cpu@700 {
next-level-cache = <&L2_700>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file @ 44b5814f
......@@ -108,10 +108,12 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -135,6 +137,7 @@ CPU1: cpu@100 {
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -158,6 +161,7 @@ CPU2: cpu@200 {
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -181,6 +185,7 @@ CPU3: cpu@300 {
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -204,6 +209,7 @@ CPU4: cpu@400 {
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -227,6 +233,7 @@ CPU5: cpu@500 {
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -250,6 +257,7 @@ CPU6: cpu@600 {
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -273,6 +281,7 @@ CPU7: cpu@700 {
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sm6115.dtsi
View file @ 44b5814f
......@@ -50,6 +50,7 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......@@ -102,6 +103,7 @@ CPU4: cpu@100 {
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/sm6125.dtsi
View file @ 44b5814f
......@@ -47,6 +47,7 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......@@ -87,6 +88,7 @@ CPU4: cpu@100 {
L2_1: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
......
arch/arm64/boot/dts/qcom/sm6350.dtsi
View file @ 44b5814f
......@@ -60,10 +60,12 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -86,6 +88,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -108,6 +111,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -130,6 +134,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -152,6 +157,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -174,6 +180,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -196,6 +203,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -218,6 +226,7 @@ &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ACTIVE_ONLY>,
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts
View file @ 44b5814f
......@@ -178,12 +178,12 @@ &qupv3_id_1 {
};
&remoteproc_adsp {
firmware-name = "qcom/Sony/murray/adsp.mbn";
firmware-name = "qcom/sm6375/Sony/murray/adsp.mbn";
status = "okay";
};
&remoteproc_cdsp {
firmware-name = "qcom/Sony/murray/cdsp.mbn";
firmware-name = "qcom/sm6375/Sony/murray/cdsp.mbn";
status = "okay";
};
......
arch/arm64/boot/dts/qcom/sm6375.dtsi
View file @ 44b5814f
......@@ -48,10 +48,14 @@ CPU0: cpu@0 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -68,8 +72,10 @@ CPU1: cpu@100 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -85,8 +91,10 @@ CPU2: cpu@200 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -102,8 +110,10 @@ CPU3: cpu@300 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -119,8 +129,10 @@ CPU4: cpu@400 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -136,8 +148,10 @@ CPU5: cpu@500 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -153,8 +167,10 @@ CPU6: cpu@600 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -170,8 +186,10 @@ CPU7: cpu@700 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sm8150.dtsi
View file @ 44b5814f
......@@ -63,10 +63,12 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -90,6 +92,7 @@ CPU1: cpu@100 {
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -113,6 +116,7 @@ CPU2: cpu@200 {
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -136,6 +140,7 @@ CPU3: cpu@300 {
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -159,6 +164,7 @@ CPU4: cpu@400 {
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -182,6 +188,7 @@ CPU5: cpu@500 {
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -205,6 +212,7 @@ CPU6: cpu@600 {
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -228,6 +236,7 @@ CPU7: cpu@700 {
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-boe.dts
View file @ 44b5814f
......@@ -13,6 +13,6 @@ / {
};
&display_panel {
compatible = "xiaomi,elish-boe-nt36523";
compatible = "xiaomi,elish-boe-nt36523", "novatek,nt36523";
status = "okay";
};
arch/arm64/boot/dts/qcom/sm8250-xiaomi-elish-csot.dts
View file @ 44b5814f
......@@ -13,6 +13,6 @@ / {
};
&display_panel {
compatible = "xiaomi,elish-csot-nt36523";
compatible = "xiaomi,elish-csot-nt36523", "novatek,nt36523";
status = "okay";
};
arch/arm64/boot/dts/qcom/sm8350.dtsi
View file @ 44b5814f
......@@ -58,12 +58,14 @@ CPU0: cpu@0 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -80,9 +82,10 @@ CPU1: cpu@100 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -98,9 +101,10 @@ CPU2: cpu@200 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -116,9 +120,10 @@ CPU3: cpu@300 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -134,9 +139,10 @@ CPU4: cpu@400 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -152,9 +158,10 @@ CPU5: cpu@500 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -170,9 +177,10 @@ CPU6: cpu@600 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -188,9 +196,10 @@ CPU7: cpu@700 {
power-domain-names = "psci";
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sm8450.dtsi
View file @ 44b5814f
......@@ -57,12 +57,14 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -79,9 +81,10 @@ CPU1: cpu@100 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -97,9 +100,10 @@ CPU2: cpu@200 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -115,9 +119,10 @@ CPU3: cpu@300 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 0>;
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -133,9 +138,10 @@ CPU4: cpu@400 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 1>;
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -151,9 +157,10 @@ CPU5: cpu@500 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 1>;
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -169,9 +176,10 @@ CPU6: cpu@600 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 1>;
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -187,9 +195,10 @@ CPU7: cpu@700 {
#cooling-cells = <2>;
clocks = <&cpufreq_hw 2>;
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
next-level-cache = <&L3_0>;
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......
arch/arm64/boot/dts/qcom/sm8550.dtsi
View file @ 44b5814f
......@@ -80,10 +80,12 @@ CPU0: cpu@0 {
L2_0: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "cache";
cache-level = <3>;
cache-unified;
};
};
};
......@@ -104,6 +106,7 @@ CPU1: cpu@100 {
L2_100: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -124,6 +127,7 @@ CPU2: cpu@200 {
L2_200: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -144,6 +148,7 @@ CPU3: cpu@300 {
L2_300: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -164,6 +169,7 @@ CPU4: cpu@400 {
L2_400: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -184,6 +190,7 @@ CPU5: cpu@500 {
L2_500: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -204,6 +211,7 @@ CPU6: cpu@600 {
L2_600: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -224,6 +232,7 @@ CPU7: cpu@700 {
L2_700: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
next-level-cache = <&L3_0>;
};
};
......@@ -2022,7 +2031,7 @@ swr3: soundwire-controller@6ab0000 {
qcom,din-ports = <4>;
qcom,dout-ports = <9>;
qcom,ports-sinterval = <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
......@@ -2068,7 +2077,7 @@ swr1: soundwire-controller@6ad0000 {
qcom,din-ports = <0>;
qcom,dout-ports = <10>;
qcom,ports-sinterval = <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>;
qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff>;
qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff>;
qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff>;
qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff>;
......@@ -2133,7 +2142,7 @@ swr0: soundwire-controller@6b10000 {
qcom,din-ports = <4>;
qcom,dout-ports = <9>;
qcom,ports-sinterval = <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
......@@ -3762,9 +3771,16 @@ gem_noc: interconnect@24100000 {
system-cache-controller@25000000 {
compatible = "qcom,sm8550-llcc";
reg = <0 0x25000000 0 0x800000>,
reg = <0 0x25000000 0 0x200000>,
<0 0x25200000 0 0x200000>,
<0 0x25400000 0 0x200000>,
<0 0x25600000 0 0x200000>,
<0 0x25800000 0 0x200000>;
reg-names = "llcc_base", "llcc_broadcast_base";
reg-names = "llcc0_base",
"llcc1_base",
"llcc2_base",
"llcc3_base",
"llcc_broadcast_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
};
......
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