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Commit 46bdcac5 authored by Odelu Kukatla's avatar Odelu Kukatla Committed by Georgi Djakov
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interconnect: qcom: Add SC7280 interconnect provider driver 

Add driver for the Qualcomm interconnect buses found in SC7280 based
platforms. The topology consists of several NoCs that are controlled by
a remote processor that collects the aggregated bandwidth for each
master-slave pairs.
Signed-off-by: default avatarOdelu Kukatla <okukatla@codeaurora.org>
Link: https://lore.kernel.org/r/1619517059-12109-3-git-send-email-okukatla@codeaurora.orgSigned-off-by: default avatarGeorgi Djakov <djakov@kernel.org>
parent 0b889618
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drivers/interconnect/qcom/Kconfig
View file @ 46bdcac5
......@@ -74,6 +74,15 @@ config INTERCONNECT_QCOM_SC7180
This is a driver for the Qualcomm Network-on-Chip on sc7180-based
platforms.
config INTERCONNECT_QCOM_SC7280
tristate "Qualcomm SC7280 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
help
This is a driver for the Qualcomm Network-on-Chip on sc7280-based
platforms.
config INTERCONNECT_QCOM_SDM660
tristate "Qualcomm SDM660 interconnect driver"
depends on INTERCONNECT_QCOM
......
drivers/interconnect/qcom/Makefile
View file @ 46bdcac5
......@@ -8,6 +8,7 @@ icc-osm-l3-objs := osm-l3.o
qnoc-qcs404-objs := qcs404.o
icc-rpmh-obj := icc-rpmh.o
qnoc-sc7180-objs := sc7180.o
qnoc-sc7280-objs := sc7280.o
qnoc-sdm660-objs := sdm660.o
qnoc-sdm845-objs := sdm845.o
qnoc-sdx55-objs := sdx55.o
......@@ -24,6 +25,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
obj-$(CONFIG_INTERCONNECT_QCOM_SC7280) += qnoc-sc7280.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDM660) += qnoc-sdm660.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o
......
drivers/interconnect/qcom/sc7280.c 0 → 100644
View file @ 46bdcac5
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*
*/
#include <linux/device.h>
#include <linux/interconnect.h>
#include <linux/interconnect-provider.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include "bcm-voter.h"
#include "icc-rpmh.h"
#include "sc7280.h"
static struct qcom_icc_node qhm_qspi = {
.name = "qhm_qspi",
.id = SC7280_MASTER_QSPI_0,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_SLAVE_A1NOC_SNOC },
};
static struct qcom_icc_node qhm_qup0 = {
.name = "qhm_qup0",
.id = SC7280_MASTER_QUP_0,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_SLAVE_A1NOC_SNOC },
};
static struct qcom_icc_node qhm_qup1 = {
.name = "qhm_qup1",
.id = SC7280_MASTER_QUP_1,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_SLAVE_A1NOC_SNOC },
};
static struct qcom_icc_node qnm_a1noc_cfg = {
.name = "qnm_a1noc_cfg",
.id = SC7280_MASTER_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_SLAVE_SERVICE_A1NOC },
};
static struct qcom_icc_node xm_sdc1 = {
.name = "xm_sdc1",
.id = SC7280_MASTER_SDCC_1,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_SLAVE_A1NOC_SNOC },
};
static struct qcom_icc_node xm_sdc2 = {
.name = "xm_sdc2",
.id = SC7280_MASTER_SDCC_2,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_SLAVE_A1NOC_SNOC },
};
static struct qcom_icc_node xm_sdc4 = {
.name = "xm_sdc4",
.id = SC7280_MASTER_SDCC_4,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_SLAVE_A1NOC_SNOC },
};
static struct qcom_icc_node xm_ufs_mem = {
.name = "xm_ufs_mem",
.id = SC7280_MASTER_UFS_MEM,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_SLAVE_A1NOC_SNOC },
};
static struct qcom_icc_node xm_usb2 = {
.name = "xm_usb2",
.id = SC7280_MASTER_USB2,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_SLAVE_A1NOC_SNOC },
};
static struct qcom_icc_node xm_usb3_0 = {
.name = "xm_usb3_0",
.id = SC7280_MASTER_USB3_0,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_SLAVE_A1NOC_SNOC },
};
static struct qcom_icc_node qhm_qdss_bam = {
.name = "qhm_qdss_bam",
.id = SC7280_MASTER_QDSS_BAM,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_SLAVE_A2NOC_SNOC },
};
static struct qcom_icc_node qnm_a2noc_cfg = {
.name = "qnm_a2noc_cfg",
.id = SC7280_MASTER_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_SLAVE_SERVICE_A2NOC },
};
static struct qcom_icc_node qnm_cnoc_datapath = {
.name = "qnm_cnoc_datapath",
.id = SC7280_MASTER_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_SLAVE_A2NOC_SNOC },
};
static struct qcom_icc_node qxm_crypto = {
.name = "qxm_crypto",
.id = SC7280_MASTER_CRYPTO,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_SLAVE_A2NOC_SNOC },
};
static struct qcom_icc_node qxm_ipa = {
.name = "qxm_ipa",
.id = SC7280_MASTER_IPA,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_SLAVE_A2NOC_SNOC },
};
static struct qcom_icc_node xm_pcie3_0 = {
.name = "xm_pcie3_0",
.id = SC7280_MASTER_PCIE_0,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC },
};
static struct qcom_icc_node xm_pcie3_1 = {
.name = "xm_pcie3_1",
.id = SC7280_MASTER_PCIE_1,
.channels = 1,
.buswidth = 8,
.links = { SC7280_SLAVE_ANOC_PCIE_GEM_NOC },
};
static struct qcom_icc_node xm_qdss_etr = {
.name = "xm_qdss_etr",
.id = SC7280_MASTER_QDSS_ETR,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_SLAVE_A2NOC_SNOC },
};
static struct qcom_icc_node qup0_core_master = {
.name = "qup0_core_master",
.id = SC7280_MASTER_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_SLAVE_QUP_CORE_0 },
};
static struct qcom_icc_node qup1_core_master = {
.name = "qup1_core_master",
.id = SC7280_MASTER_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_SLAVE_QUP_CORE_1 },
};
static struct qcom_icc_node qnm_cnoc3_cnoc2 = {
.name = "qnm_cnoc3_cnoc2",
.id = SC7280_MASTER_CNOC3_CNOC2,
.channels = 1,
.buswidth = 8,
.num_links = 44,
.links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH,
SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL,
SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG,
SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG,
SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG,
SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG,
SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG,
SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG,
SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS,
SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG,
SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM,
SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG,
SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG,
SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0,
SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1,
SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4,
SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR,
SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG,
SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0,
SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG,
SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG,
SC7280_SLAVE_CNOC_MNOC_CFG, SC7280_SLAVE_SNOC_CFG },
};
static struct qcom_icc_node xm_qdss_dap = {
.name = "xm_qdss_dap",
.id = SC7280_MASTER_QDSS_DAP,
.channels = 1,
.buswidth = 8,
.num_links = 45,
.links = { SC7280_SLAVE_AHB2PHY_SOUTH, SC7280_SLAVE_AHB2PHY_NORTH,
SC7280_SLAVE_CAMERA_CFG, SC7280_SLAVE_CLK_CTL,
SC7280_SLAVE_CDSP_CFG, SC7280_SLAVE_RBCPR_CX_CFG,
SC7280_SLAVE_RBCPR_MX_CFG, SC7280_SLAVE_CRYPTO_0_CFG,
SC7280_SLAVE_CX_RDPM, SC7280_SLAVE_DCC_CFG,
SC7280_SLAVE_DISPLAY_CFG, SC7280_SLAVE_GFX3D_CFG,
SC7280_SLAVE_HWKM, SC7280_SLAVE_IMEM_CFG,
SC7280_SLAVE_IPA_CFG, SC7280_SLAVE_IPC_ROUTER_CFG,
SC7280_SLAVE_LPASS, SC7280_SLAVE_CNOC_MSS,
SC7280_SLAVE_MX_RDPM, SC7280_SLAVE_PCIE_0_CFG,
SC7280_SLAVE_PCIE_1_CFG, SC7280_SLAVE_PDM,
SC7280_SLAVE_PIMEM_CFG, SC7280_SLAVE_PKA_WRAPPER_CFG,
SC7280_SLAVE_PMU_WRAPPER_CFG, SC7280_SLAVE_QDSS_CFG,
SC7280_SLAVE_QSPI_0, SC7280_SLAVE_QUP_0,
SC7280_SLAVE_QUP_1, SC7280_SLAVE_SDCC_1,
SC7280_SLAVE_SDCC_2, SC7280_SLAVE_SDCC_4,
SC7280_SLAVE_SECURITY, SC7280_SLAVE_TCSR,
SC7280_SLAVE_TLMM, SC7280_SLAVE_UFS_MEM_CFG,
SC7280_SLAVE_USB2, SC7280_SLAVE_USB3_0,
SC7280_SLAVE_VENUS_CFG, SC7280_SLAVE_VSENSE_CTRL_CFG,
SC7280_SLAVE_A1NOC_CFG, SC7280_SLAVE_A2NOC_CFG,
SC7280_SLAVE_CNOC2_CNOC3, SC7280_SLAVE_CNOC_MNOC_CFG,
SC7280_SLAVE_SNOC_CFG },
};
static struct qcom_icc_node qnm_cnoc2_cnoc3 = {
.name = "qnm_cnoc2_cnoc3",
.id = SC7280_MASTER_CNOC2_CNOC3,
.channels = 1,
.buswidth = 8,
.num_links = 9,
.links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS,
SC7280_SLAVE_CNOC_A2NOC, SC7280_SLAVE_DDRSS_CFG,
SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM,
SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM,
SC7280_SLAVE_TCU },
};
static struct qcom_icc_node qnm_gemnoc_cnoc = {
.name = "qnm_gemnoc_cnoc",
.id = SC7280_MASTER_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
.num_links = 9,
.links = { SC7280_SLAVE_AOSS, SC7280_SLAVE_APPSS,
SC7280_SLAVE_CNOC3_CNOC2, SC7280_SLAVE_DDRSS_CFG,
SC7280_SLAVE_BOOT_IMEM, SC7280_SLAVE_IMEM,
SC7280_SLAVE_PIMEM, SC7280_SLAVE_QDSS_STM,
SC7280_SLAVE_TCU },
};
static struct qcom_icc_node qnm_gemnoc_pcie = {
.name = "qnm_gemnoc_pcie",
.id = SC7280_MASTER_GEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 2,
.links = { SC7280_SLAVE_PCIE_0, SC7280_SLAVE_PCIE_1 },
};
static struct qcom_icc_node qnm_cnoc_dc_noc = {
.name = "qnm_cnoc_dc_noc",
.id = SC7280_MASTER_CNOC_DC_NOC,
.channels = 1,
.buswidth = 4,
.num_links = 2,
.links = { SC7280_SLAVE_LLCC_CFG, SC7280_SLAVE_GEM_NOC_CFG },
};
static struct qcom_icc_node alm_gpu_tcu = {
.name = "alm_gpu_tcu",
.id = SC7280_MASTER_GPU_TCU,
.channels = 1,
.buswidth = 8,
.num_links = 2,
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
};
static struct qcom_icc_node alm_sys_tcu = {
.name = "alm_sys_tcu",
.id = SC7280_MASTER_SYS_TCU,
.channels = 1,
.buswidth = 8,
.num_links = 2,
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
};
static struct qcom_icc_node chm_apps = {
.name = "chm_apps",
.id = SC7280_MASTER_APPSS_PROC,
.channels = 1,
.buswidth = 32,
.num_links = 3,
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC,
SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
};
static struct qcom_icc_node qnm_cmpnoc = {
.name = "qnm_cmpnoc",
.id = SC7280_MASTER_COMPUTE_NOC,
.channels = 2,
.buswidth = 32,
.num_links = 2,
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
};
static struct qcom_icc_node qnm_gemnoc_cfg = {
.name = "qnm_gemnoc_cfg",
.id = SC7280_MASTER_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 5,
.links = { SC7280_SLAVE_MSS_PROC_MS_MPU_CFG, SC7280_SLAVE_MCDMA_MS_MPU_CFG,
SC7280_SLAVE_SERVICE_GEM_NOC_1, SC7280_SLAVE_SERVICE_GEM_NOC_2,
SC7280_SLAVE_SERVICE_GEM_NOC },
};
static struct qcom_icc_node qnm_gpu = {
.name = "qnm_gpu",
.id = SC7280_MASTER_GFX3D,
.channels = 2,
.buswidth = 32,
.num_links = 2,
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
};
static struct qcom_icc_node qnm_mnoc_hf = {
.name = "qnm_mnoc_hf",
.id = SC7280_MASTER_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
.num_links = 1,
.links = { SC7280_SLAVE_LLCC },
};
static struct qcom_icc_node qnm_mnoc_sf = {
.name = "qnm_mnoc_sf",
.id = SC7280_MASTER_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
.num_links = 2,
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
};
static struct qcom_icc_node qnm_pcie = {
.name = "qnm_pcie",
.id = SC7280_MASTER_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
.num_links = 2,
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC },
};
static struct qcom_icc_node qnm_snoc_gc = {
.name = "qnm_snoc_gc",
.id = SC7280_MASTER_SNOC_GC_MEM_NOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_SLAVE_LLCC },
};
static struct qcom_icc_node qnm_snoc_sf = {
.name = "qnm_snoc_sf",
.id = SC7280_MASTER_SNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 16,
.num_links = 3,
.links = { SC7280_SLAVE_GEM_NOC_CNOC, SC7280_SLAVE_LLCC,
SC7280_SLAVE_MEM_NOC_PCIE_SNOC },
};
static struct qcom_icc_node qhm_config_noc = {
.name = "qhm_config_noc",
.id = SC7280_MASTER_CNOC_LPASS_AG_NOC,
.channels = 1,
.buswidth = 4,
.num_links = 6,
.links = { SC7280_SLAVE_LPASS_CORE_CFG, SC7280_SLAVE_LPASS_LPI_CFG,
SC7280_SLAVE_LPASS_MPU_CFG, SC7280_SLAVE_LPASS_TOP_CFG,
SC7280_SLAVE_SERVICES_LPASS_AML_NOC, SC7280_SLAVE_SERVICE_LPASS_AG_NOC },
};
static struct qcom_icc_node llcc_mc = {
.name = "llcc_mc",
.id = SC7280_MASTER_LLCC,
.channels = 2,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_SLAVE_EBI1 },
};
static struct qcom_icc_node qnm_mnoc_cfg = {
.name = "qnm_mnoc_cfg",
.id = SC7280_MASTER_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_SLAVE_SERVICE_MNOC },
};
static struct qcom_icc_node qnm_video0 = {
.name = "qnm_video0",
.id = SC7280_MASTER_VIDEO_P0,
.channels = 1,
.buswidth = 32,
.num_links = 1,
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
};
static struct qcom_icc_node qnm_video_cpu = {
.name = "qnm_video_cpu",
.id = SC7280_MASTER_VIDEO_PROC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
};
static struct qcom_icc_node qxm_camnoc_hf = {
.name = "qxm_camnoc_hf",
.id = SC7280_MASTER_CAMNOC_HF,
.channels = 2,
.buswidth = 32,
.num_links = 1,
.links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
};
static struct qcom_icc_node qxm_camnoc_icp = {
.name = "qxm_camnoc_icp",
.id = SC7280_MASTER_CAMNOC_ICP,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
};
static struct qcom_icc_node qxm_camnoc_sf = {
.name = "qxm_camnoc_sf",
.id = SC7280_MASTER_CAMNOC_SF,
.channels = 1,
.buswidth = 32,
.num_links = 1,
.links = { SC7280_SLAVE_MNOC_SF_MEM_NOC },
};
static struct qcom_icc_node qxm_mdp0 = {
.name = "qxm_mdp0",
.id = SC7280_MASTER_MDP0,
.channels = 1,
.buswidth = 32,
.num_links = 1,
.links = { SC7280_SLAVE_MNOC_HF_MEM_NOC },
};
static struct qcom_icc_node qhm_nsp_noc_config = {
.name = "qhm_nsp_noc_config",
.id = SC7280_MASTER_CDSP_NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_SLAVE_SERVICE_NSP_NOC },
};
static struct qcom_icc_node qxm_nsp = {
.name = "qxm_nsp",
.id = SC7280_MASTER_CDSP_PROC,
.channels = 2,
.buswidth = 32,
.num_links = 1,
.links = { SC7280_SLAVE_CDSP_MEM_NOC },
};
static struct qcom_icc_node qnm_aggre1_noc = {
.name = "qnm_aggre1_noc",
.id = SC7280_MASTER_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SC7280_SLAVE_SNOC_GEM_NOC_SF },
};
static struct qcom_icc_node qnm_aggre2_noc = {
.name = "qnm_aggre2_noc",
.id = SC7280_MASTER_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SC7280_SLAVE_SNOC_GEM_NOC_SF },
};
static struct qcom_icc_node qnm_snoc_cfg = {
.name = "qnm_snoc_cfg",
.id = SC7280_MASTER_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_SLAVE_SERVICE_SNOC },
};
static struct qcom_icc_node qxm_pimem = {
.name = "qxm_pimem",
.id = SC7280_MASTER_PIMEM,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
};
static struct qcom_icc_node xm_gic = {
.name = "xm_gic",
.id = SC7280_MASTER_GIC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_SLAVE_SNOC_GEM_NOC_GC },
};
static struct qcom_icc_node qns_a1noc_snoc = {
.name = "qns_a1noc_snoc",
.id = SC7280_SLAVE_A1NOC_SNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SC7280_MASTER_A1NOC_SNOC },
};
static struct qcom_icc_node srvc_aggre1_noc = {
.name = "srvc_aggre1_noc",
.id = SC7280_SLAVE_SERVICE_A1NOC,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qns_a2noc_snoc = {
.name = "qns_a2noc_snoc",
.id = SC7280_SLAVE_A2NOC_SNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SC7280_MASTER_A2NOC_SNOC },
};
static struct qcom_icc_node qns_pcie_mem_noc = {
.name = "qns_pcie_mem_noc",
.id = SC7280_SLAVE_ANOC_PCIE_GEM_NOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SC7280_MASTER_ANOC_PCIE_GEM_NOC },
};
static struct qcom_icc_node srvc_aggre2_noc = {
.name = "srvc_aggre2_noc",
.id = SC7280_SLAVE_SERVICE_A2NOC,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qup0_core_slave = {
.name = "qup0_core_slave",
.id = SC7280_SLAVE_QUP_CORE_0,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qup1_core_slave = {
.name = "qup1_core_slave",
.id = SC7280_SLAVE_QUP_CORE_1,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_ahb2phy0 = {
.name = "qhs_ahb2phy0",
.id = SC7280_SLAVE_AHB2PHY_SOUTH,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_ahb2phy1 = {
.name = "qhs_ahb2phy1",
.id = SC7280_SLAVE_AHB2PHY_NORTH,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_camera_cfg = {
.name = "qhs_camera_cfg",
.id = SC7280_SLAVE_CAMERA_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_clk_ctl = {
.name = "qhs_clk_ctl",
.id = SC7280_SLAVE_CLK_CTL,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_compute_cfg = {
.name = "qhs_compute_cfg",
.id = SC7280_SLAVE_CDSP_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_MASTER_CDSP_NOC_CFG },
};
static struct qcom_icc_node qhs_cpr_cx = {
.name = "qhs_cpr_cx",
.id = SC7280_SLAVE_RBCPR_CX_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_cpr_mx = {
.name = "qhs_cpr_mx",
.id = SC7280_SLAVE_RBCPR_MX_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_crypto0_cfg = {
.name = "qhs_crypto0_cfg",
.id = SC7280_SLAVE_CRYPTO_0_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_cx_rdpm = {
.name = "qhs_cx_rdpm",
.id = SC7280_SLAVE_CX_RDPM,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_dcc_cfg = {
.name = "qhs_dcc_cfg",
.id = SC7280_SLAVE_DCC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_display_cfg = {
.name = "qhs_display_cfg",
.id = SC7280_SLAVE_DISPLAY_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_gpuss_cfg = {
.name = "qhs_gpuss_cfg",
.id = SC7280_SLAVE_GFX3D_CFG,
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node qhs_hwkm = {
.name = "qhs_hwkm",
.id = SC7280_SLAVE_HWKM,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_imem_cfg = {
.name = "qhs_imem_cfg",
.id = SC7280_SLAVE_IMEM_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_ipa = {
.name = "qhs_ipa",
.id = SC7280_SLAVE_IPA_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_ipc_router = {
.name = "qhs_ipc_router",
.id = SC7280_SLAVE_IPC_ROUTER_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_lpass_cfg = {
.name = "qhs_lpass_cfg",
.id = SC7280_SLAVE_LPASS,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_MASTER_CNOC_LPASS_AG_NOC },
};
static struct qcom_icc_node qhs_mss_cfg = {
.name = "qhs_mss_cfg",
.id = SC7280_SLAVE_CNOC_MSS,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_mx_rdpm = {
.name = "qhs_mx_rdpm",
.id = SC7280_SLAVE_MX_RDPM,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pcie0_cfg = {
.name = "qhs_pcie0_cfg",
.id = SC7280_SLAVE_PCIE_0_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pcie1_cfg = {
.name = "qhs_pcie1_cfg",
.id = SC7280_SLAVE_PCIE_1_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pdm = {
.name = "qhs_pdm",
.id = SC7280_SLAVE_PDM,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pimem_cfg = {
.name = "qhs_pimem_cfg",
.id = SC7280_SLAVE_PIMEM_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pka_wrapper_cfg = {
.name = "qhs_pka_wrapper_cfg",
.id = SC7280_SLAVE_PKA_WRAPPER_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_pmu_wrapper_cfg = {
.name = "qhs_pmu_wrapper_cfg",
.id = SC7280_SLAVE_PMU_WRAPPER_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_qdss_cfg = {
.name = "qhs_qdss_cfg",
.id = SC7280_SLAVE_QDSS_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_qspi = {
.name = "qhs_qspi",
.id = SC7280_SLAVE_QSPI_0,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_qup0 = {
.name = "qhs_qup0",
.id = SC7280_SLAVE_QUP_0,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_qup1 = {
.name = "qhs_qup1",
.id = SC7280_SLAVE_QUP_1,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_sdc1 = {
.name = "qhs_sdc1",
.id = SC7280_SLAVE_SDCC_1,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_sdc2 = {
.name = "qhs_sdc2",
.id = SC7280_SLAVE_SDCC_2,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_sdc4 = {
.name = "qhs_sdc4",
.id = SC7280_SLAVE_SDCC_4,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_security = {
.name = "qhs_security",
.id = SC7280_SLAVE_SECURITY,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_tcsr = {
.name = "qhs_tcsr",
.id = SC7280_SLAVE_TCSR,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_tlmm = {
.name = "qhs_tlmm",
.id = SC7280_SLAVE_TLMM,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_ufs_mem_cfg = {
.name = "qhs_ufs_mem_cfg",
.id = SC7280_SLAVE_UFS_MEM_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_usb2 = {
.name = "qhs_usb2",
.id = SC7280_SLAVE_USB2,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_usb3_0 = {
.name = "qhs_usb3_0",
.id = SC7280_SLAVE_USB3_0,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_venus_cfg = {
.name = "qhs_venus_cfg",
.id = SC7280_SLAVE_VENUS_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
.name = "qhs_vsense_ctrl_cfg",
.id = SC7280_SLAVE_VSENSE_CTRL_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qns_a1_noc_cfg = {
.name = "qns_a1_noc_cfg",
.id = SC7280_SLAVE_A1NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_MASTER_A1NOC_CFG },
};
static struct qcom_icc_node qns_a2_noc_cfg = {
.name = "qns_a2_noc_cfg",
.id = SC7280_SLAVE_A2NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_MASTER_A2NOC_CFG },
};
static struct qcom_icc_node qns_cnoc2_cnoc3 = {
.name = "qns_cnoc2_cnoc3",
.id = SC7280_SLAVE_CNOC2_CNOC3,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_MASTER_CNOC2_CNOC3 },
};
static struct qcom_icc_node qns_mnoc_cfg = {
.name = "qns_mnoc_cfg",
.id = SC7280_SLAVE_CNOC_MNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_MASTER_CNOC_MNOC_CFG },
};
static struct qcom_icc_node qns_snoc_cfg = {
.name = "qns_snoc_cfg",
.id = SC7280_SLAVE_SNOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_MASTER_SNOC_CFG },
};
static struct qcom_icc_node qhs_aoss = {
.name = "qhs_aoss",
.id = SC7280_SLAVE_AOSS,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_apss = {
.name = "qhs_apss",
.id = SC7280_SLAVE_APPSS,
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node qns_cnoc3_cnoc2 = {
.name = "qns_cnoc3_cnoc2",
.id = SC7280_SLAVE_CNOC3_CNOC2,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_MASTER_CNOC3_CNOC2 },
};
static struct qcom_icc_node qns_cnoc_a2noc = {
.name = "qns_cnoc_a2noc",
.id = SC7280_SLAVE_CNOC_A2NOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_MASTER_CNOC_A2NOC },
};
static struct qcom_icc_node qns_ddrss_cfg = {
.name = "qns_ddrss_cfg",
.id = SC7280_SLAVE_DDRSS_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_MASTER_CNOC_DC_NOC },
};
static struct qcom_icc_node qxs_boot_imem = {
.name = "qxs_boot_imem",
.id = SC7280_SLAVE_BOOT_IMEM,
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node qxs_imem = {
.name = "qxs_imem",
.id = SC7280_SLAVE_IMEM,
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node qxs_pimem = {
.name = "qxs_pimem",
.id = SC7280_SLAVE_PIMEM,
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node xs_pcie_0 = {
.name = "xs_pcie_0",
.id = SC7280_SLAVE_PCIE_0,
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node xs_pcie_1 = {
.name = "xs_pcie_1",
.id = SC7280_SLAVE_PCIE_1,
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node xs_qdss_stm = {
.name = "xs_qdss_stm",
.id = SC7280_SLAVE_QDSS_STM,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node xs_sys_tcu_cfg = {
.name = "xs_sys_tcu_cfg",
.id = SC7280_SLAVE_TCU,
.channels = 1,
.buswidth = 8,
.num_links = 0,
};
static struct qcom_icc_node qhs_llcc = {
.name = "qhs_llcc",
.id = SC7280_SLAVE_LLCC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qns_gemnoc = {
.name = "qns_gemnoc",
.id = SC7280_SLAVE_GEM_NOC_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 1,
.links = { SC7280_MASTER_GEM_NOC_CFG },
};
static struct qcom_icc_node qhs_mdsp_ms_mpu_cfg = {
.name = "qhs_mdsp_ms_mpu_cfg",
.id = SC7280_SLAVE_MSS_PROC_MS_MPU_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_modem_ms_mpu_cfg = {
.name = "qhs_modem_ms_mpu_cfg",
.id = SC7280_SLAVE_MCDMA_MS_MPU_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qns_gem_noc_cnoc = {
.name = "qns_gem_noc_cnoc",
.id = SC7280_SLAVE_GEM_NOC_CNOC,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SC7280_MASTER_GEM_NOC_CNOC },
};
static struct qcom_icc_node qns_llcc = {
.name = "qns_llcc",
.id = SC7280_SLAVE_LLCC,
.channels = 2,
.buswidth = 16,
.num_links = 1,
.links = { SC7280_MASTER_LLCC },
};
static struct qcom_icc_node qns_pcie = {
.name = "qns_pcie",
.id = SC7280_SLAVE_MEM_NOC_PCIE_SNOC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_MASTER_GEM_NOC_PCIE_SNOC },
};
static struct qcom_icc_node srvc_even_gemnoc = {
.name = "srvc_even_gemnoc",
.id = SC7280_SLAVE_SERVICE_GEM_NOC_1,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node srvc_odd_gemnoc = {
.name = "srvc_odd_gemnoc",
.id = SC7280_SLAVE_SERVICE_GEM_NOC_2,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node srvc_sys_gemnoc = {
.name = "srvc_sys_gemnoc",
.id = SC7280_SLAVE_SERVICE_GEM_NOC,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_lpass_core = {
.name = "qhs_lpass_core",
.id = SC7280_SLAVE_LPASS_CORE_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_lpass_lpi = {
.name = "qhs_lpass_lpi",
.id = SC7280_SLAVE_LPASS_LPI_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_lpass_mpu = {
.name = "qhs_lpass_mpu",
.id = SC7280_SLAVE_LPASS_MPU_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qhs_lpass_top = {
.name = "qhs_lpass_top",
.id = SC7280_SLAVE_LPASS_TOP_CFG,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node srvc_niu_aml_noc = {
.name = "srvc_niu_aml_noc",
.id = SC7280_SLAVE_SERVICES_LPASS_AML_NOC,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node srvc_niu_lpass_agnoc = {
.name = "srvc_niu_lpass_agnoc",
.id = SC7280_SLAVE_SERVICE_LPASS_AG_NOC,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node ebi = {
.name = "ebi",
.id = SC7280_SLAVE_EBI1,
.channels = 2,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qns_mem_noc_hf = {
.name = "qns_mem_noc_hf",
.id = SC7280_SLAVE_MNOC_HF_MEM_NOC,
.channels = 2,
.buswidth = 32,
.num_links = 1,
.links = { SC7280_MASTER_MNOC_HF_MEM_NOC },
};
static struct qcom_icc_node qns_mem_noc_sf = {
.name = "qns_mem_noc_sf",
.id = SC7280_SLAVE_MNOC_SF_MEM_NOC,
.channels = 1,
.buswidth = 32,
.num_links = 1,
.links = { SC7280_MASTER_MNOC_SF_MEM_NOC },
};
static struct qcom_icc_node srvc_mnoc = {
.name = "srvc_mnoc",
.id = SC7280_SLAVE_SERVICE_MNOC,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qns_nsp_gemnoc = {
.name = "qns_nsp_gemnoc",
.id = SC7280_SLAVE_CDSP_MEM_NOC,
.channels = 2,
.buswidth = 32,
.num_links = 1,
.links = { SC7280_MASTER_COMPUTE_NOC },
};
static struct qcom_icc_node service_nsp_noc = {
.name = "service_nsp_noc",
.id = SC7280_SLAVE_SERVICE_NSP_NOC,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_node qns_gemnoc_gc = {
.name = "qns_gemnoc_gc",
.id = SC7280_SLAVE_SNOC_GEM_NOC_GC,
.channels = 1,
.buswidth = 8,
.num_links = 1,
.links = { SC7280_MASTER_SNOC_GC_MEM_NOC },
};
static struct qcom_icc_node qns_gemnoc_sf = {
.name = "qns_gemnoc_sf",
.id = SC7280_SLAVE_SNOC_GEM_NOC_SF,
.channels = 1,
.buswidth = 16,
.num_links = 1,
.links = { SC7280_MASTER_SNOC_SF_MEM_NOC },
};
static struct qcom_icc_node srvc_snoc = {
.name = "srvc_snoc",
.id = SC7280_SLAVE_SERVICE_SNOC,
.channels = 1,
.buswidth = 4,
.num_links = 0,
};
static struct qcom_icc_bcm bcm_acv = {
.name = "ACV",
.num_nodes = 1,
.nodes = { &ebi },
};
static struct qcom_icc_bcm bcm_ce0 = {
.name = "CE0",
.num_nodes = 1,
.nodes = { &qxm_crypto },
};
static struct qcom_icc_bcm bcm_cn0 = {
.name = "CN0",
.keepalive = true,
.num_nodes = 2,
.nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
};
static struct qcom_icc_bcm bcm_cn1 = {
.name = "CN1",
.num_nodes = 47,
.nodes = { &qnm_cnoc3_cnoc2, &xm_qdss_dap,
&qhs_ahb2phy0, &qhs_ahb2phy1,
&qhs_camera_cfg, &qhs_clk_ctl,
&qhs_compute_cfg, &qhs_cpr_cx,
&qhs_cpr_mx, &qhs_crypto0_cfg,
&qhs_cx_rdpm, &qhs_dcc_cfg,
&qhs_display_cfg, &qhs_gpuss_cfg,
&qhs_hwkm, &qhs_imem_cfg,
&qhs_ipa, &qhs_ipc_router,
&qhs_mss_cfg, &qhs_mx_rdpm,
&qhs_pcie0_cfg, &qhs_pcie1_cfg,
&qhs_pimem_cfg, &qhs_pka_wrapper_cfg,
&qhs_pmu_wrapper_cfg, &qhs_qdss_cfg,
&qhs_qup0, &qhs_qup1,
&qhs_security, &qhs_tcsr,
&qhs_tlmm, &qhs_ufs_mem_cfg, &qhs_usb2,
&qhs_usb3_0, &qhs_venus_cfg,
&qhs_vsense_ctrl_cfg, &qns_a1_noc_cfg,
&qns_a2_noc_cfg, &qns_cnoc2_cnoc3,
&qns_mnoc_cfg, &qns_snoc_cfg,
&qnm_cnoc2_cnoc3, &qhs_aoss,
&qhs_apss, &qns_cnoc3_cnoc2,
&qns_cnoc_a2noc, &qns_ddrss_cfg },
};
static struct qcom_icc_bcm bcm_cn2 = {
.name = "CN2",
.num_nodes = 6,
.nodes = { &qhs_lpass_cfg, &qhs_pdm,
&qhs_qspi, &qhs_sdc1,
&qhs_sdc2, &qhs_sdc4 },
};
static struct qcom_icc_bcm bcm_co0 = {
.name = "CO0",
.num_nodes = 1,
.nodes = { &qns_nsp_gemnoc },
};
static struct qcom_icc_bcm bcm_co3 = {
.name = "CO3",
.num_nodes = 1,
.nodes = { &qxm_nsp },
};
static struct qcom_icc_bcm bcm_mc0 = {
.name = "MC0",
.keepalive = true,
.num_nodes = 1,
.nodes = { &ebi },
};
static struct qcom_icc_bcm bcm_mm0 = {
.name = "MM0",
.keepalive = true,
.num_nodes = 1,
.nodes = { &qns_mem_noc_hf },
};
static struct qcom_icc_bcm bcm_mm1 = {
.name = "MM1",
.num_nodes = 2,
.nodes = { &qxm_camnoc_hf, &qxm_mdp0 },
};
static struct qcom_icc_bcm bcm_mm4 = {
.name = "MM4",
.num_nodes = 1,
.nodes = { &qns_mem_noc_sf },
};
static struct qcom_icc_bcm bcm_mm5 = {
.name = "MM5",
.num_nodes = 3,
.nodes = { &qnm_video0, &qxm_camnoc_icp,
&qxm_camnoc_sf },
};
static struct qcom_icc_bcm bcm_qup0 = {
.name = "QUP0",
.vote_scale = 1,
.num_nodes = 1,
.nodes = { &qup0_core_slave },
};
static struct qcom_icc_bcm bcm_qup1 = {
.name = "QUP1",
.vote_scale = 1,
.num_nodes = 1,
.nodes = { &qup1_core_slave },
};
static struct qcom_icc_bcm bcm_sh0 = {
.name = "SH0",
.keepalive = true,
.num_nodes = 1,
.nodes = { &qns_llcc },
};
static struct qcom_icc_bcm bcm_sh2 = {
.name = "SH2",
.num_nodes = 2,
.nodes = { &alm_gpu_tcu, &alm_sys_tcu },
};
static struct qcom_icc_bcm bcm_sh3 = {
.name = "SH3",
.num_nodes = 1,
.nodes = { &qnm_cmpnoc },
};
static struct qcom_icc_bcm bcm_sh4 = {
.name = "SH4",
.num_nodes = 1,
.nodes = { &chm_apps },
};
static struct qcom_icc_bcm bcm_sn0 = {
.name = "SN0",
.keepalive = true,
.num_nodes = 1,
.nodes = { &qns_gemnoc_sf },
};
static struct qcom_icc_bcm bcm_sn2 = {
.name = "SN2",
.num_nodes = 1,
.nodes = { &qns_gemnoc_gc },
};
static struct qcom_icc_bcm bcm_sn3 = {
.name = "SN3",
.num_nodes = 1,
.nodes = { &qxs_pimem },
};
static struct qcom_icc_bcm bcm_sn4 = {
.name = "SN4",
.num_nodes = 1,
.nodes = { &xs_qdss_stm },
};
static struct qcom_icc_bcm bcm_sn5 = {
.name = "SN5",
.num_nodes = 1,
.nodes = { &xm_pcie3_0 },
};
static struct qcom_icc_bcm bcm_sn6 = {
.name = "SN6",
.num_nodes = 1,
.nodes = { &xm_pcie3_1 },
};
static struct qcom_icc_bcm bcm_sn7 = {
.name = "SN7",
.num_nodes = 1,
.nodes = { &qnm_aggre1_noc },
};
static struct qcom_icc_bcm bcm_sn8 = {
.name = "SN8",
.num_nodes = 1,
.nodes = { &qnm_aggre2_noc },
};
static struct qcom_icc_bcm bcm_sn14 = {
.name = "SN14",
.num_nodes = 1,
.nodes = { &qns_pcie_mem_noc },
};
static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
&bcm_sn5,
&bcm_sn6,
&bcm_sn14,
};
static struct qcom_icc_node *aggre1_noc_nodes[] = {
[MASTER_QSPI_0] = &qhm_qspi,
[MASTER_QUP_0] = &qhm_qup0,
[MASTER_QUP_1] = &qhm_qup1,
[MASTER_A1NOC_CFG] = &qnm_a1noc_cfg,
[MASTER_PCIE_0] = &xm_pcie3_0,
[MASTER_PCIE_1] = &xm_pcie3_1,
[MASTER_SDCC_1] = &xm_sdc1,
[MASTER_SDCC_2] = &xm_sdc2,
[MASTER_SDCC_4] = &xm_sdc4,
[MASTER_UFS_MEM] = &xm_ufs_mem,
[MASTER_USB2] = &xm_usb2,
[MASTER_USB3_0] = &xm_usb3_0,
[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
[SLAVE_SERVICE_A1NOC] = &srvc_aggre1_noc,
};
static struct qcom_icc_desc sc7280_aggre1_noc = {
.nodes = aggre1_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
.bcms = aggre1_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
};
static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
&bcm_ce0,
};
static struct qcom_icc_node *aggre2_noc_nodes[] = {
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
[MASTER_A2NOC_CFG] = &qnm_a2noc_cfg,
[MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath,
[MASTER_CRYPTO] = &qxm_crypto,
[MASTER_IPA] = &qxm_ipa,
[MASTER_QDSS_ETR] = &xm_qdss_etr,
[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,
};
static struct qcom_icc_desc sc7280_aggre2_noc = {
.nodes = aggre2_noc_nodes,
.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
.bcms = aggre2_noc_bcms,
.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
};
static struct qcom_icc_bcm *clk_virt_bcms[] = {
&bcm_qup0,
&bcm_qup1,
};
static struct qcom_icc_node *clk_virt_nodes[] = {
[MASTER_QUP_CORE_0] = &qup0_core_master,
[MASTER_QUP_CORE_1] = &qup1_core_master,
[SLAVE_QUP_CORE_0] = &qup0_core_slave,
[SLAVE_QUP_CORE_1] = &qup1_core_slave,
};
static struct qcom_icc_desc sc7280_clk_virt = {
.nodes = clk_virt_nodes,
.num_nodes = ARRAY_SIZE(clk_virt_nodes),
.bcms = clk_virt_bcms,
.num_bcms = ARRAY_SIZE(clk_virt_bcms),
};
static struct qcom_icc_bcm *cnoc2_bcms[] = {
&bcm_cn1,
&bcm_cn2,
};
static struct qcom_icc_node *cnoc2_nodes[] = {
[MASTER_CNOC3_CNOC2] = &qnm_cnoc3_cnoc2,
[MASTER_QDSS_DAP] = &xm_qdss_dap,
[SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0,
[SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1,
[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
[SLAVE_CLK_CTL] = &qhs_clk_ctl,
[SLAVE_CDSP_CFG] = &qhs_compute_cfg,
[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
[SLAVE_CX_RDPM] = &qhs_cx_rdpm,
[SLAVE_DCC_CFG] = &qhs_dcc_cfg,
[SLAVE_DISPLAY_CFG] = &qhs_display_cfg,
[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
[SLAVE_HWKM] = &qhs_hwkm,
[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
[SLAVE_IPA_CFG] = &qhs_ipa,
[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
[SLAVE_LPASS] = &qhs_lpass_cfg,
[SLAVE_CNOC_MSS] = &qhs_mss_cfg,
[SLAVE_MX_RDPM] = &qhs_mx_rdpm,
[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
[SLAVE_PDM] = &qhs_pdm,
[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
[SLAVE_PKA_WRAPPER_CFG] = &qhs_pka_wrapper_cfg,
[SLAVE_PMU_WRAPPER_CFG] = &qhs_pmu_wrapper_cfg,
[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
[SLAVE_QSPI_0] = &qhs_qspi,
[SLAVE_QUP_0] = &qhs_qup0,
[SLAVE_QUP_1] = &qhs_qup1,
[SLAVE_SDCC_1] = &qhs_sdc1,
[SLAVE_SDCC_2] = &qhs_sdc2,
[SLAVE_SDCC_4] = &qhs_sdc4,
[SLAVE_SECURITY] = &qhs_security,
[SLAVE_TCSR] = &qhs_tcsr,
[SLAVE_TLMM] = &qhs_tlmm,
[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
[SLAVE_USB2] = &qhs_usb2,
[SLAVE_USB3_0] = &qhs_usb3_0,
[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
[SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
[SLAVE_A1NOC_CFG] = &qns_a1_noc_cfg,
[SLAVE_A2NOC_CFG] = &qns_a2_noc_cfg,
[SLAVE_CNOC2_CNOC3] = &qns_cnoc2_cnoc3,
[SLAVE_CNOC_MNOC_CFG] = &qns_mnoc_cfg,
[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
};
static struct qcom_icc_desc sc7280_cnoc2 = {
.nodes = cnoc2_nodes,
.num_nodes = ARRAY_SIZE(cnoc2_nodes),
.bcms = cnoc2_bcms,
.num_bcms = ARRAY_SIZE(cnoc2_bcms),
};
static struct qcom_icc_bcm *cnoc3_bcms[] = {
&bcm_cn0,
&bcm_cn1,
&bcm_sn3,
&bcm_sn4,
};
static struct qcom_icc_node *cnoc3_nodes[] = {
[MASTER_CNOC2_CNOC3] = &qnm_cnoc2_cnoc3,
[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
[SLAVE_AOSS] = &qhs_aoss,
[SLAVE_APPSS] = &qhs_apss,
[SLAVE_CNOC3_CNOC2] = &qns_cnoc3_cnoc2,
[SLAVE_CNOC_A2NOC] = &qns_cnoc_a2noc,
[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
[SLAVE_BOOT_IMEM] = &qxs_boot_imem,
[SLAVE_IMEM] = &qxs_imem,
[SLAVE_PIMEM] = &qxs_pimem,
[SLAVE_PCIE_0] = &xs_pcie_0,
[SLAVE_PCIE_1] = &xs_pcie_1,
[SLAVE_QDSS_STM] = &xs_qdss_stm,
[SLAVE_TCU] = &xs_sys_tcu_cfg,
};
static struct qcom_icc_desc sc7280_cnoc3 = {
.nodes = cnoc3_nodes,
.num_nodes = ARRAY_SIZE(cnoc3_nodes),
.bcms = cnoc3_bcms,
.num_bcms = ARRAY_SIZE(cnoc3_bcms),
};
static struct qcom_icc_bcm *dc_noc_bcms[] = {
};
static struct qcom_icc_node *dc_noc_nodes[] = {
[MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
[SLAVE_LLCC_CFG] = &qhs_llcc,
[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
};
static struct qcom_icc_desc sc7280_dc_noc = {
.nodes = dc_noc_nodes,
.num_nodes = ARRAY_SIZE(dc_noc_nodes),
.bcms = dc_noc_bcms,
.num_bcms = ARRAY_SIZE(dc_noc_bcms),
};
static struct qcom_icc_bcm *gem_noc_bcms[] = {
&bcm_sh0,
&bcm_sh2,
&bcm_sh3,
&bcm_sh4,
};
static struct qcom_icc_node *gem_noc_nodes[] = {
[MASTER_GPU_TCU] = &alm_gpu_tcu,
[MASTER_SYS_TCU] = &alm_sys_tcu,
[MASTER_APPSS_PROC] = &chm_apps,
[MASTER_COMPUTE_NOC] = &qnm_cmpnoc,
[MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
[MASTER_GFX3D] = &qnm_gpu,
[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
[SLAVE_MSS_PROC_MS_MPU_CFG] = &qhs_mdsp_ms_mpu_cfg,
[SLAVE_MCDMA_MS_MPU_CFG] = &qhs_modem_ms_mpu_cfg,
[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
[SLAVE_LLCC] = &qns_llcc,
[SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
[SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
[SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
};
static struct qcom_icc_desc sc7280_gem_noc = {
.nodes = gem_noc_nodes,
.num_nodes = ARRAY_SIZE(gem_noc_nodes),
.bcms = gem_noc_bcms,
.num_bcms = ARRAY_SIZE(gem_noc_bcms),
};
static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {
};
static struct qcom_icc_node *lpass_ag_noc_nodes[] = {
[MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
[SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
[SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
[SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
[SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
[SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
};
static struct qcom_icc_desc sc7280_lpass_ag_noc = {
.nodes = lpass_ag_noc_nodes,
.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
.bcms = lpass_ag_noc_bcms,
.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
};
static struct qcom_icc_bcm *mc_virt_bcms[] = {
&bcm_acv,
&bcm_mc0,
};
static struct qcom_icc_node *mc_virt_nodes[] = {
[MASTER_LLCC] = &llcc_mc,
[SLAVE_EBI1] = &ebi,
};
static struct qcom_icc_desc sc7280_mc_virt = {
.nodes = mc_virt_nodes,
.num_nodes = ARRAY_SIZE(mc_virt_nodes),
.bcms = mc_virt_bcms,
.num_bcms = ARRAY_SIZE(mc_virt_bcms),
};
static struct qcom_icc_bcm *mmss_noc_bcms[] = {
&bcm_mm0,
&bcm_mm1,
&bcm_mm4,
&bcm_mm5,
};
static struct qcom_icc_node *mmss_noc_nodes[] = {
[MASTER_CNOC_MNOC_CFG] = &qnm_mnoc_cfg,
[MASTER_VIDEO_P0] = &qnm_video0,
[MASTER_VIDEO_PROC] = &qnm_video_cpu,
[MASTER_CAMNOC_HF] = &qxm_camnoc_hf,
[MASTER_CAMNOC_ICP] = &qxm_camnoc_icp,
[MASTER_CAMNOC_SF] = &qxm_camnoc_sf,
[MASTER_MDP0] = &qxm_mdp0,
[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
[SLAVE_SERVICE_MNOC] = &srvc_mnoc,
};
static struct qcom_icc_desc sc7280_mmss_noc = {
.nodes = mmss_noc_nodes,
.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
.bcms = mmss_noc_bcms,
.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
};
static struct qcom_icc_bcm *nsp_noc_bcms[] = {
&bcm_co0,
&bcm_co3,
};
static struct qcom_icc_node *nsp_noc_nodes[] = {
[MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
[MASTER_CDSP_PROC] = &qxm_nsp,
[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
};
static struct qcom_icc_desc sc7280_nsp_noc = {
.nodes = nsp_noc_nodes,
.num_nodes = ARRAY_SIZE(nsp_noc_nodes),
.bcms = nsp_noc_bcms,
.num_bcms = ARRAY_SIZE(nsp_noc_bcms),
};
static struct qcom_icc_bcm *system_noc_bcms[] = {
&bcm_sn0,
&bcm_sn2,
&bcm_sn7,
&bcm_sn8,
};
static struct qcom_icc_node *system_noc_nodes[] = {
[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
[MASTER_SNOC_CFG] = &qnm_snoc_cfg,
[MASTER_PIMEM] = &qxm_pimem,
[MASTER_GIC] = &xm_gic,
[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
[SLAVE_SERVICE_SNOC] = &srvc_snoc,
};
static struct qcom_icc_desc sc7280_system_noc = {
.nodes = system_noc_nodes,
.num_nodes = ARRAY_SIZE(system_noc_nodes),
.bcms = system_noc_bcms,
.num_bcms = ARRAY_SIZE(system_noc_bcms),
};
static int qnoc_probe(struct platform_device *pdev)
{
const struct qcom_icc_desc *desc;
struct icc_onecell_data *data;
struct icc_provider *provider;
struct qcom_icc_node **qnodes;
struct qcom_icc_provider *qp;
struct icc_node *node;
size_t num_nodes, i;
int ret;
desc = device_get_match_data(&pdev->dev);
if (!desc)
return -EINVAL;
qnodes = desc->nodes;
num_nodes = desc->num_nodes;
qp = devm_kzalloc(&pdev->dev, sizeof(*qp), GFP_KERNEL);
if (!qp)
return -ENOMEM;
data = devm_kcalloc(&pdev->dev, num_nodes, sizeof(*node), GFP_KERNEL);
if (!data)
return -ENOMEM;
provider = &qp->provider;
provider->dev = &pdev->dev;
provider->set = qcom_icc_set;
provider->pre_aggregate = qcom_icc_pre_aggregate;
provider->aggregate = qcom_icc_aggregate;
provider->xlate_extended = qcom_icc_xlate_extended;
INIT_LIST_HEAD(&provider->nodes);
provider->data = data;
qp->dev = &pdev->dev;
qp->bcms = desc->bcms;
qp->num_bcms = desc->num_bcms;
qp->voter = of_bcm_voter_get(qp->dev, NULL);
if (IS_ERR(qp->voter))
return PTR_ERR(qp->voter);
ret = icc_provider_add(provider);
if (ret) {
dev_err(&pdev->dev, "error adding interconnect provider\n");
return ret;
}
for (i = 0; i < qp->num_bcms; i++)
qcom_icc_bcm_init(qp->bcms[i], &pdev->dev);
for (i = 0; i < num_nodes; i++) {
size_t j;
if (!qnodes[i])
continue;
node = icc_node_create(qnodes[i]->id);
if (IS_ERR(node)) {
ret = PTR_ERR(node);
goto err;
}
node->name = qnodes[i]->name;
node->data = qnodes[i];
icc_node_add(node, provider);
for (j = 0; j < qnodes[i]->num_links; j++)
icc_link_create(node, qnodes[i]->links[j]);
data->nodes[i] = node;
}
data->num_nodes = num_nodes;
platform_set_drvdata(pdev, qp);
return 0;
err:
icc_nodes_remove(provider);
icc_provider_del(provider);
return ret;
}
static int qnoc_remove(struct platform_device *pdev)
{
struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
icc_nodes_remove(&qp->provider);
return icc_provider_del(&qp->provider);
}
static const struct of_device_id qnoc_of_match[] = {
{ .compatible = "qcom,sc7280-aggre1-noc",
.data = &sc7280_aggre1_noc},
{ .compatible = "qcom,sc7280-aggre2-noc",
.data = &sc7280_aggre2_noc},
{ .compatible = "qcom,sc7280-clk-virt",
.data = &sc7280_clk_virt},
{ .compatible = "qcom,sc7280-cnoc2",
.data = &sc7280_cnoc2},
{ .compatible = "qcom,sc7280-cnoc3",
.data = &sc7280_cnoc3},
{ .compatible = "qcom,sc7280-dc-noc",
.data = &sc7280_dc_noc},
{ .compatible = "qcom,sc7280-gem-noc",
.data = &sc7280_gem_noc},
{ .compatible = "qcom,sc7280-lpass-ag-noc",
.data = &sc7280_lpass_ag_noc},
{ .compatible = "qcom,sc7280-mc-virt",
.data = &sc7280_mc_virt},
{ .compatible = "qcom,sc7280-mmss-noc",
.data = &sc7280_mmss_noc},
{ .compatible = "qcom,sc7280-nsp-noc",
.data = &sc7280_nsp_noc},
{ .compatible = "qcom,sc7280-system-noc",
.data = &sc7280_system_noc},
{ }
};
MODULE_DEVICE_TABLE(of, qnoc_of_match);
static struct platform_driver qnoc_driver = {
.probe = qnoc_probe,
.remove = qnoc_remove,
.driver = {
.name = "qnoc-sc7280",
.of_match_table = qnoc_of_match,
.sync_state = icc_sync_state,
},
};
module_platform_driver(qnoc_driver);
MODULE_DESCRIPTION("SC7280 NoC driver");
MODULE_LICENSE("GPL v2");
drivers/interconnect/qcom/sc7280.h 0 → 100644
View file @ 46bdcac5
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Qualcomm #define SC7280 interconnect IDs
*
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SC7280_H
#define __DRIVERS_INTERCONNECT_QCOM_SC7280_H
#define SC7280_MASTER_GPU_TCU 0
#define SC7280_MASTER_SYS_TCU 1
#define SC7280_MASTER_APPSS_PROC 2
#define SC7280_MASTER_LLCC 3
#define SC7280_MASTER_CNOC_LPASS_AG_NOC 4
#define SC7280_MASTER_CDSP_NOC_CFG 5
#define SC7280_MASTER_QDSS_BAM 6
#define SC7280_MASTER_QSPI_0 7
#define SC7280_MASTER_QUP_0 8
#define SC7280_MASTER_QUP_1 9
#define SC7280_MASTER_A1NOC_CFG 10
#define SC7280_MASTER_A2NOC_CFG 11
#define SC7280_MASTER_A1NOC_SNOC 12
#define SC7280_MASTER_A2NOC_SNOC 13
#define SC7280_MASTER_COMPUTE_NOC 14
#define SC7280_MASTER_CNOC2_CNOC3 15
#define SC7280_MASTER_CNOC3_CNOC2 16
#define SC7280_MASTER_CNOC_A2NOC 17
#define SC7280_MASTER_CNOC_DC_NOC 18
#define SC7280_MASTER_GEM_NOC_CFG 19
#define SC7280_MASTER_GEM_NOC_CNOC 20
#define SC7280_MASTER_GEM_NOC_PCIE_SNOC 21
#define SC7280_MASTER_GFX3D 22
#define SC7280_MASTER_CNOC_MNOC_CFG 23
#define SC7280_MASTER_MNOC_HF_MEM_NOC 24
#define SC7280_MASTER_MNOC_SF_MEM_NOC 25
#define SC7280_MASTER_ANOC_PCIE_GEM_NOC 26
#define SC7280_MASTER_SNOC_CFG 27
#define SC7280_MASTER_SNOC_GC_MEM_NOC 28
#define SC7280_MASTER_SNOC_SF_MEM_NOC 29
#define SC7280_MASTER_VIDEO_P0 30
#define SC7280_MASTER_VIDEO_PROC 31
#define SC7280_MASTER_QUP_CORE_0 32
#define SC7280_MASTER_QUP_CORE_1 33
#define SC7280_MASTER_CAMNOC_HF 34
#define SC7280_MASTER_CAMNOC_ICP 35
#define SC7280_MASTER_CAMNOC_SF 36
#define SC7280_MASTER_CRYPTO 37
#define SC7280_MASTER_IPA 38
#define SC7280_MASTER_MDP0 39
#define SC7280_MASTER_CDSP_PROC 40
#define SC7280_MASTER_PIMEM 41
#define SC7280_MASTER_GIC 42
#define SC7280_MASTER_PCIE_0 43
#define SC7280_MASTER_PCIE_1 44
#define SC7280_MASTER_QDSS_DAP 45
#define SC7280_MASTER_QDSS_ETR 46
#define SC7280_MASTER_SDCC_1 47
#define SC7280_MASTER_SDCC_2 48
#define SC7280_MASTER_SDCC_4 49
#define SC7280_MASTER_UFS_MEM 50
#define SC7280_MASTER_USB2 51
#define SC7280_MASTER_USB3_0 52
#define SC7280_SLAVE_EBI1 53
#define SC7280_SLAVE_AHB2PHY_SOUTH 54
#define SC7280_SLAVE_AHB2PHY_NORTH 55
#define SC7280_SLAVE_AOSS 56
#define SC7280_SLAVE_APPSS 57
#define SC7280_SLAVE_CAMERA_CFG 58
#define SC7280_SLAVE_CLK_CTL 59
#define SC7280_SLAVE_CDSP_CFG 60
#define SC7280_SLAVE_RBCPR_CX_CFG 61
#define SC7280_SLAVE_RBCPR_MX_CFG 62
#define SC7280_SLAVE_CRYPTO_0_CFG 63
#define SC7280_SLAVE_CX_RDPM 64
#define SC7280_SLAVE_DCC_CFG 65
#define SC7280_SLAVE_DISPLAY_CFG 66
#define SC7280_SLAVE_GFX3D_CFG 67
#define SC7280_SLAVE_HWKM 68
#define SC7280_SLAVE_IMEM_CFG 69
#define SC7280_SLAVE_IPA_CFG 70
#define SC7280_SLAVE_IPC_ROUTER_CFG 71
#define SC7280_SLAVE_LLCC_CFG 72
#define SC7280_SLAVE_LPASS 73
#define SC7280_SLAVE_LPASS_CORE_CFG 74
#define SC7280_SLAVE_LPASS_LPI_CFG 75
#define SC7280_SLAVE_LPASS_MPU_CFG 76
#define SC7280_SLAVE_LPASS_TOP_CFG 77
#define SC7280_SLAVE_MSS_PROC_MS_MPU_CFG 78
#define SC7280_SLAVE_MCDMA_MS_MPU_CFG 79
#define SC7280_SLAVE_CNOC_MSS 80
#define SC7280_SLAVE_MX_RDPM 81
#define SC7280_SLAVE_PCIE_0_CFG 82
#define SC7280_SLAVE_PCIE_1_CFG 83
#define SC7280_SLAVE_PDM 84
#define SC7280_SLAVE_PIMEM_CFG 85
#define SC7280_SLAVE_PKA_WRAPPER_CFG 86
#define SC7280_SLAVE_PMU_WRAPPER_CFG 87
#define SC7280_SLAVE_QDSS_CFG 88
#define SC7280_SLAVE_QSPI_0 89
#define SC7280_SLAVE_QUP_0 90
#define SC7280_SLAVE_QUP_1 91
#define SC7280_SLAVE_SDCC_1 92
#define SC7280_SLAVE_SDCC_2 93
#define SC7280_SLAVE_SDCC_4 94
#define SC7280_SLAVE_SECURITY 95
#define SC7280_SLAVE_TCSR 96
#define SC7280_SLAVE_TLMM 97
#define SC7280_SLAVE_UFS_MEM_CFG 98
#define SC7280_SLAVE_USB2 99
#define SC7280_SLAVE_USB3_0 100
#define SC7280_SLAVE_VENUS_CFG 101
#define SC7280_SLAVE_VSENSE_CTRL_CFG 102
#define SC7280_SLAVE_A1NOC_CFG 103
#define SC7280_SLAVE_A1NOC_SNOC 104
#define SC7280_SLAVE_A2NOC_CFG 105
#define SC7280_SLAVE_A2NOC_SNOC 106
#define SC7280_SLAVE_CNOC2_CNOC3 107
#define SC7280_SLAVE_CNOC3_CNOC2 108
#define SC7280_SLAVE_CNOC_A2NOC 109
#define SC7280_SLAVE_DDRSS_CFG 110
#define SC7280_SLAVE_GEM_NOC_CNOC 111
#define SC7280_SLAVE_GEM_NOC_CFG 112
#define SC7280_SLAVE_SNOC_GEM_NOC_GC 113
#define SC7280_SLAVE_SNOC_GEM_NOC_SF 114
#define SC7280_SLAVE_LLCC 115
#define SC7280_SLAVE_MNOC_HF_MEM_NOC 116
#define SC7280_SLAVE_MNOC_SF_MEM_NOC 117
#define SC7280_SLAVE_CNOC_MNOC_CFG 118
#define SC7280_SLAVE_CDSP_MEM_NOC 119
#define SC7280_SLAVE_MEM_NOC_PCIE_SNOC 120
#define SC7280_SLAVE_ANOC_PCIE_GEM_NOC 121
#define SC7280_SLAVE_SNOC_CFG 122
#define SC7280_SLAVE_QUP_CORE_0 123
#define SC7280_SLAVE_QUP_CORE_1 124
#define SC7280_SLAVE_BOOT_IMEM 125
#define SC7280_SLAVE_IMEM 126
#define SC7280_SLAVE_PIMEM 127
#define SC7280_SLAVE_SERVICE_NSP_NOC 128
#define SC7280_SLAVE_SERVICE_A1NOC 129
#define SC7280_SLAVE_SERVICE_A2NOC 130
#define SC7280_SLAVE_SERVICE_GEM_NOC_1 131
#define SC7280_SLAVE_SERVICE_MNOC 132
#define SC7280_SLAVE_SERVICES_LPASS_AML_NOC 133
#define SC7280_SLAVE_SERVICE_LPASS_AG_NOC 134
#define SC7280_SLAVE_SERVICE_GEM_NOC_2 135
#define SC7280_SLAVE_SERVICE_SNOC 136
#define SC7280_SLAVE_SERVICE_GEM_NOC 137
#define SC7280_SLAVE_PCIE_0 138
#define SC7280_SLAVE_PCIE_1 139
#define SC7280_SLAVE_QDSS_STM 140
#define SC7280_SLAVE_TCU 141
#endif
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