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Commit 52260ae4 authored by Rob Clark's avatar Rob Clark
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drm/msm: update generated headers 

Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent 8432a903
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drivers/gpu/drm/msm/adreno/a2xx.xml.h
View file @ 52260ae4
......@@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
Copyright (C) 2013-2016 by the following authors:
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
Copyright (C) 2013-2017 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
......@@ -352,6 +352,38 @@ static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_cln
#define REG_A2XX_RBBM_DEBUG 0x0000039b
#define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c
#define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE 0x00000001
#define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE 0x00000002
#define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE 0x00000004
#define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE 0x00000008
#define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE 0x00000010
#define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE 0x00000020
#define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040
#define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080
#define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE 0x00000100
#define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE 0x00000200
#define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE 0x00000400
#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE 0x00000800
#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE 0x00001000
#define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE 0x00002000
#define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE 0x00004000
#define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE 0x00008000
#define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE 0x00010000
#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE 0x00020000
#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE 0x00040000
#define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000
#define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE 0x00100000
#define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE 0x00200000
#define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE 0x00400000
#define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE 0x00800000
#define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE 0x01000000
#define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE 0x02000000
#define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE 0x04000000
#define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE 0x08000000
#define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE 0x10000000
#define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE 0x20000000
#define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE 0x40000000
#define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000
#define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d
......@@ -477,12 +509,43 @@ static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x000
#define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81
#define REG_A2XX_PA_SU_FACE_DATA 0x00000c86
#define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK 0xffffffe0
#define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT 5
static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val)
{
return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK;
}
#define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00
#define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC 0x00000001
#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK 0x00000ff0
#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT 4
static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val)
{
return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK;
}
#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK 0x000ff000
#define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT 12
static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val)
{
return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK;
}
#define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01
#define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02
#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK 0x00000fff
#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT 0
static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val)
{
return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK;
}
#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK 0x0fff0000
#define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT 16
static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val)
{
return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK;
}
#define REG_A2XX_SQ_DEBUG_MISC 0x00000d05
......@@ -742,6 +805,24 @@ static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
#define REG_A2XX_RB_BLEND_ALPHA 0x00002108
#define REG_A2XX_RB_FOG_COLOR 0x00002109
#define A2XX_RB_FOG_COLOR_FOG_RED__MASK 0x000000ff
#define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT 0
static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val)
{
return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK;
}
#define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK 0x0000ff00
#define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT 8
static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val)
{
return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK;
}
#define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK 0x00ff0000
#define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT 16
static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val)
{
return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK;
}
#define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c
#define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
......@@ -890,14 +971,146 @@ static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val)
#define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000
#define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182
#define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK 0x0000ffff
#define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT 0
static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val)
{
return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK;
}
#define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK 0xffff0000
#define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT 16
static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val)
{
return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK;
}
#define REG_A2XX_SQ_WRAPPING_0 0x00002183
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK 0x0000000f
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT 0
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val)
{
return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK;
}
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK 0x000000f0
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT 4
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val)
{
return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK;
}
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK 0x00000f00
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT 8
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val)
{
return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK;
}
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK 0x0000f000
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT 12
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val)
{
return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK;
}
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK 0x000f0000
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT 16
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val)
{
return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK;
}
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK 0x00f00000
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT 20
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val)
{
return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK;
}
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK 0x0f000000
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT 24
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val)
{
return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK;
}
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK 0xf0000000
#define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT 28
static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val)
{
return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK;
}
#define REG_A2XX_SQ_WRAPPING_1 0x00002184
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK 0x0000000f
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT 0
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val)
{
return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK;
}
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK 0x000000f0
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT 4
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val)
{
return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK;
}
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK 0x00000f00
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT 8
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val)
{
return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK;
}
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK 0x0000f000
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT 12
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val)
{
return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK;
}
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK 0x000f0000
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT 16
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val)
{
return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK;
}
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK 0x00f00000
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT 20
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val)
{
return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK;
}
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK 0x0f000000
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT 24
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val)
{
return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK;
}
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK 0xf0000000
#define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT 28
static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val)
{
return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK;
}
#define REG_A2XX_SQ_PS_PROGRAM 0x000021f6
#define A2XX_SQ_PS_PROGRAM_BASE__MASK 0x00000fff
#define A2XX_SQ_PS_PROGRAM_BASE__SHIFT 0
static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val)
{
return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK;
}
#define A2XX_SQ_PS_PROGRAM_SIZE__MASK 0x00fff000
#define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT 12
static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val)
{
return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK;
}
#define REG_A2XX_SQ_VS_PROGRAM 0x000021f7
#define A2XX_SQ_VS_PROGRAM_BASE__MASK 0x00000fff
#define A2XX_SQ_VS_PROGRAM_BASE__SHIFT 0
static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val)
{
return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK;
}
#define A2XX_SQ_VS_PROGRAM_SIZE__MASK 0x00fff000
#define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT 12
static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val)
{
return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK;
}
#define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9
......@@ -1304,6 +1517,14 @@ static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_a
}
#define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293
#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA 0x00000001
#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK 0x0000007e
#define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT 1
static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val)
{
return ((val) << A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT) & A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK;
}
#define A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z 0x00000100
#define REG_A2XX_VGT_ENHANCE 0x00002294
......@@ -1319,6 +1540,18 @@ static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val)
#define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400
#define REG_A2XX_PA_SC_AA_CONFIG 0x00002301
#define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK 0x00000007
#define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT 0
static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val)
{
return ((val) << A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT) & A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK;
}
#define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK 0x0001e000
#define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT 13
static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val)
{
return ((val) << A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT) & A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK;
}
#define REG_A2XX_PA_SU_VTX_CNTL 0x00002302
#define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001
......@@ -1407,8 +1640,20 @@ static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val)
#define REG_A2XX_PA_SC_AA_MASK 0x00002312
#define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316
#define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK 0x00000007
#define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT 0
static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val)
{
return ((val) << A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT) & A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK;
}
#define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317
#define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK 0x00000003
#define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT 0
static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val)
{
return ((val) << A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT) & A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK;
}
#define REG_A2XX_RB_COPY_CONTROL 0x00002318
#define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007
......
drivers/gpu/drm/msm/adreno/a3xx.xml.h
View file @ 52260ae4
......@@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
Copyright (C) 2013-2016 by the following authors:
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
Copyright (C) 2013-2017 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
......
drivers/gpu/drm/msm/adreno/a4xx.xml.h
View file @ 52260ae4
......@@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
Copyright (C) 2013-2016 by the following authors:
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
Copyright (C) 2013-2017 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
......@@ -3010,11 +3010,11 @@ static inline uint32_t A4XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x0000220b + 0x4*i0; }
static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_2(uint32_t i0) { return 0x0000220c + 0x4*i0; }
#define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xfffffff0
#define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 4
#define A4XX_VFD_FETCH_INSTR_2_SIZE__MASK 0xffffffff
#define A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT 0
static inline uint32_t A4XX_VFD_FETCH_INSTR_2_SIZE(uint32_t val)
{
return ((val >> 4) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
return ((val) << A4XX_VFD_FETCH_INSTR_2_SIZE__SHIFT) & A4XX_VFD_FETCH_INSTR_2_SIZE__MASK;
}
static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_3(uint32_t i0) { return 0x0000220d + 0x4*i0; }
......@@ -3829,6 +3829,44 @@ static inline uint32_t A4XX_PC_HS_PARAM_SPACING(enum a4xx_tess_spacing val)
#define REG_A4XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
#define REG_A4XX_VBIF_PERF_CNT_EN0 0x000030c0
#define REG_A4XX_VBIF_PERF_CNT_EN1 0x000030c1
#define REG_A4XX_VBIF_PERF_CNT_EN2 0x000030c2
#define REG_A4XX_VBIF_PERF_CNT_EN3 0x000030c3
#define REG_A4XX_VBIF_PERF_CNT_SEL0 0x000030d0
#define REG_A4XX_VBIF_PERF_CNT_SEL1 0x000030d1
#define REG_A4XX_VBIF_PERF_CNT_SEL2 0x000030d2
#define REG_A4XX_VBIF_PERF_CNT_SEL3 0x000030d3
#define REG_A4XX_VBIF_PERF_CNT_LOW0 0x000030d8
#define REG_A4XX_VBIF_PERF_CNT_LOW1 0x000030d9
#define REG_A4XX_VBIF_PERF_CNT_LOW2 0x000030da
#define REG_A4XX_VBIF_PERF_CNT_LOW3 0x000030db
#define REG_A4XX_VBIF_PERF_CNT_HIGH0 0x000030e0
#define REG_A4XX_VBIF_PERF_CNT_HIGH1 0x000030e1
#define REG_A4XX_VBIF_PERF_CNT_HIGH2 0x000030e2
#define REG_A4XX_VBIF_PERF_CNT_HIGH3 0x000030e3
#define REG_A4XX_VBIF_PERF_PWR_CNT_EN0 0x00003100
#define REG_A4XX_VBIF_PERF_PWR_CNT_EN1 0x00003101
#define REG_A4XX_VBIF_PERF_PWR_CNT_EN2 0x00003102
#define REG_A4XX_UNKNOWN_0CC5 0x00000cc5
#define REG_A4XX_UNKNOWN_0CC6 0x00000cc6
......
drivers/gpu/drm/msm/adreno/a5xx.xml.h
View file @ 52260ae4
......@@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
Copyright (C) 2013-2016 by the following authors:
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
Copyright (C) 2013-2017 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
......@@ -45,20 +45,50 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
enum a5xx_color_fmt {
RB5_A8_UNORM = 2,
RB5_R8_UNORM = 3,
RB5_R8_SNORM = 4,
RB5_R8_UINT = 5,
RB5_R8_SINT = 6,
RB5_R4G4B4A4_UNORM = 8,
RB5_R5G5B5A1_UNORM = 10,
RB5_R5G6B5_UNORM = 14,
RB5_R8G8_UNORM = 15,
RB5_R8G8_SNORM = 16,
RB5_R8G8_UINT = 17,
RB5_R8G8_SINT = 18,
RB5_R16_UNORM = 21,
RB5_R16_SNORM = 22,
RB5_R16_FLOAT = 23,
RB5_R16_UINT = 24,
RB5_R16_SINT = 25,
RB5_R8G8B8A8_UNORM = 48,
RB5_R8G8B8_UNORM = 49,
RB5_R8G8B8A8_SNORM = 50,
RB5_R8G8B8A8_UINT = 51,
RB5_R8G8B8A8_SINT = 52,
RB5_R10G10B10A2_UNORM = 55,
RB5_R10G10B10A2_UINT = 58,
RB5_R11G11B10_FLOAT = 66,
RB5_R16G16_UNORM = 67,
RB5_R16G16_SNORM = 68,
RB5_R16G16_FLOAT = 69,
RB5_R16G16_UINT = 70,
RB5_R16G16_SINT = 71,
RB5_R32_FLOAT = 74,
RB5_R32_UINT = 75,
RB5_R32_SINT = 76,
RB5_R16G16B16A16_UNORM = 96,
RB5_R16G16B16A16_SNORM = 97,
RB5_R16G16B16A16_FLOAT = 98,
RB5_R16G16B16A16_UINT = 99,
RB5_R16G16B16A16_SINT = 100,
RB5_R32G32_FLOAT = 103,
RB5_R32G32_UINT = 104,
RB5_R32G32_SINT = 105,
RB5_R32G32B32A32_FLOAT = 130,
RB5_R32G32B32A32_UINT = 131,
RB5_R32G32B32A32_SINT = 132,
};
enum a5xx_tile_mode {
......@@ -133,25 +163,55 @@ enum a5xx_vtx_fmt {
enum a5xx_tex_fmt {
TFMT5_A8_UNORM = 2,
TFMT5_8_UNORM = 3,
TFMT5_8_SNORM = 4,
TFMT5_8_UINT = 5,
TFMT5_8_SINT = 6,
TFMT5_4_4_4_4_UNORM = 8,
TFMT5_5_5_5_1_UNORM = 10,
TFMT5_5_6_5_UNORM = 14,
TFMT5_8_8_UNORM = 15,
TFMT5_8_8_SNORM = 16,
TFMT5_8_8_UINT = 17,
TFMT5_8_8_SINT = 18,
TFMT5_L8_A8_UNORM = 19,
TFMT5_16_UNORM = 21,
TFMT5_16_SNORM = 22,
TFMT5_16_FLOAT = 23,
TFMT5_16_UINT = 24,
TFMT5_16_SINT = 25,
TFMT5_8_8_8_8_UNORM = 48,
TFMT5_8_8_8_UNORM = 49,
TFMT5_8_8_8_SNORM = 50,
TFMT5_8_8_8_8_SNORM = 50,
TFMT5_8_8_8_8_UINT = 51,
TFMT5_8_8_8_8_SINT = 52,
TFMT5_9_9_9_E5_FLOAT = 53,
TFMT5_10_10_10_2_UNORM = 54,
TFMT5_10_10_10_2_UINT = 58,
TFMT5_11_11_10_FLOAT = 66,
TFMT5_16_16_UNORM = 67,
TFMT5_16_16_SNORM = 68,
TFMT5_16_16_FLOAT = 69,
TFMT5_16_16_UINT = 70,
TFMT5_16_16_SINT = 71,
TFMT5_32_FLOAT = 74,
TFMT5_32_UINT = 75,
TFMT5_32_SINT = 76,
TFMT5_16_16_16_16_UNORM = 96,
TFMT5_16_16_16_16_SNORM = 97,
TFMT5_16_16_16_16_FLOAT = 98,
TFMT5_16_16_16_16_UINT = 99,
TFMT5_16_16_16_16_SINT = 100,
TFMT5_32_32_FLOAT = 103,
TFMT5_32_32_UINT = 104,
TFMT5_32_32_SINT = 105,
TFMT5_32_32_32_32_FLOAT = 130,
TFMT5_32_32_32_32_UINT = 131,
TFMT5_32_32_32_32_SINT = 132,
TFMT5_X8Z24_UNORM = 160,
TFMT5_RGTC1_UNORM = 183,
TFMT5_RGTC1_SNORM = 184,
TFMT5_RGTC2_UNORM = 187,
TFMT5_RGTC2_SNORM = 188,
};
enum a5xx_tex_fetchsize {
......@@ -182,6 +242,565 @@ enum a5xx_blit_buf {
BLIT_Z32 = 9,
};
enum a5xx_cp_perfcounter_select {
PERF_CP_ALWAYS_COUNT = 0,
PERF_CP_BUSY_GFX_CORE_IDLE = 1,
PERF_CP_BUSY_CYCLES = 2,
PERF_CP_PFP_IDLE = 3,
PERF_CP_PFP_BUSY_WORKING = 4,
PERF_CP_PFP_STALL_CYCLES_ANY = 5,
PERF_CP_PFP_STARVE_CYCLES_ANY = 6,
PERF_CP_PFP_ICACHE_MISS = 7,
PERF_CP_PFP_ICACHE_HIT = 8,
PERF_CP_PFP_MATCH_PM4_PKT_PROFILE = 9,
PERF_CP_ME_BUSY_WORKING = 10,
PERF_CP_ME_IDLE = 11,
PERF_CP_ME_STARVE_CYCLES_ANY = 12,
PERF_CP_ME_FIFO_EMPTY_PFP_IDLE = 13,
PERF_CP_ME_FIFO_EMPTY_PFP_BUSY = 14,
PERF_CP_ME_FIFO_FULL_ME_BUSY = 15,
PERF_CP_ME_FIFO_FULL_ME_NON_WORKING = 16,
PERF_CP_ME_STALL_CYCLES_ANY = 17,
PERF_CP_ME_ICACHE_MISS = 18,
PERF_CP_ME_ICACHE_HIT = 19,
PERF_CP_NUM_PREEMPTIONS = 20,
PERF_CP_PREEMPTION_REACTION_DELAY = 21,
PERF_CP_PREEMPTION_SWITCH_OUT_TIME = 22,
PERF_CP_PREEMPTION_SWITCH_IN_TIME = 23,
PERF_CP_DEAD_DRAWS_IN_BIN_RENDER = 24,
PERF_CP_PREDICATED_DRAWS_KILLED = 25,
PERF_CP_MODE_SWITCH = 26,
PERF_CP_ZPASS_DONE = 27,
PERF_CP_CONTEXT_DONE = 28,
PERF_CP_CACHE_FLUSH = 29,
PERF_CP_LONG_PREEMPTIONS = 30,
};
enum a5xx_rbbm_perfcounter_select {
PERF_RBBM_ALWAYS_COUNT = 0,
PERF_RBBM_ALWAYS_ON = 1,
PERF_RBBM_TSE_BUSY = 2,
PERF_RBBM_RAS_BUSY = 3,
PERF_RBBM_PC_DCALL_BUSY = 4,
PERF_RBBM_PC_VSD_BUSY = 5,
PERF_RBBM_STATUS_MASKED = 6,
PERF_RBBM_COM_BUSY = 7,
PERF_RBBM_DCOM_BUSY = 8,
PERF_RBBM_VBIF_BUSY = 9,
PERF_RBBM_VSC_BUSY = 10,
PERF_RBBM_TESS_BUSY = 11,
PERF_RBBM_UCHE_BUSY = 12,
PERF_RBBM_HLSQ_BUSY = 13,
};
enum a5xx_pc_perfcounter_select {
PERF_PC_BUSY_CYCLES = 0,
PERF_PC_WORKING_CYCLES = 1,
PERF_PC_STALL_CYCLES_VFD = 2,
PERF_PC_STALL_CYCLES_TSE = 3,
PERF_PC_STALL_CYCLES_VPC = 4,
PERF_PC_STALL_CYCLES_UCHE = 5,
PERF_PC_STALL_CYCLES_TESS = 6,
PERF_PC_STALL_CYCLES_TSE_ONLY = 7,
PERF_PC_STALL_CYCLES_VPC_ONLY = 8,
PERF_PC_PASS1_TF_STALL_CYCLES = 9,
PERF_PC_STARVE_CYCLES_FOR_INDEX = 10,
PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR = 11,
PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM = 12,
PERF_PC_STARVE_CYCLES_FOR_POSITION = 13,
PERF_PC_STARVE_CYCLES_DI = 14,
PERF_PC_VIS_STREAMS_LOADED = 15,
PERF_PC_INSTANCES = 16,
PERF_PC_VPC_PRIMITIVES = 17,
PERF_PC_DEAD_PRIM = 18,
PERF_PC_LIVE_PRIM = 19,
PERF_PC_VERTEX_HITS = 20,
PERF_PC_IA_VERTICES = 21,
PERF_PC_IA_PRIMITIVES = 22,
PERF_PC_GS_PRIMITIVES = 23,
PERF_PC_HS_INVOCATIONS = 24,
PERF_PC_DS_INVOCATIONS = 25,
PERF_PC_VS_INVOCATIONS = 26,
PERF_PC_GS_INVOCATIONS = 27,
PERF_PC_DS_PRIMITIVES = 28,
PERF_PC_VPC_POS_DATA_TRANSACTION = 29,
PERF_PC_3D_DRAWCALLS = 30,
PERF_PC_2D_DRAWCALLS = 31,
PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS = 32,
PERF_TESS_BUSY_CYCLES = 33,
PERF_TESS_WORKING_CYCLES = 34,
PERF_TESS_STALL_CYCLES_PC = 35,
PERF_TESS_STARVE_CYCLES_PC = 36,
};
enum a5xx_vfd_perfcounter_select {
PERF_VFD_BUSY_CYCLES = 0,
PERF_VFD_STALL_CYCLES_UCHE = 1,
PERF_VFD_STALL_CYCLES_VPC_ALLOC = 2,
PERF_VFD_STALL_CYCLES_MISS_VB = 3,
PERF_VFD_STALL_CYCLES_MISS_Q = 4,
PERF_VFD_STALL_CYCLES_SP_INFO = 5,
PERF_VFD_STALL_CYCLES_SP_ATTR = 6,
PERF_VFD_STALL_CYCLES_VFDP_VB = 7,
PERF_VFD_STALL_CYCLES_VFDP_Q = 8,
PERF_VFD_DECODER_PACKER_STALL = 9,
PERF_VFD_STARVE_CYCLES_UCHE = 10,
PERF_VFD_RBUFFER_FULL = 11,
PERF_VFD_ATTR_INFO_FIFO_FULL = 12,
PERF_VFD_DECODED_ATTRIBUTE_BYTES = 13,
PERF_VFD_NUM_ATTRIBUTES = 14,
PERF_VFD_INSTRUCTIONS = 15,
PERF_VFD_UPPER_SHADER_FIBERS = 16,
PERF_VFD_LOWER_SHADER_FIBERS = 17,
PERF_VFD_MODE_0_FIBERS = 18,
PERF_VFD_MODE_1_FIBERS = 19,
PERF_VFD_MODE_2_FIBERS = 20,
PERF_VFD_MODE_3_FIBERS = 21,
PERF_VFD_MODE_4_FIBERS = 22,
PERF_VFD_TOTAL_VERTICES = 23,
PERF_VFD_NUM_ATTR_MISS = 24,
PERF_VFD_1_BURST_REQ = 25,
PERF_VFDP_STALL_CYCLES_VFD = 26,
PERF_VFDP_STALL_CYCLES_VFD_INDEX = 27,
PERF_VFDP_STALL_CYCLES_VFD_PROG = 28,
PERF_VFDP_STARVE_CYCLES_PC = 29,
PERF_VFDP_VS_STAGE_32_WAVES = 30,
};
enum a5xx_hlsq_perfcounter_select {
PERF_HLSQ_BUSY_CYCLES = 0,
PERF_HLSQ_STALL_CYCLES_UCHE = 1,
PERF_HLSQ_STALL_CYCLES_SP_STATE = 2,
PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE = 3,
PERF_HLSQ_UCHE_LATENCY_CYCLES = 4,
PERF_HLSQ_UCHE_LATENCY_COUNT = 5,
PERF_HLSQ_FS_STAGE_32_WAVES = 6,
PERF_HLSQ_FS_STAGE_64_WAVES = 7,
PERF_HLSQ_QUADS = 8,
PERF_HLSQ_SP_STATE_COPY_TRANS_FS_STAGE = 9,
PERF_HLSQ_SP_STATE_COPY_TRANS_VS_STAGE = 10,
PERF_HLSQ_TP_STATE_COPY_TRANS_FS_STAGE = 11,
PERF_HLSQ_TP_STATE_COPY_TRANS_VS_STAGE = 12,
PERF_HLSQ_CS_INVOCATIONS = 13,
PERF_HLSQ_COMPUTE_DRAWCALLS = 14,
};
enum a5xx_vpc_perfcounter_select {
PERF_VPC_BUSY_CYCLES = 0,
PERF_VPC_WORKING_CYCLES = 1,
PERF_VPC_STALL_CYCLES_UCHE = 2,
PERF_VPC_STALL_CYCLES_VFD_WACK = 3,
PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC = 4,
PERF_VPC_STALL_CYCLES_PC = 5,
PERF_VPC_STALL_CYCLES_SP_LM = 6,
PERF_VPC_POS_EXPORT_STALL_CYCLES = 7,
PERF_VPC_STARVE_CYCLES_SP = 8,
PERF_VPC_STARVE_CYCLES_LRZ = 9,
PERF_VPC_PC_PRIMITIVES = 10,
PERF_VPC_SP_COMPONENTS = 11,
PERF_VPC_SP_LM_PRIMITIVES = 12,
PERF_VPC_SP_LM_COMPONENTS = 13,
PERF_VPC_SP_LM_DWORDS = 14,
PERF_VPC_STREAMOUT_COMPONENTS = 15,
PERF_VPC_GRANT_PHASES = 16,
};
enum a5xx_tse_perfcounter_select {
PERF_TSE_BUSY_CYCLES = 0,
PERF_TSE_CLIPPING_CYCLES = 1,
PERF_TSE_STALL_CYCLES_RAS = 2,
PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE = 3,
PERF_TSE_STALL_CYCLES_LRZ_ZPLANE = 4,
PERF_TSE_STARVE_CYCLES_PC = 5,
PERF_TSE_INPUT_PRIM = 6,
PERF_TSE_INPUT_NULL_PRIM = 7,
PERF_TSE_TRIVAL_REJ_PRIM = 8,
PERF_TSE_CLIPPED_PRIM = 9,
PERF_TSE_ZERO_AREA_PRIM = 10,
PERF_TSE_FACENESS_CULLED_PRIM = 11,
PERF_TSE_ZERO_PIXEL_PRIM = 12,
PERF_TSE_OUTPUT_NULL_PRIM = 13,
PERF_TSE_OUTPUT_VISIBLE_PRIM = 14,
PERF_TSE_CINVOCATION = 15,
PERF_TSE_CPRIMITIVES = 16,
PERF_TSE_2D_INPUT_PRIM = 17,
PERF_TSE_2D_ALIVE_CLCLES = 18,
};
enum a5xx_ras_perfcounter_select {
PERF_RAS_BUSY_CYCLES = 0,
PERF_RAS_SUPERTILE_ACTIVE_CYCLES = 1,
PERF_RAS_STALL_CYCLES_LRZ = 2,
PERF_RAS_STARVE_CYCLES_TSE = 3,
PERF_RAS_SUPER_TILES = 4,
PERF_RAS_8X4_TILES = 5,
PERF_RAS_MASKGEN_ACTIVE = 6,
PERF_RAS_FULLY_COVERED_SUPER_TILES = 7,
PERF_RAS_FULLY_COVERED_8X4_TILES = 8,
PERF_RAS_PRIM_KILLED_INVISILBE = 9,
};
enum a5xx_lrz_perfcounter_select {
PERF_LRZ_BUSY_CYCLES = 0,
PERF_LRZ_STARVE_CYCLES_RAS = 1,
PERF_LRZ_STALL_CYCLES_RB = 2,
PERF_LRZ_STALL_CYCLES_VSC = 3,
PERF_LRZ_STALL_CYCLES_VPC = 4,
PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH = 5,
PERF_LRZ_STALL_CYCLES_UCHE = 6,
PERF_LRZ_LRZ_READ = 7,
PERF_LRZ_LRZ_WRITE = 8,
PERF_LRZ_READ_LATENCY = 9,
PERF_LRZ_MERGE_CACHE_UPDATING = 10,
PERF_LRZ_PRIM_KILLED_BY_MASKGEN = 11,
PERF_LRZ_PRIM_KILLED_BY_LRZ = 12,
PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ = 13,
PERF_LRZ_FULL_8X8_TILES = 14,
PERF_LRZ_PARTIAL_8X8_TILES = 15,
PERF_LRZ_TILE_KILLED = 16,
PERF_LRZ_TOTAL_PIXEL = 17,
PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ = 18,
};
enum a5xx_uche_perfcounter_select {
PERF_UCHE_BUSY_CYCLES = 0,
PERF_UCHE_STALL_CYCLES_VBIF = 1,
PERF_UCHE_VBIF_LATENCY_CYCLES = 2,
PERF_UCHE_VBIF_LATENCY_SAMPLES = 3,
PERF_UCHE_VBIF_READ_BEATS_TP = 4,
PERF_UCHE_VBIF_READ_BEATS_VFD = 5,
PERF_UCHE_VBIF_READ_BEATS_HLSQ = 6,
PERF_UCHE_VBIF_READ_BEATS_LRZ = 7,
PERF_UCHE_VBIF_READ_BEATS_SP = 8,
PERF_UCHE_READ_REQUESTS_TP = 9,
PERF_UCHE_READ_REQUESTS_VFD = 10,
PERF_UCHE_READ_REQUESTS_HLSQ = 11,
PERF_UCHE_READ_REQUESTS_LRZ = 12,
PERF_UCHE_READ_REQUESTS_SP = 13,
PERF_UCHE_WRITE_REQUESTS_LRZ = 14,
PERF_UCHE_WRITE_REQUESTS_SP = 15,
PERF_UCHE_WRITE_REQUESTS_VPC = 16,
PERF_UCHE_WRITE_REQUESTS_VSC = 17,
PERF_UCHE_EVICTS = 18,
PERF_UCHE_BANK_REQ0 = 19,
PERF_UCHE_BANK_REQ1 = 20,
PERF_UCHE_BANK_REQ2 = 21,
PERF_UCHE_BANK_REQ3 = 22,
PERF_UCHE_BANK_REQ4 = 23,
PERF_UCHE_BANK_REQ5 = 24,
PERF_UCHE_BANK_REQ6 = 25,
PERF_UCHE_BANK_REQ7 = 26,
PERF_UCHE_VBIF_READ_BEATS_CH0 = 27,
PERF_UCHE_VBIF_READ_BEATS_CH1 = 28,
PERF_UCHE_GMEM_READ_BEATS = 29,
PERF_UCHE_FLAG_COUNT = 30,
};
enum a5xx_tp_perfcounter_select {
PERF_TP_BUSY_CYCLES = 0,
PERF_TP_STALL_CYCLES_UCHE = 1,
PERF_TP_LATENCY_CYCLES = 2,
PERF_TP_LATENCY_TRANS = 3,
PERF_TP_FLAG_CACHE_REQUEST_SAMPLES = 4,
PERF_TP_FLAG_CACHE_REQUEST_LATENCY = 5,
PERF_TP_L1_CACHELINE_REQUESTS = 6,
PERF_TP_L1_CACHELINE_MISSES = 7,
PERF_TP_SP_TP_TRANS = 8,
PERF_TP_TP_SP_TRANS = 9,
PERF_TP_OUTPUT_PIXELS = 10,
PERF_TP_FILTER_WORKLOAD_16BIT = 11,
PERF_TP_FILTER_WORKLOAD_32BIT = 12,
PERF_TP_QUADS_RECEIVED = 13,
PERF_TP_QUADS_OFFSET = 14,
PERF_TP_QUADS_SHADOW = 15,
PERF_TP_QUADS_ARRAY = 16,
PERF_TP_QUADS_GRADIENT = 17,
PERF_TP_QUADS_1D = 18,
PERF_TP_QUADS_2D = 19,
PERF_TP_QUADS_BUFFER = 20,
PERF_TP_QUADS_3D = 21,
PERF_TP_QUADS_CUBE = 22,
PERF_TP_STATE_CACHE_REQUESTS = 23,
PERF_TP_STATE_CACHE_MISSES = 24,
PERF_TP_DIVERGENT_QUADS_RECEIVED = 25,
PERF_TP_BINDLESS_STATE_CACHE_REQUESTS = 26,
PERF_TP_BINDLESS_STATE_CACHE_MISSES = 27,
PERF_TP_PRT_NON_RESIDENT_EVENTS = 28,
PERF_TP_OUTPUT_PIXELS_POINT = 29,
PERF_TP_OUTPUT_PIXELS_BILINEAR = 30,
PERF_TP_OUTPUT_PIXELS_MIP = 31,
PERF_TP_OUTPUT_PIXELS_ANISO = 32,
PERF_TP_OUTPUT_PIXELS_ZERO_LOD = 33,
PERF_TP_FLAG_CACHE_REQUESTS = 34,
PERF_TP_FLAG_CACHE_MISSES = 35,
PERF_TP_L1_5_L2_REQUESTS = 36,
PERF_TP_2D_OUTPUT_PIXELS = 37,
PERF_TP_2D_OUTPUT_PIXELS_POINT = 38,
PERF_TP_2D_OUTPUT_PIXELS_BILINEAR = 39,
PERF_TP_2D_FILTER_WORKLOAD_16BIT = 40,
PERF_TP_2D_FILTER_WORKLOAD_32BIT = 41,
};
enum a5xx_sp_perfcounter_select {
PERF_SP_BUSY_CYCLES = 0,
PERF_SP_ALU_WORKING_CYCLES = 1,
PERF_SP_EFU_WORKING_CYCLES = 2,
PERF_SP_STALL_CYCLES_VPC = 3,
PERF_SP_STALL_CYCLES_TP = 4,
PERF_SP_STALL_CYCLES_UCHE = 5,
PERF_SP_STALL_CYCLES_RB = 6,
PERF_SP_SCHEDULER_NON_WORKING = 7,
PERF_SP_WAVE_CONTEXTS = 8,
PERF_SP_WAVE_CONTEXT_CYCLES = 9,
PERF_SP_FS_STAGE_WAVE_CYCLES = 10,
PERF_SP_FS_STAGE_WAVE_SAMPLES = 11,
PERF_SP_VS_STAGE_WAVE_CYCLES = 12,
PERF_SP_VS_STAGE_WAVE_SAMPLES = 13,
PERF_SP_FS_STAGE_DURATION_CYCLES = 14,
PERF_SP_VS_STAGE_DURATION_CYCLES = 15,
PERF_SP_WAVE_CTRL_CYCLES = 16,
PERF_SP_WAVE_LOAD_CYCLES = 17,
PERF_SP_WAVE_EMIT_CYCLES = 18,
PERF_SP_WAVE_NOP_CYCLES = 19,
PERF_SP_WAVE_WAIT_CYCLES = 20,
PERF_SP_WAVE_FETCH_CYCLES = 21,
PERF_SP_WAVE_IDLE_CYCLES = 22,
PERF_SP_WAVE_END_CYCLES = 23,
PERF_SP_WAVE_LONG_SYNC_CYCLES = 24,
PERF_SP_WAVE_SHORT_SYNC_CYCLES = 25,
PERF_SP_WAVE_JOIN_CYCLES = 26,
PERF_SP_LM_LOAD_INSTRUCTIONS = 27,
PERF_SP_LM_STORE_INSTRUCTIONS = 28,
PERF_SP_LM_ATOMICS = 29,
PERF_SP_GM_LOAD_INSTRUCTIONS = 30,
PERF_SP_GM_STORE_INSTRUCTIONS = 31,
PERF_SP_GM_ATOMICS = 32,
PERF_SP_VS_STAGE_TEX_INSTRUCTIONS = 33,
PERF_SP_VS_STAGE_CFLOW_INSTRUCTIONS = 34,
PERF_SP_VS_STAGE_EFU_INSTRUCTIONS = 35,
PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS = 36,
PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS = 37,
PERF_SP_FS_STAGE_TEX_INSTRUCTIONS = 38,
PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS = 39,
PERF_SP_FS_STAGE_EFU_INSTRUCTIONS = 40,
PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS = 41,
PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS = 42,
PERF_SP_FS_STAGE_BARY_INSTRUCTIONS = 43,
PERF_SP_VS_INSTRUCTIONS = 44,
PERF_SP_FS_INSTRUCTIONS = 45,
PERF_SP_ADDR_LOCK_COUNT = 46,
PERF_SP_UCHE_READ_TRANS = 47,
PERF_SP_UCHE_WRITE_TRANS = 48,
PERF_SP_EXPORT_VPC_TRANS = 49,
PERF_SP_EXPORT_RB_TRANS = 50,
PERF_SP_PIXELS_KILLED = 51,
PERF_SP_ICL1_REQUESTS = 52,
PERF_SP_ICL1_MISSES = 53,
PERF_SP_ICL0_REQUESTS = 54,
PERF_SP_ICL0_MISSES = 55,
PERF_SP_HS_INSTRUCTIONS = 56,
PERF_SP_DS_INSTRUCTIONS = 57,
PERF_SP_GS_INSTRUCTIONS = 58,
PERF_SP_CS_INSTRUCTIONS = 59,
PERF_SP_GPR_READ = 60,
PERF_SP_GPR_WRITE = 61,
PERF_SP_LM_CH0_REQUESTS = 62,
PERF_SP_LM_CH1_REQUESTS = 63,
PERF_SP_LM_BANK_CONFLICTS = 64,
};
enum a5xx_rb_perfcounter_select {
PERF_RB_BUSY_CYCLES = 0,
PERF_RB_STALL_CYCLES_CCU = 1,
PERF_RB_STALL_CYCLES_HLSQ = 2,
PERF_RB_STALL_CYCLES_FIFO0_FULL = 3,
PERF_RB_STALL_CYCLES_FIFO1_FULL = 4,
PERF_RB_STALL_CYCLES_FIFO2_FULL = 5,
PERF_RB_STARVE_CYCLES_SP = 6,
PERF_RB_STARVE_CYCLES_LRZ_TILE = 7,
PERF_RB_STARVE_CYCLES_CCU = 8,
PERF_RB_STARVE_CYCLES_Z_PLANE = 9,
PERF_RB_STARVE_CYCLES_BARY_PLANE = 10,
PERF_RB_Z_WORKLOAD = 11,
PERF_RB_HLSQ_ACTIVE = 12,
PERF_RB_Z_READ = 13,
PERF_RB_Z_WRITE = 14,
PERF_RB_C_READ = 15,
PERF_RB_C_WRITE = 16,
PERF_RB_TOTAL_PASS = 17,
PERF_RB_Z_PASS = 18,
PERF_RB_Z_FAIL = 19,
PERF_RB_S_FAIL = 20,
PERF_RB_BLENDED_FXP_COMPONENTS = 21,
PERF_RB_BLENDED_FP16_COMPONENTS = 22,
RB_RESERVED = 23,
PERF_RB_2D_ALIVE_CYCLES = 24,
PERF_RB_2D_STALL_CYCLES_A2D = 25,
PERF_RB_2D_STARVE_CYCLES_SRC = 26,
PERF_RB_2D_STARVE_CYCLES_SP = 27,
PERF_RB_2D_STARVE_CYCLES_DST = 28,
PERF_RB_2D_VALID_PIXELS = 29,
};
enum a5xx_rb_samples_perfcounter_select {
TOTAL_SAMPLES = 0,
ZPASS_SAMPLES = 1,
ZFAIL_SAMPLES = 2,
SFAIL_SAMPLES = 3,
};
enum a5xx_vsc_perfcounter_select {
PERF_VSC_BUSY_CYCLES = 0,
PERF_VSC_WORKING_CYCLES = 1,
PERF_VSC_STALL_CYCLES_UCHE = 2,
PERF_VSC_EOT_NUM = 3,
};
enum a5xx_ccu_perfcounter_select {
PERF_CCU_BUSY_CYCLES = 0,
PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN = 1,
PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN = 2,
PERF_CCU_STARVE_CYCLES_FLAG_RETURN = 3,
PERF_CCU_DEPTH_BLOCKS = 4,
PERF_CCU_COLOR_BLOCKS = 5,
PERF_CCU_DEPTH_BLOCK_HIT = 6,
PERF_CCU_COLOR_BLOCK_HIT = 7,
PERF_CCU_PARTIAL_BLOCK_READ = 8,
PERF_CCU_GMEM_READ = 9,
PERF_CCU_GMEM_WRITE = 10,
PERF_CCU_DEPTH_READ_FLAG0_COUNT = 11,
PERF_CCU_DEPTH_READ_FLAG1_COUNT = 12,
PERF_CCU_DEPTH_READ_FLAG2_COUNT = 13,
PERF_CCU_DEPTH_READ_FLAG3_COUNT = 14,
PERF_CCU_DEPTH_READ_FLAG4_COUNT = 15,
PERF_CCU_COLOR_READ_FLAG0_COUNT = 16,
PERF_CCU_COLOR_READ_FLAG1_COUNT = 17,
PERF_CCU_COLOR_READ_FLAG2_COUNT = 18,
PERF_CCU_COLOR_READ_FLAG3_COUNT = 19,
PERF_CCU_COLOR_READ_FLAG4_COUNT = 20,
PERF_CCU_2D_BUSY_CYCLES = 21,
PERF_CCU_2D_RD_REQ = 22,
PERF_CCU_2D_WR_REQ = 23,
PERF_CCU_2D_REORDER_STARVE_CYCLES = 24,
PERF_CCU_2D_PIXELS = 25,
};
enum a5xx_cmp_perfcounter_select {
PERF_CMPDECMP_STALL_CYCLES_VBIF = 0,
PERF_CMPDECMP_VBIF_LATENCY_CYCLES = 1,
PERF_CMPDECMP_VBIF_LATENCY_SAMPLES = 2,
PERF_CMPDECMP_VBIF_READ_DATA_CCU = 3,
PERF_CMPDECMP_VBIF_WRITE_DATA_CCU = 4,
PERF_CMPDECMP_VBIF_READ_REQUEST = 5,
PERF_CMPDECMP_VBIF_WRITE_REQUEST = 6,
PERF_CMPDECMP_VBIF_READ_DATA = 7,
PERF_CMPDECMP_VBIF_WRITE_DATA = 8,
PERF_CMPDECMP_FLAG_FETCH_CYCLES = 9,
PERF_CMPDECMP_FLAG_FETCH_SAMPLES = 10,
PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT = 11,
PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT = 12,
PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT = 13,
PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT = 14,
PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT = 15,
PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT = 16,
PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT = 17,
PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT = 18,
PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ = 19,
PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR = 20,
PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN = 21,
PERF_CMPDECMP_2D_RD_DATA = 22,
PERF_CMPDECMP_2D_WR_DATA = 23,
};
enum a5xx_vbif_perfcounter_select {
AXI_READ_REQUESTS_ID_0 = 0,
AXI_READ_REQUESTS_ID_1 = 1,
AXI_READ_REQUESTS_ID_2 = 2,
AXI_READ_REQUESTS_ID_3 = 3,
AXI_READ_REQUESTS_ID_4 = 4,
AXI_READ_REQUESTS_ID_5 = 5,
AXI_READ_REQUESTS_ID_6 = 6,
AXI_READ_REQUESTS_ID_7 = 7,
AXI_READ_REQUESTS_ID_8 = 8,
AXI_READ_REQUESTS_ID_9 = 9,
AXI_READ_REQUESTS_ID_10 = 10,
AXI_READ_REQUESTS_ID_11 = 11,
AXI_READ_REQUESTS_ID_12 = 12,
AXI_READ_REQUESTS_ID_13 = 13,
AXI_READ_REQUESTS_ID_14 = 14,
AXI_READ_REQUESTS_ID_15 = 15,
AXI0_READ_REQUESTS_TOTAL = 16,
AXI1_READ_REQUESTS_TOTAL = 17,
AXI2_READ_REQUESTS_TOTAL = 18,
AXI3_READ_REQUESTS_TOTAL = 19,
AXI_READ_REQUESTS_TOTAL = 20,
AXI_WRITE_REQUESTS_ID_0 = 21,
AXI_WRITE_REQUESTS_ID_1 = 22,
AXI_WRITE_REQUESTS_ID_2 = 23,
AXI_WRITE_REQUESTS_ID_3 = 24,
AXI_WRITE_REQUESTS_ID_4 = 25,
AXI_WRITE_REQUESTS_ID_5 = 26,
AXI_WRITE_REQUESTS_ID_6 = 27,
AXI_WRITE_REQUESTS_ID_7 = 28,
AXI_WRITE_REQUESTS_ID_8 = 29,
AXI_WRITE_REQUESTS_ID_9 = 30,
AXI_WRITE_REQUESTS_ID_10 = 31,
AXI_WRITE_REQUESTS_ID_11 = 32,
AXI_WRITE_REQUESTS_ID_12 = 33,
AXI_WRITE_REQUESTS_ID_13 = 34,
AXI_WRITE_REQUESTS_ID_14 = 35,
AXI_WRITE_REQUESTS_ID_15 = 36,
AXI0_WRITE_REQUESTS_TOTAL = 37,
AXI1_WRITE_REQUESTS_TOTAL = 38,
AXI2_WRITE_REQUESTS_TOTAL = 39,
AXI3_WRITE_REQUESTS_TOTAL = 40,
AXI_WRITE_REQUESTS_TOTAL = 41,
AXI_TOTAL_REQUESTS = 42,
AXI_READ_DATA_BEATS_ID_0 = 43,
AXI_READ_DATA_BEATS_ID_1 = 44,
AXI_READ_DATA_BEATS_ID_2 = 45,
AXI_READ_DATA_BEATS_ID_3 = 46,
AXI_READ_DATA_BEATS_ID_4 = 47,
AXI_READ_DATA_BEATS_ID_5 = 48,
AXI_READ_DATA_BEATS_ID_6 = 49,
AXI_READ_DATA_BEATS_ID_7 = 50,
AXI_READ_DATA_BEATS_ID_8 = 51,
AXI_READ_DATA_BEATS_ID_9 = 52,
AXI_READ_DATA_BEATS_ID_10 = 53,
AXI_READ_DATA_BEATS_ID_11 = 54,
AXI_READ_DATA_BEATS_ID_12 = 55,
AXI_READ_DATA_BEATS_ID_13 = 56,
AXI_READ_DATA_BEATS_ID_14 = 57,
AXI_READ_DATA_BEATS_ID_15 = 58,
AXI0_READ_DATA_BEATS_TOTAL = 59,
AXI1_READ_DATA_BEATS_TOTAL = 60,
AXI2_READ_DATA_BEATS_TOTAL = 61,
AXI3_READ_DATA_BEATS_TOTAL = 62,
AXI_READ_DATA_BEATS_TOTAL = 63,
AXI_WRITE_DATA_BEATS_ID_0 = 64,
AXI_WRITE_DATA_BEATS_ID_1 = 65,
AXI_WRITE_DATA_BEATS_ID_2 = 66,
AXI_WRITE_DATA_BEATS_ID_3 = 67,
AXI_WRITE_DATA_BEATS_ID_4 = 68,
AXI_WRITE_DATA_BEATS_ID_5 = 69,
AXI_WRITE_DATA_BEATS_ID_6 = 70,
AXI_WRITE_DATA_BEATS_ID_7 = 71,
AXI_WRITE_DATA_BEATS_ID_8 = 72,
AXI_WRITE_DATA_BEATS_ID_9 = 73,
AXI_WRITE_DATA_BEATS_ID_10 = 74,
AXI_WRITE_DATA_BEATS_ID_11 = 75,
AXI_WRITE_DATA_BEATS_ID_12 = 76,
AXI_WRITE_DATA_BEATS_ID_13 = 77,
AXI_WRITE_DATA_BEATS_ID_14 = 78,
AXI_WRITE_DATA_BEATS_ID_15 = 79,
AXI0_WRITE_DATA_BEATS_TOTAL = 80,
AXI1_WRITE_DATA_BEATS_TOTAL = 81,
AXI2_WRITE_DATA_BEATS_TOTAL = 82,
AXI3_WRITE_DATA_BEATS_TOTAL = 83,
AXI_WRITE_DATA_BEATS_TOTAL = 84,
AXI_DATA_BEATS_TOTAL = 85,
};
enum a5xx_tex_filter {
A5XX_TEX_NEAREST = 0,
A5XX_TEX_LINEAR = 1,
......@@ -1289,25 +1908,83 @@ static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val)
#define REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL 0x0000f810
#define REG_A5XX_VSC_PIPE_DATA_LENGTH_0 0x00000c00
#define REG_A5XX_VSC_BIN_SIZE 0x00000bc2
#define A5XX_VSC_BIN_SIZE_WIDTH__MASK 0x000000ff
#define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
{
return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK;
}
#define A5XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001fe00
#define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT 9
static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
{
return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK;
}
#define REG_A5XX_VSC_SIZE_ADDRESS_LO 0x00000bc3
#define REG_A5XX_VSC_SIZE_ADDRESS_HI 0x00000bc4
#define REG_A5XX_UNKNOWN_0BC5 0x00000bc5
#define REG_A5XX_UNKNOWN_0BC6 0x00000bc6
static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; }
#define A5XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff
#define A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT 0
static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_X(uint32_t val)
{
return ((val) << A5XX_VSC_PIPE_CONFIG_REG_X__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_X__MASK;
}
#define A5XX_VSC_PIPE_CONFIG_REG_Y__MASK 0x000ffc00
#define A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT 10
static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_Y(uint32_t val)
{
return ((val) << A5XX_VSC_PIPE_CONFIG_REG_Y__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_Y__MASK;
}
#define A5XX_VSC_PIPE_CONFIG_REG_W__MASK 0x00f00000
#define A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT 20
static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_W(uint32_t val)
{
return ((val) << A5XX_VSC_PIPE_CONFIG_REG_W__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_W__MASK;
}
#define A5XX_VSC_PIPE_CONFIG_REG_H__MASK 0x0f000000
#define A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT 24
static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val)
{
return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK;
}
static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; }
static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; }
static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; }
#define REG_A5XX_VSC_PERFCTR_VSC_SEL_0 0x00000c60
#define REG_A5XX_VSC_PERFCTR_VSC_SEL_1 0x00000c61
#define REG_A5XX_VSC_BIN_SIZE 0x00000cdd
#define A5XX_VSC_BIN_SIZE_WINDOW_OFFSET_DISABLE 0x80000000
#define A5XX_VSC_BIN_SIZE_X__MASK 0x00007fff
#define A5XX_VSC_BIN_SIZE_X__SHIFT 0
static inline uint32_t A5XX_VSC_BIN_SIZE_X(uint32_t val)
#define REG_A5XX_VSC_RESOLVE_CNTL 0x00000cdd
#define A5XX_VSC_RESOLVE_CNTL_WINDOW_OFFSET_DISABLE 0x80000000
#define A5XX_VSC_RESOLVE_CNTL_X__MASK 0x00007fff
#define A5XX_VSC_RESOLVE_CNTL_X__SHIFT 0
static inline uint32_t A5XX_VSC_RESOLVE_CNTL_X(uint32_t val)
{
return ((val) << A5XX_VSC_BIN_SIZE_X__SHIFT) & A5XX_VSC_BIN_SIZE_X__MASK;
return ((val) << A5XX_VSC_RESOLVE_CNTL_X__SHIFT) & A5XX_VSC_RESOLVE_CNTL_X__MASK;
}
#define A5XX_VSC_BIN_SIZE_Y__MASK 0x7fff0000
#define A5XX_VSC_BIN_SIZE_Y__SHIFT 16
static inline uint32_t A5XX_VSC_BIN_SIZE_Y(uint32_t val)
#define A5XX_VSC_RESOLVE_CNTL_Y__MASK 0x7fff0000
#define A5XX_VSC_RESOLVE_CNTL_Y__SHIFT 16
static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val)
{
return ((val) << A5XX_VSC_BIN_SIZE_Y__SHIFT) & A5XX_VSC_BIN_SIZE_Y__MASK;
return ((val) << A5XX_VSC_RESOLVE_CNTL_Y__SHIFT) & A5XX_VSC_RESOLVE_CNTL_Y__MASK;
}
#define REG_A5XX_GRAS_ADDR_MODE_CNTL 0x00000c81
......@@ -1470,6 +2147,7 @@ static inline uint32_t A5XX_VSC_BIN_SIZE_Y(uint32_t val)
#define REG_A5XX_VPC_ADDR_MODE_CNTL 0x00000e61
#define REG_A5XX_VPC_MODE_CNTL 0x00000e62
#define A5XX_VPC_MODE_CNTL_BINNING_PASS 0x00000001
#define REG_A5XX_VPC_PERFCTR_VPC_SEL_0 0x00000e64
......@@ -1641,6 +2319,14 @@ static inline uint32_t A5XX_VSC_BIN_SIZE_Y(uint32_t val)
#define REG_A5XX_VBIF_TEST_BUS_OUT 0x0000308c
#define REG_A5XX_VBIF_PERF_CNT_EN0 0x000030c0
#define REG_A5XX_VBIF_PERF_CNT_EN1 0x000030c1
#define REG_A5XX_VBIF_PERF_CNT_EN2 0x000030c2
#define REG_A5XX_VBIF_PERF_CNT_EN3 0x000030c3
#define REG_A5XX_VBIF_PERF_CNT_SEL0 0x000030d0
#define REG_A5XX_VBIF_PERF_CNT_SEL1 0x000030d1
......@@ -1911,6 +2597,11 @@ static inline uint32_t A5XX_VSC_BIN_SIZE_Y(uint32_t val)
#define REG_A5XX_GRAS_CNTL 0x0000e005
#define A5XX_GRAS_CNTL_VARYING 0x00000001
#define A5XX_GRAS_CNTL_UNK3 0x00000008
#define A5XX_GRAS_CNTL_XCOORD 0x00000040
#define A5XX_GRAS_CNTL_YCOORD 0x00000080
#define A5XX_GRAS_CNTL_ZCOORD 0x00000100
#define A5XX_GRAS_CNTL_WCOORD 0x00000200
#define REG_A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x0000e006
#define A5XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000003ff
......@@ -1975,6 +2666,8 @@ static inline uint32_t A5XX_GRAS_CL_VPORT_ZSCALE_0(float val)
}
#define REG_A5XX_GRAS_SU_CNTL 0x0000e090
#define A5XX_GRAS_SU_CNTL_CULL_FRONT 0x00000001
#define A5XX_GRAS_SU_CNTL_CULL_BACK 0x00000002
#define A5XX_GRAS_SU_CNTL_FRONT_CW 0x00000004
#define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK 0x000007f8
#define A5XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT 3
......@@ -2010,7 +2703,8 @@ static inline uint32_t A5XX_GRAS_SU_POINT_SIZE(float val)
#define REG_A5XX_UNKNOWN_E093 0x0000e093
#define REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL 0x0000e094
#define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_ALPHA_TEST_ENABLE 0x00000001
#define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
#define A5XX_GRAS_SU_DEPTH_PLANE_CNTL_UNK1 0x00000002
#define REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000e095
#define A5XX_GRAS_SU_POLY_OFFSET_SCALE__MASK 0xffffffff
......@@ -2047,6 +2741,7 @@ static inline uint32_t A5XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_dep
#define REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x0000e099
#define REG_A5XX_GRAS_SC_CNTL 0x0000e0a0
#define A5XX_GRAS_SC_CNTL_BINNING_PASS 0x00000001
#define A5XX_GRAS_SC_CNTL_SAMPLES_PASSED 0x00008000
#define REG_A5XX_GRAS_SC_BIN_CNTL 0x0000e0a1
......@@ -2161,12 +2856,21 @@ static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
}
#define REG_A5XX_GRAS_LRZ_CNTL 0x0000e100
#define A5XX_GRAS_LRZ_CNTL_ENABLE 0x00000001
#define A5XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002
#define A5XX_GRAS_LRZ_CNTL_GREATER 0x00000004
#define REG_A5XX_GRAS_LRZ_BUFFER_BASE_LO 0x0000e101
#define REG_A5XX_GRAS_LRZ_BUFFER_BASE_HI 0x0000e102
#define REG_A5XX_GRAS_LRZ_BUFFER_PITCH 0x0000e103
#define A5XX_GRAS_LRZ_BUFFER_PITCH__MASK 0xffffffff
#define A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT 0
static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val)
{
return ((val >> 5) << A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT) & A5XX_GRAS_LRZ_BUFFER_PITCH__MASK;
}
#define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104
......@@ -2188,7 +2892,9 @@ static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val)
#define A5XX_RB_CNTL_BYPASS 0x00020000
#define REG_A5XX_RB_RENDER_CNTL 0x0000e141
#define A5XX_RB_RENDER_CNTL_BINNING_PASS 0x00000001
#define A5XX_RB_RENDER_CNTL_SAMPLES_PASSED 0x00000040
#define A5XX_RB_RENDER_CNTL_DISABLE_COLOR_PIPE 0x00000080
#define A5XX_RB_RENDER_CNTL_FLAG_DEPTH 0x00004000
#define A5XX_RB_RENDER_CNTL_FLAG_DEPTH2 0x00008000
#define A5XX_RB_RENDER_CNTL_FLAG_MRTS__MASK 0x00ff0000
......@@ -2223,6 +2929,7 @@ static inline uint32_t A5XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val
#define REG_A5XX_RB_RENDER_CONTROL0 0x0000e144
#define A5XX_RB_RENDER_CONTROL0_VARYING 0x00000001
#define A5XX_RB_RENDER_CONTROL0_UNK3 0x00000008
#define A5XX_RB_RENDER_CONTROL0_XCOORD 0x00000040
#define A5XX_RB_RENDER_CONTROL0_YCOORD 0x00000080
#define A5XX_RB_RENDER_CONTROL0_ZCOORD 0x00000100
......@@ -2525,6 +3232,7 @@ static inline uint32_t A5XX_RB_BLEND_CNTL_SAMPLE_MASK(uint32_t val)
#define REG_A5XX_RB_DEPTH_PLANE_CNTL 0x0000e1b0
#define A5XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z 0x00000001
#define A5XX_RB_DEPTH_PLANE_CNTL_UNK1 0x00000002
#define REG_A5XX_RB_DEPTH_CNTL 0x0000e1b1
#define A5XX_RB_DEPTH_CNTL_Z_ENABLE 0x00000001
......@@ -2554,7 +3262,7 @@ static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_fo
#define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
{
return ((val >> 5) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK;
return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK;
}
#define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6
......@@ -2562,7 +3270,7 @@ static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val)
#define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val)
{
return ((val >> 5) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK;
}
#define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0
......@@ -2678,8 +3386,11 @@ static inline uint32_t A5XX_RB_WINDOW_OFFSET_Y(uint32_t val)
return ((val) << A5XX_RB_WINDOW_OFFSET_Y__SHIFT) & A5XX_RB_WINDOW_OFFSET_Y__MASK;
}
#define REG_A5XX_RB_SAMPLE_COUNT_CONTROL 0x0000e1d1
#define A5XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
#define REG_A5XX_RB_BLIT_CNTL 0x0000e210
#define A5XX_RB_BLIT_CNTL_BUF__MASK 0x0000003f
#define A5XX_RB_BLIT_CNTL_BUF__MASK 0x0000000f
#define A5XX_RB_BLIT_CNTL_BUF__SHIFT 0
static inline uint32_t A5XX_RB_BLIT_CNTL_BUF(enum a5xx_blit_buf val)
{
......@@ -2803,6 +3514,10 @@ static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val)
return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK;
}
#define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO 0x0000e267
#define REG_A5XX_RB_SAMPLE_COUNT_ADDR_HI 0x0000e268
#define REG_A5XX_VPC_CNTL_0 0x0000e280
#define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__MASK 0x0000007f
#define A5XX_VPC_CNTL_0_STRIDE_IN_VPC__SHIFT 0
......@@ -2839,32 +3554,71 @@ static inline uint32_t A5XX_VPC_PACK_NUMNONPOSVAR(uint32_t val)
{
return ((val) << A5XX_VPC_PACK_NUMNONPOSVAR__SHIFT) & A5XX_VPC_PACK_NUMNONPOSVAR__MASK;
}
#define A5XX_VPC_PACK_PSIZELOC__MASK 0x0000ff00
#define A5XX_VPC_PACK_PSIZELOC__SHIFT 8
static inline uint32_t A5XX_VPC_PACK_PSIZELOC(uint32_t val)
{
return ((val) << A5XX_VPC_PACK_PSIZELOC__SHIFT) & A5XX_VPC_PACK_PSIZELOC__MASK;
}
#define REG_A5XX_VPC_FS_PRIMITIVEID_CNTL 0x0000e2a0
#define REG_A5XX_UNKNOWN_E2A1 0x0000e2a1
#define REG_A5XX_VPC_SO_BUF_CNTL 0x0000e2a1
#define A5XX_VPC_SO_BUF_CNTL_BUF0 0x00000001
#define A5XX_VPC_SO_BUF_CNTL_BUF1 0x00000008
#define A5XX_VPC_SO_BUF_CNTL_BUF2 0x00000040
#define A5XX_VPC_SO_BUF_CNTL_BUF3 0x00000200
#define A5XX_VPC_SO_BUF_CNTL_ENABLE 0x00008000
#define REG_A5XX_VPC_SO_OVERRIDE 0x0000e2a2
#define A5XX_VPC_SO_OVERRIDE_SO_DISABLE 0x00000001
#define REG_A5XX_VPC_SO_BUFFER_BASE_LO_0 0x0000e2a7
#define REG_A5XX_VPC_SO_CNTL 0x0000e2a3
#define A5XX_VPC_SO_CNTL_ENABLE 0x00010000
#define REG_A5XX_VPC_SO_BUFFER_BASE_HI_0 0x0000e2a8
#define REG_A5XX_VPC_SO_PROG 0x0000e2a4
#define A5XX_VPC_SO_PROG_A_BUF__MASK 0x00000003
#define A5XX_VPC_SO_PROG_A_BUF__SHIFT 0
static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val)
{
return ((val) << A5XX_VPC_SO_PROG_A_BUF__SHIFT) & A5XX_VPC_SO_PROG_A_BUF__MASK;
}
#define A5XX_VPC_SO_PROG_A_OFF__MASK 0x000007fc
#define A5XX_VPC_SO_PROG_A_OFF__SHIFT 2
static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val)
{
return ((val >> 2) << A5XX_VPC_SO_PROG_A_OFF__SHIFT) & A5XX_VPC_SO_PROG_A_OFF__MASK;
}
#define A5XX_VPC_SO_PROG_A_EN 0x00000800
#define A5XX_VPC_SO_PROG_B_BUF__MASK 0x00003000
#define A5XX_VPC_SO_PROG_B_BUF__SHIFT 12
static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val)
{
return ((val) << A5XX_VPC_SO_PROG_B_BUF__SHIFT) & A5XX_VPC_SO_PROG_B_BUF__MASK;
}
#define A5XX_VPC_SO_PROG_B_OFF__MASK 0x007fc000
#define A5XX_VPC_SO_PROG_B_OFF__SHIFT 14
static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val)
{
return ((val >> 2) << A5XX_VPC_SO_PROG_B_OFF__SHIFT) & A5XX_VPC_SO_PROG_B_OFF__MASK;
}
#define A5XX_VPC_SO_PROG_B_EN 0x00800000
#define REG_A5XX_VPC_SO_BUFFER_SIZE_0 0x0000e2a9
static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
#define REG_A5XX_UNKNOWN_E2AB 0x0000e2ab
static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; }
#define REG_A5XX_VPC_SO_FLUSH_BASE_LO_0 0x0000e2ac
static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_HI(uint32_t i0) { return 0x0000e2a8 + 0x7*i0; }
#define REG_A5XX_VPC_SO_FLUSH_BASE_HI_0 0x0000e2ad
static inline uint32_t REG_A5XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000e2a9 + 0x7*i0; }
#define REG_A5XX_UNKNOWN_E2AE 0x0000e2ae
static inline uint32_t REG_A5XX_VPC_SO_NCOMP(uint32_t i0) { return 0x0000e2aa + 0x7*i0; }
#define REG_A5XX_UNKNOWN_E2B2 0x0000e2b2
static inline uint32_t REG_A5XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000e2ab + 0x7*i0; }
#define REG_A5XX_UNKNOWN_E2B9 0x0000e2b9
static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_LO(uint32_t i0) { return 0x0000e2ac + 0x7*i0; }
#define REG_A5XX_UNKNOWN_E2C0 0x0000e2c0
static inline uint32_t REG_A5XX_VPC_SO_FLUSH_BASE_HI(uint32_t i0) { return 0x0000e2ad + 0x7*i0; }
#define REG_A5XX_PC_PRIMITIVE_CNTL 0x0000e384
#define A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000007f
......@@ -2873,6 +3627,7 @@ static inline uint32_t A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)
{
return ((val) << A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_PC_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK;
}
#define A5XX_PC_PRIMITIVE_CNTL_PROVOKING_VTX_LAST 0x00000400
#define REG_A5XX_PC_PRIM_VTX_CNTL 0x0000e385
#define A5XX_PC_PRIM_VTX_CNTL_PSIZE 0x00000800
......@@ -2900,18 +3655,18 @@ static inline uint32_t A5XX_VFD_CONTROL_0_VTXCNT(uint32_t val)
}
#define REG_A5XX_VFD_CONTROL_1 0x0000e401
#define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x000000ff
#define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 0
static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
{
return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK;
}
#define A5XX_VFD_CONTROL_1_REGID4INST__MASK 0x0000ff00
#define A5XX_VFD_CONTROL_1_REGID4INST__SHIFT 8
static inline uint32_t A5XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
{
return ((val) << A5XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A5XX_VFD_CONTROL_1_REGID4INST__MASK;
}
#define A5XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
#define A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
static inline uint32_t A5XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
{
return ((val) << A5XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A5XX_VFD_CONTROL_1_REGID4VTX__MASK;
}
#define REG_A5XX_VFD_CONTROL_2 0x0000e402
......@@ -2944,18 +3699,15 @@ static inline uint32_t A5XX_VFD_DECODE_INSTR_IDX(uint32_t val)
{
return ((val) << A5XX_VFD_DECODE_INSTR_IDX__SHIFT) & A5XX_VFD_DECODE_INSTR_IDX__MASK;
}
#define A5XX_VFD_DECODE_INSTR_INSTANCED 0x00020000
#define A5XX_VFD_DECODE_INSTR_FORMAT__MASK 0x3ff00000
#define A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT 20
static inline uint32_t A5XX_VFD_DECODE_INSTR_FORMAT(enum a5xx_vtx_fmt val)
{
return ((val) << A5XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A5XX_VFD_DECODE_INSTR_FORMAT__MASK;
}
#define A5XX_VFD_DECODE_INSTR_SWAP__MASK 0xc0000000
#define A5XX_VFD_DECODE_INSTR_SWAP__SHIFT 30
static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
{
return ((val) << A5XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A5XX_VFD_DECODE_INSTR_SWAP__MASK;
}
#define A5XX_VFD_DECODE_INSTR_UNK30 0x40000000
#define A5XX_VFD_DECODE_INSTR_FLOAT 0x80000000
static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; }
......@@ -2979,88 +3731,107 @@ static inline uint32_t A5XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val)
#define REG_A5XX_SP_SP_CNTL 0x0000e580
#define REG_A5XX_SP_VS_CONTROL_REG 0x0000e584
#define A5XX_SP_VS_CONTROL_REG_ENABLED 0x00000001
#define A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
#define REG_A5XX_SP_VS_CONFIG 0x0000e584
#define A5XX_SP_VS_CONFIG_ENABLED 0x00000001
#define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
{
return ((val) << A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
return ((val) << A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
}
#define A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
#define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_SP_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
{
return ((val) << A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
return ((val) << A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_VS_CONFIG_SHADEROBJOFFSET__MASK;
}
#define REG_A5XX_SP_FS_CONTROL_REG 0x0000e585
#define A5XX_SP_FS_CONTROL_REG_ENABLED 0x00000001
#define A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
#define REG_A5XX_SP_FS_CONFIG 0x0000e585
#define A5XX_SP_FS_CONFIG_ENABLED 0x00000001
#define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
{
return ((val) << A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
return ((val) << A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
}
#define A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
#define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_SP_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
{
return ((val) << A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
return ((val) << A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_FS_CONFIG_SHADEROBJOFFSET__MASK;
}
#define REG_A5XX_SP_HS_CONTROL_REG 0x0000e586
#define A5XX_SP_HS_CONTROL_REG_ENABLED 0x00000001
#define A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
#define REG_A5XX_SP_HS_CONFIG 0x0000e586
#define A5XX_SP_HS_CONFIG_ENABLED 0x00000001
#define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
{
return ((val) << A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
return ((val) << A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
}
#define A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
#define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_SP_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
{
return ((val) << A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
return ((val) << A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_HS_CONFIG_SHADEROBJOFFSET__MASK;
}
#define REG_A5XX_SP_DS_CONTROL_REG 0x0000e587
#define A5XX_SP_DS_CONTROL_REG_ENABLED 0x00000001
#define A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
#define REG_A5XX_SP_DS_CONFIG 0x0000e587
#define A5XX_SP_DS_CONFIG_ENABLED 0x00000001
#define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
{
return ((val) << A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
return ((val) << A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
}
#define A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
#define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_SP_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
{
return ((val) << A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
return ((val) << A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_DS_CONFIG_SHADEROBJOFFSET__MASK;
}
#define REG_A5XX_SP_GS_CONTROL_REG 0x0000e588
#define A5XX_SP_GS_CONTROL_REG_ENABLED 0x00000001
#define A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
#define REG_A5XX_SP_GS_CONFIG 0x0000e588
#define A5XX_SP_GS_CONFIG_ENABLED 0x00000001
#define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
{
return ((val) << A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
return ((val) << A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
}
#define A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
#define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_SP_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
{
return ((val) << A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
return ((val) << A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_GS_CONFIG_SHADEROBJOFFSET__MASK;
}
#define REG_A5XX_SP_CS_CONFIG 0x0000e589
#define A5XX_SP_CS_CONFIG_ENABLED 0x00000001
#define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
{
return ((val) << A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
}
#define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_SP_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
{
return ((val) << A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_SP_CS_CONFIG_SHADEROBJOFFSET__MASK;
}
#define REG_A5XX_SP_VS_CONFIG_MAX_CONST 0x0000e58a
#define REG_A5XX_SP_FS_CONFIG_MAX_CONST 0x0000e58b
#define REG_A5XX_SP_VS_CTRL_REG0 0x0000e590
#define A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00000008
#define A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 3
static inline uint32_t A5XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
{
return ((val) << A5XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
}
#define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
#define A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
static inline uint32_t A5XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
......@@ -3075,13 +3846,19 @@ static inline uint32_t A5XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
}
#define A5XX_SP_VS_CTRL_REG0_VARYING 0x00010000
#define A5XX_SP_VS_CTRL_REG0_PIXLODENABLE 0x00100000
#define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
#define A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT 25
static inline uint32_t A5XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val)
{
return ((val) << A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK;
}
#define REG_A5XX_SP_PRIMITIVE_CNTL 0x0000e592
#define A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK 0x0000001f
#define A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT 0
static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC(uint32_t val)
#define A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK 0x0000001f
#define A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT 0
static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val)
{
return ((val >> 2) << A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_STRIDE_IN_VPC__MASK;
return ((val) << A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK;
}
static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; }
......@@ -3147,6 +3924,12 @@ static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
#define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad
#define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0
#define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00000008
#define A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 3
static inline uint32_t A5XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
{
return ((val) << A5XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
}
#define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
#define A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
static inline uint32_t A5XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
......@@ -3161,6 +3944,12 @@ static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
}
#define A5XX_SP_FS_CTRL_REG0_VARYING 0x00010000
#define A5XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00100000
#define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
#define A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT 25
static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val)
{
return ((val) << A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK;
}
#define REG_A5XX_UNKNOWN_E5C2 0x0000e5c2
......@@ -3169,6 +3958,8 @@ static inline uint32_t A5XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
#define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4
#define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9
#define A5XX_SP_BLEND_CNTL_ENABLED 0x00000001
#define A5XX_SP_BLEND_CNTL_UNK8 0x00000100
#define REG_A5XX_SP_FS_OUTPUT_CNTL 0x0000e5ca
#define A5XX_SP_FS_OUTPUT_CNTL_MRT__MASK 0x0000000f
......@@ -3210,15 +4001,66 @@ static inline uint32_t A5XX_SP_FS_MRT_REG_COLOR_FORMAT(enum a5xx_color_fmt val)
{
return ((val) << A5XX_SP_FS_MRT_REG_COLOR_FORMAT__SHIFT) & A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK;
}
#define A5XX_SP_FS_MRT_REG_COLOR_SRGB 0x00000400
#define REG_A5XX_UNKNOWN_E5DB 0x0000e5db
#define REG_A5XX_SP_CS_CNTL_0 0x0000e5f0
#define REG_A5XX_UNKNOWN_E5F2 0x0000e5f2
#define REG_A5XX_SP_CS_OBJ_START_LO 0x0000e5f3
#define REG_A5XX_SP_CS_OBJ_START_HI 0x0000e5f4
#define REG_A5XX_SP_CS_CTRL_REG0 0x0000e5f0
#define A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00000008
#define A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 3
static inline uint32_t A5XX_SP_CS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
{
return ((val) << A5XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A5XX_SP_CS_CTRL_REG0_THREADSIZE__MASK;
}
#define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
#define A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
static inline uint32_t A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
{
return ((val) << A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
}
#define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
#define A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
static inline uint32_t A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
{
return ((val) << A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A5XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
}
#define A5XX_SP_CS_CTRL_REG0_VARYING 0x00010000
#define A5XX_SP_CS_CTRL_REG0_PIXLODENABLE 0x00100000
#define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK 0xfe000000
#define A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT 25
static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val)
{
return ((val) << A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A5XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK;
}
#define REG_A5XX_UNKNOWN_E600 0x0000e600
#define REG_A5XX_UNKNOWN_E602 0x0000e602
#define REG_A5XX_SP_HS_OBJ_START_LO 0x0000e603
#define REG_A5XX_SP_HS_OBJ_START_HI 0x0000e604
#define REG_A5XX_UNKNOWN_E62B 0x0000e62b
#define REG_A5XX_SP_DS_OBJ_START_LO 0x0000e62c
#define REG_A5XX_SP_DS_OBJ_START_HI 0x0000e62d
#define REG_A5XX_UNKNOWN_E640 0x0000e640
#define REG_A5XX_UNKNOWN_E65B 0x0000e65b
#define REG_A5XX_SP_GS_OBJ_START_LO 0x0000e65c
#define REG_A5XX_SP_GS_OBJ_START_HI 0x0000e65d
#define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704
#define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003
#define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0
......@@ -3236,29 +4078,85 @@ static inline uint32_t A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_sample
}
#define A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004
#define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO 0x0000e706
#define REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_HI 0x0000e707
#define REG_A5XX_TPL1_VS_TEX_COUNT 0x0000e700
#define REG_A5XX_TPL1_HS_TEX_COUNT 0x0000e701
#define REG_A5XX_TPL1_DS_TEX_COUNT 0x0000e702
#define REG_A5XX_TPL1_GS_TEX_COUNT 0x0000e703
#define REG_A5XX_TPL1_VS_TEX_SAMP_LO 0x0000e722
#define REG_A5XX_TPL1_VS_TEX_SAMP_HI 0x0000e723
#define REG_A5XX_TPL1_HS_TEX_SAMP_LO 0x0000e724
#define REG_A5XX_TPL1_HS_TEX_SAMP_HI 0x0000e725
#define REG_A5XX_TPL1_DS_TEX_SAMP_LO 0x0000e726
#define REG_A5XX_TPL1_DS_TEX_SAMP_HI 0x0000e727
#define REG_A5XX_TPL1_GS_TEX_SAMP_LO 0x0000e728
#define REG_A5XX_TPL1_GS_TEX_SAMP_HI 0x0000e729
#define REG_A5XX_TPL1_VS_TEX_CONST_LO 0x0000e72a
#define REG_A5XX_TPL1_VS_TEX_CONST_HI 0x0000e72b
#define REG_A5XX_TPL1_HS_TEX_CONST_LO 0x0000e72c
#define REG_A5XX_TPL1_HS_TEX_CONST_HI 0x0000e72d
#define REG_A5XX_TPL1_DS_TEX_CONST_LO 0x0000e72e
#define REG_A5XX_TPL1_DS_TEX_CONST_HI 0x0000e72f
#define REG_A5XX_TPL1_GS_TEX_CONST_LO 0x0000e730
#define REG_A5XX_TPL1_GS_TEX_CONST_HI 0x0000e731
#define REG_A5XX_TPL1_FS_TEX_COUNT 0x0000e750
#define REG_A5XX_TPL1_CS_TEX_COUNT 0x0000e751
#define REG_A5XX_TPL1_FS_TEX_SAMP_LO 0x0000e75a
#define REG_A5XX_TPL1_FS_TEX_SAMP_HI 0x0000e75b
#define REG_A5XX_TPL1_CS_TEX_SAMP_LO 0x0000e75c
#define REG_A5XX_TPL1_CS_TEX_SAMP_HI 0x0000e75d
#define REG_A5XX_TPL1_FS_TEX_CONST_LO 0x0000e75e
#define REG_A5XX_TPL1_FS_TEX_CONST_HI 0x0000e75f
#define REG_A5XX_TPL1_CS_TEX_CONST_LO 0x0000e760
#define REG_A5XX_TPL1_CS_TEX_CONST_HI 0x0000e761
#define REG_A5XX_TPL1_TP_FS_ROTATION_CNTL 0x0000e764
#define REG_A5XX_HLSQ_CONTROL_0_REG 0x0000e784
#define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000001
#define A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 0
static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
{
return ((val) << A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
}
#define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK 0x00000004
#define A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT 2
static inline uint32_t A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE(enum a3xx_threadsize val)
{
return ((val) << A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__SHIFT) & A5XX_HLSQ_CONTROL_0_REG_CSTHREADSIZE__MASK;
}
#define REG_A5XX_HLSQ_CONTROL_1_REG 0x0000e785
#define A5XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x0000003f
......@@ -3300,84 +4198,98 @@ static inline uint32_t A5XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val)
#define REG_A5XX_HLSQ_UPDATE_CNTL 0x0000e78a
#define REG_A5XX_HLSQ_VS_CONTROL_REG 0x0000e78b
#define A5XX_HLSQ_VS_CONTROL_REG_ENABLED 0x00000001
#define A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
#define REG_A5XX_HLSQ_VS_CONFIG 0x0000e78b
#define A5XX_HLSQ_VS_CONFIG_ENABLED 0x00000001
#define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
{
return ((val) << A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
return ((val) << A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_CONSTOBJECTOFFSET__MASK;
}
#define A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
#define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET(uint32_t val)
{
return ((val) << A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONTROL_REG_SHADEROBJOFFSET__MASK;
return ((val) << A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_VS_CONFIG_SHADEROBJOFFSET__MASK;
}
#define REG_A5XX_HLSQ_FS_CONTROL_REG 0x0000e78c
#define A5XX_HLSQ_FS_CONTROL_REG_ENABLED 0x00000001
#define A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
#define REG_A5XX_HLSQ_FS_CONFIG 0x0000e78c
#define A5XX_HLSQ_FS_CONFIG_ENABLED 0x00000001
#define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
{
return ((val) << A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
return ((val) << A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_CONSTOBJECTOFFSET__MASK;
}
#define A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
#define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET(uint32_t val)
{
return ((val) << A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONTROL_REG_SHADEROBJOFFSET__MASK;
return ((val) << A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_FS_CONFIG_SHADEROBJOFFSET__MASK;
}
#define REG_A5XX_HLSQ_HS_CONTROL_REG 0x0000e78d
#define A5XX_HLSQ_HS_CONTROL_REG_ENABLED 0x00000001
#define A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
#define REG_A5XX_HLSQ_HS_CONFIG 0x0000e78d
#define A5XX_HLSQ_HS_CONFIG_ENABLED 0x00000001
#define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
{
return ((val) << A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
return ((val) << A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_CONSTOBJECTOFFSET__MASK;
}
#define A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
#define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET(uint32_t val)
{
return ((val) << A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONTROL_REG_SHADEROBJOFFSET__MASK;
return ((val) << A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_HS_CONFIG_SHADEROBJOFFSET__MASK;
}
#define REG_A5XX_HLSQ_DS_CONTROL_REG 0x0000e78e
#define A5XX_HLSQ_DS_CONTROL_REG_ENABLED 0x00000001
#define A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
#define REG_A5XX_HLSQ_DS_CONFIG 0x0000e78e
#define A5XX_HLSQ_DS_CONFIG_ENABLED 0x00000001
#define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
{
return ((val) << A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
return ((val) << A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_CONSTOBJECTOFFSET__MASK;
}
#define A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
#define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET(uint32_t val)
{
return ((val) << A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONTROL_REG_SHADEROBJOFFSET__MASK;
return ((val) << A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_DS_CONFIG_SHADEROBJOFFSET__MASK;
}
#define REG_A5XX_HLSQ_GS_CONTROL_REG 0x0000e78f
#define A5XX_HLSQ_GS_CONTROL_REG_ENABLED 0x00000001
#define A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET(uint32_t val)
#define REG_A5XX_HLSQ_GS_CONFIG 0x0000e78f
#define A5XX_HLSQ_GS_CONFIG_ENABLED 0x00000001
#define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
{
return ((val) << A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONTROL_REG_CONSTOBJECTOFFSET__MASK;
return ((val) << A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_CONSTOBJECTOFFSET__MASK;
}
#define A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET(uint32_t val)
#define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET(uint32_t val)
{
return ((val) << A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONTROL_REG_SHADEROBJOFFSET__MASK;
return ((val) << A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_GS_CONFIG_SHADEROBJOFFSET__MASK;
}
#define REG_A5XX_HLSQ_CS_CONFIG 0x0000e790
#define A5XX_HLSQ_CS_CONFIG_ENABLED 0x00000001
#define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK 0x000000fe
#define A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT 1
static inline uint32_t A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET(uint32_t val)
{
return ((val) << A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_CONSTOBJECTOFFSET__MASK;
}
#define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK 0x00007f00
#define A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT 8
static inline uint32_t A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET(uint32_t val)
{
return ((val) << A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__SHIFT) & A5XX_HLSQ_CS_CONFIG_SHADEROBJOFFSET__MASK;
}
#define REG_A5XX_HLSQ_VS_CNTL 0x0000e791
#define A5XX_HLSQ_VS_CNTL_SSBO_ENABLE 0x00000001
#define A5XX_HLSQ_VS_CNTL_INSTRLEN__MASK 0xfffffffe
#define A5XX_HLSQ_VS_CNTL_INSTRLEN__SHIFT 1
static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val)
......@@ -3386,6 +4298,7 @@ static inline uint32_t A5XX_HLSQ_VS_CNTL_INSTRLEN(uint32_t val)
}
#define REG_A5XX_HLSQ_FS_CNTL 0x0000e792
#define A5XX_HLSQ_FS_CNTL_SSBO_ENABLE 0x00000001
#define A5XX_HLSQ_FS_CNTL_INSTRLEN__MASK 0xfffffffe
#define A5XX_HLSQ_FS_CNTL_INSTRLEN__SHIFT 1
static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val)
......@@ -3394,6 +4307,7 @@ static inline uint32_t A5XX_HLSQ_FS_CNTL_INSTRLEN(uint32_t val)
}
#define REG_A5XX_HLSQ_HS_CNTL 0x0000e793
#define A5XX_HLSQ_HS_CNTL_SSBO_ENABLE 0x00000001
#define A5XX_HLSQ_HS_CNTL_INSTRLEN__MASK 0xfffffffe
#define A5XX_HLSQ_HS_CNTL_INSTRLEN__SHIFT 1
static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val)
......@@ -3402,6 +4316,7 @@ static inline uint32_t A5XX_HLSQ_HS_CNTL_INSTRLEN(uint32_t val)
}
#define REG_A5XX_HLSQ_DS_CNTL 0x0000e794
#define A5XX_HLSQ_DS_CNTL_SSBO_ENABLE 0x00000001
#define A5XX_HLSQ_DS_CNTL_INSTRLEN__MASK 0xfffffffe
#define A5XX_HLSQ_DS_CNTL_INSTRLEN__SHIFT 1
static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val)
......@@ -3410,6 +4325,7 @@ static inline uint32_t A5XX_HLSQ_DS_CNTL_INSTRLEN(uint32_t val)
}
#define REG_A5XX_HLSQ_GS_CNTL 0x0000e795
#define A5XX_HLSQ_GS_CNTL_SSBO_ENABLE 0x00000001
#define A5XX_HLSQ_GS_CNTL_INSTRLEN__MASK 0xfffffffe
#define A5XX_HLSQ_GS_CNTL_INSTRLEN__SHIFT 1
static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val)
......@@ -3418,6 +4334,7 @@ static inline uint32_t A5XX_HLSQ_GS_CNTL_INSTRLEN(uint32_t val)
}
#define REG_A5XX_HLSQ_CS_CNTL 0x0000e796
#define A5XX_HLSQ_CS_CNTL_SSBO_ENABLE 0x00000001
#define A5XX_HLSQ_CS_CNTL_INSTRLEN__MASK 0xfffffffe
#define A5XX_HLSQ_CS_CNTL_INSTRLEN__SHIFT 1
static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val)
......@@ -3432,20 +4349,86 @@ static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val)
#define REG_A5XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000e7bb
#define REG_A5XX_HLSQ_CS_NDRANGE_0 0x0000e7b0
#define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003
#define A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val)
{
return ((val) << A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK;
}
#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc
#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val)
{
return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK;
}
#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000
#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val)
{
return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK;
}
#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000
#define A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val)
{
return ((val) << A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A5XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK;
}
#define REG_A5XX_HLSQ_CS_NDRANGE_1 0x0000e7b1
#define A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__MASK 0xffffffff
#define A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__SHIFT 0
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_1_SIZE_X(uint32_t val)
{
return ((val) << A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__SHIFT) & A5XX_HLSQ_CS_NDRANGE_1_SIZE_X__MASK;
}
#define REG_A5XX_HLSQ_CS_NDRANGE_2 0x0000e7b2
#define REG_A5XX_HLSQ_CS_NDRANGE_3 0x0000e7b3
#define A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__MASK 0xffffffff
#define A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__SHIFT 0
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y(uint32_t val)
{
return ((val) << A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__SHIFT) & A5XX_HLSQ_CS_NDRANGE_3_SIZE_Y__MASK;
}
#define REG_A5XX_HLSQ_CS_NDRANGE_4 0x0000e7b4
#define REG_A5XX_HLSQ_CS_NDRANGE_5 0x0000e7b5
#define A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__MASK 0xffffffff
#define A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__SHIFT 0
static inline uint32_t A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z(uint32_t val)
{
return ((val) << A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__SHIFT) & A5XX_HLSQ_CS_NDRANGE_5_SIZE_Z__MASK;
}
#define REG_A5XX_HLSQ_CS_NDRANGE_6 0x0000e7b6
#define REG_A5XX_HLSQ_CS_CNTL_0 0x0000e7b7
#define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff
#define A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT 0
static inline uint32_t A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID(uint32_t val)
{
return ((val) << A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_WGIDCONSTID__MASK;
}
#define A5XX_HLSQ_CS_CNTL_0_UNK0__MASK 0x0000ff00
#define A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT 8
static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK0(uint32_t val)
{
return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK0__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK0__MASK;
}
#define A5XX_HLSQ_CS_CNTL_0_UNK1__MASK 0x00ff0000
#define A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT 16
static inline uint32_t A5XX_HLSQ_CS_CNTL_0_UNK1(uint32_t val)
{
return ((val) << A5XX_HLSQ_CS_CNTL_0_UNK1__SHIFT) & A5XX_HLSQ_CS_CNTL_0_UNK1__MASK;
}
#define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK 0xff000000
#define A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT 24
static inline uint32_t A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID(uint32_t val)
{
return ((val) << A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__SHIFT) & A5XX_HLSQ_CS_CNTL_0_LOCALIDREGID__MASK;
}
#define REG_A5XX_HLSQ_CS_CNTL_1 0x0000e7b8
......@@ -3457,16 +4440,12 @@ static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val)
#define REG_A5XX_UNKNOWN_E7C5 0x0000e7c5
#define REG_A5XX_UNKNOWN_E7CA 0x0000e7ca
#define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7
#define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8
#define REG_A5XX_HLSQ_HS_CONSTLEN 0x0000e7c8
#define REG_A5XX_HLSQ_HS_INSTRLEN 0x0000e7c9
#define REG_A5XX_UNKNOWN_E7CA 0x0000e7ca
#define REG_A5XX_HLSQ_DS_CONSTLEN 0x0000e7cd
#define REG_A5XX_HLSQ_DS_INSTRLEN 0x0000e7ce
......@@ -3479,13 +4458,23 @@ static inline uint32_t A5XX_HLSQ_CS_CNTL_INSTRLEN(uint32_t val)
#define REG_A5XX_UNKNOWN_E7D4 0x0000e7d4
#define REG_A5XX_HLSQ_FS_CONSTLEN 0x0000e7d7
#define REG_A5XX_HLSQ_FS_INSTRLEN 0x0000e7d8
#define REG_A5XX_UNKNOWN_E7D9 0x0000e7d9
#define REG_A5XX_HLSQ_CONTEXT_SWITCH_CS_SW_3 0x0000e7dc
#define REG_A5XX_HLSQ_CS_CONSTLEN 0x0000e7dc
#define REG_A5XX_HLSQ_CS_INSTRLEN 0x0000e7dd
#define REG_A5XX_RB_2D_SRC_SOLID_DW0 0x00002101
#define REG_A5XX_HLSQ_CONTEXT_SWITCH_CS_SW_4 0x0000e7dd
#define REG_A5XX_RB_2D_SRC_SOLID_DW1 0x00002102
#define REG_A5XX_RB_2D_DST_FILL 0x00002101
#define REG_A5XX_RB_2D_SRC_SOLID_DW2 0x00002103
#define REG_A5XX_RB_2D_SRC_SOLID_DW3 0x00002104
#define REG_A5XX_RB_2D_SRC_INFO 0x00002107
#define A5XX_RB_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff
......@@ -3505,6 +4494,20 @@ static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val)
#define REG_A5XX_RB_2D_SRC_HI 0x00002109
#define REG_A5XX_RB_2D_SRC_SIZE 0x0000210a
#define A5XX_RB_2D_SRC_SIZE_PITCH__MASK 0x0000ffff
#define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val)
{
return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK;
}
#define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK 0xffff0000
#define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT 16
static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val)
{
return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK;
}
#define REG_A5XX_RB_2D_DST_INFO 0x00002110
#define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__MASK 0x000000ff
#define A5XX_RB_2D_DST_INFO_COLOR_FORMAT__SHIFT 0
......@@ -3519,14 +4522,28 @@ static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val)
return ((val) << A5XX_RB_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_RB_2D_DST_INFO_COLOR_SWAP__MASK;
}
#define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140
#define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141
#define REG_A5XX_RB_2D_DST_LO 0x00002111
#define REG_A5XX_RB_2D_DST_HI 0x00002112
#define REG_A5XX_RB_2D_DST_SIZE 0x00002113
#define A5XX_RB_2D_DST_SIZE_PITCH__MASK 0x0000ffff
#define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT 0
static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val)
{
return ((val >> 6) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK;
}
#define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK 0xffff0000
#define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT 16
static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val)
{
return ((val >> 6) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK;
}
#define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140
#define REG_A5XX_RB_2D_SRC_FLAGS_HI 0x00002141
#define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143
#define REG_A5XX_RB_2D_DST_FLAGS_HI 0x00002144
......@@ -3559,6 +4576,12 @@ static inline uint32_t A5XX_GRAS_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val
return ((val) << A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__SHIFT) & A5XX_GRAS_2D_DST_INFO_COLOR_SWAP__MASK;
}
#define REG_A5XX_UNKNOWN_2100 0x00002100
#define REG_A5XX_UNKNOWN_2180 0x00002180
#define REG_A5XX_UNKNOWN_2184 0x00002184
#define REG_A5XX_TEX_SAMP_0 0x00000000
#define A5XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR 0x00000001
#define A5XX_TEX_SAMP_0_XY_MAG__MASK 0x00000006
......@@ -3628,6 +4651,12 @@ static inline uint32_t A5XX_TEX_SAMP_1_MIN_LOD(float val)
}
#define REG_A5XX_TEX_SAMP_2 0x00000002
#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK 0xfffffff0
#define A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT 4
static inline uint32_t A5XX_TEX_SAMP_2_BCOLOR_OFFSET(uint32_t val)
{
return ((val) << A5XX_TEX_SAMP_2_BCOLOR_OFFSET__SHIFT) & A5XX_TEX_SAMP_2_BCOLOR_OFFSET__MASK;
}
#define REG_A5XX_TEX_SAMP_3 0x00000003
......@@ -3663,6 +4692,12 @@ static inline uint32_t A5XX_TEX_CONST_0_SWIZ_W(enum a5xx_tex_swiz val)
{
return ((val) << A5XX_TEX_CONST_0_SWIZ_W__SHIFT) & A5XX_TEX_CONST_0_SWIZ_W__MASK;
}
#define A5XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
#define A5XX_TEX_CONST_0_MIPLVLS__SHIFT 16
static inline uint32_t A5XX_TEX_CONST_0_MIPLVLS(uint32_t val)
{
return ((val) << A5XX_TEX_CONST_0_MIPLVLS__SHIFT) & A5XX_TEX_CONST_0_MIPLVLS__MASK;
}
#define A5XX_TEX_CONST_0_FMT__MASK 0x3fc00000
#define A5XX_TEX_CONST_0_FMT__SHIFT 22
static inline uint32_t A5XX_TEX_CONST_0_FMT(enum a5xx_tex_fmt val)
......
drivers/gpu/drm/msm/adreno/adreno_common.xml.h
View file @ 52260ae4
......@@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
Copyright (C) 2013-2016 by the following authors:
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
Copyright (C) 2013-2017 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
......@@ -421,6 +421,35 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val)
#define REG_AXXX_CP_IB2_BUFSZ 0x0000045b
#define REG_AXXX_CP_STAT 0x0000047f
#define AXXX_CP_STAT_CP_BUSY 0x80000000
#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY 0x40000000
#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY 0x20000000
#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY 0x10000000
#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY 0x08000000
#define AXXX_CP_STAT_ME_BUSY 0x04000000
#define AXXX_CP_STAT_MIU_WR_C_BUSY 0x02000000
#define AXXX_CP_STAT_CP_3D_BUSY 0x00800000
#define AXXX_CP_STAT_CP_NRT_BUSY 0x00400000
#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY 0x00200000
#define AXXX_CP_STAT_RCIU_ME_BUSY 0x00100000
#define AXXX_CP_STAT_RCIU_PFP_BUSY 0x00080000
#define AXXX_CP_STAT_MEQ_RING_BUSY 0x00040000
#define AXXX_CP_STAT_PFP_BUSY 0x00020000
#define AXXX_CP_STAT_ST_QUEUE_BUSY 0x00010000
#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY 0x00002000
#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY 0x00001000
#define AXXX_CP_STAT_RING_QUEUE_BUSY 0x00000800
#define AXXX_CP_STAT_CSF_BUSY 0x00000400
#define AXXX_CP_STAT_CSF_ST_BUSY 0x00000200
#define AXXX_CP_STAT_EVENT_BUSY 0x00000100
#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY 0x00000080
#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY 0x00000040
#define AXXX_CP_STAT_CSF_RING_BUSY 0x00000020
#define AXXX_CP_STAT_RCIU_BUSY 0x00000010
#define AXXX_CP_STAT_RBIU_BUSY 0x00000008
#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY 0x00000004
#define AXXX_CP_STAT_MIU_RD_REQ_BUSY 0x00000002
#define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001
#define REG_AXXX_CP_SCRATCH_REG0 0x00000578
......
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
View file @ 52260ae4
......@@ -8,17 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 90321 bytes, from 2016-11-28 16:50:05)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
Copyright (C) 2013-2016 by the following authors:
- /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-06 18:26:14)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 139480 bytes, from 2017-06-16 12:44:39)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
Copyright (C) 2013-2017 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
......@@ -67,10 +67,18 @@ enum vgt_event_type {
PERFCOUNTER_STOP = 24,
VS_FETCH_DONE = 27,
FACENESS_FLUSH = 28,
FLUSH_SO_0 = 17,
FLUSH_SO_1 = 18,
FLUSH_SO_2 = 19,
FLUSH_SO_3 = 20,
UNK_19 = 25,
UNK_1C = 28,
UNK_1D = 29,
BLIT = 30,
UNK_26 = 38,
UNK_25 = 37,
LRZ_FLUSH = 38,
UNK_2C = 44,
UNK_2D = 45,
};
enum pc_di_primtype {
......@@ -134,11 +142,13 @@ enum adreno_pm4_type3_packets {
CP_WAIT_IB_PFD_COMPLETE = 93,
CP_REG_RMW = 33,
CP_SET_BIN_DATA = 47,
CP_SET_BIN_DATA5 = 47,
CP_REG_TO_MEM = 62,
CP_MEM_WRITE = 61,
CP_MEM_WRITE_CNTR = 79,
CP_COND_EXEC = 68,
CP_COND_WRITE = 69,
CP_COND_WRITE5 = 69,
CP_EVENT_WRITE = 70,
CP_EVENT_WRITE_SHD = 88,
CP_EVENT_WRITE_CFL = 89,
......@@ -165,6 +175,7 @@ enum adreno_pm4_type3_packets {
CP_SET_PROTECTED_MODE = 95,
CP_BOOTSTRAP_UCODE = 111,
CP_LOAD_STATE = 48,
CP_LOAD_STATE4 = 48,
CP_COND_INDIRECT_BUFFER_PFE = 58,
CP_COND_INDIRECT_BUFFER_PFD = 50,
CP_INDIRECT_BUFFER_PFE = 63,
......@@ -204,6 +215,7 @@ enum adreno_pm4_type3_packets {
CP_COMPUTE_CHECKPOINT = 110,
CP_MEM_TO_MEM = 115,
CP_BLIT = 44,
CP_UNK_39 = 57,
IN_IB_PREFETCH_END = 23,
IN_SUBBLK_PREFETCH = 31,
IN_INSTR_PREFETCH = 32,
......@@ -239,21 +251,61 @@ enum adreno_state_src {
SS_INDIRECT_STM = 6,
};
enum a4xx_state_block {
SB4_VS_TEX = 0,
SB4_HS_TEX = 1,
SB4_DS_TEX = 2,
SB4_GS_TEX = 3,
SB4_FS_TEX = 4,
SB4_CS_TEX = 5,
SB4_VS_SHADER = 8,
SB4_HS_SHADER = 9,
SB4_DS_SHADER = 10,
SB4_GS_SHADER = 11,
SB4_FS_SHADER = 12,
SB4_CS_SHADER = 13,
SB4_SSBO = 14,
SB4_CS_SSBO = 15,
};
enum a4xx_state_type {
ST4_SHADER = 0,
ST4_CONSTANTS = 1,
};
enum a4xx_state_src {
SS4_DIRECT = 0,
SS4_INDIRECT = 2,
};
enum a4xx_index_size {
INDEX4_SIZE_8_BIT = 0,
INDEX4_SIZE_16_BIT = 1,
INDEX4_SIZE_32_BIT = 2,
};
enum cp_cond_function {
WRITE_ALWAYS = 0,
WRITE_LT = 1,
WRITE_LE = 2,
WRITE_EQ = 3,
WRITE_NE = 4,
WRITE_GE = 5,
WRITE_GT = 6,
};
enum render_mode_cmd {
BYPASS = 1,
BINNING = 2,
GMEM = 3,
BLIT2D = 5,
BLIT2DSCALE = 7,
};
enum cp_blit_cmd {
BLIT_OP_FILL = 0,
BLIT_OP_BLIT = 1,
BLIT_OP_COPY = 1,
BLIT_OP_SCALE = 3,
};
#define REG_CP_LOAD_STATE_0 0x00000000
......@@ -296,12 +348,52 @@ static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
}
#define REG_CP_LOAD_STATE_2 0x00000002
#define CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
#define CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__SHIFT 0
static inline uint32_t CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(uint32_t val)
#define REG_CP_LOAD_STATE4_0 0x00000000
#define CP_LOAD_STATE4_0_DST_OFF__MASK 0x0000ffff
#define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0
static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
{
return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;
}
#define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000
#define CP_LOAD_STATE4_0_STATE_SRC__SHIFT 16
static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)
{
return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;
}
#define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000
#define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT 18
static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)
{
return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;
}
#define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000
#define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT 22
static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)
{
return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;
}
#define REG_CP_LOAD_STATE4_1 0x00000001
#define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003
#define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0
static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)
{
return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;
}
#define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc
#define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2
static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
{
return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
}
#define REG_CP_LOAD_STATE4_2 0x00000002
#define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
#define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0
static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
{
return ((val) << CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__MASK;
return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;
}
#define REG_CP_DRAW_INDX_0 0x00000000
......@@ -570,6 +662,52 @@ static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
}
#define REG_CP_SET_BIN_DATA5_0 0x00000000
#define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000
#define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16
static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
{
return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
}
#define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000
#define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22
static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
{
return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
}
#define REG_CP_SET_BIN_DATA5_1 0x00000001
#define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff
#define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0
static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
{
return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
}
#define REG_CP_SET_BIN_DATA5_2 0x00000002
#define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff
#define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0
static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
{
return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
}
#define REG_CP_SET_BIN_DATA5_3 0x00000003
#define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff
#define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0
static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
{
return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
}
#define REG_CP_SET_BIN_DATA5_4 0x00000004
#define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff
#define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0
static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
{
return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
}
#define REG_CP_REG_TO_MEM_0 0x00000000
#define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff
#define CP_REG_TO_MEM_0_REG__SHIFT 0
......@@ -594,6 +732,128 @@ static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
}
#define REG_CP_MEM_TO_MEM_0 0x00000000
#define CP_MEM_TO_MEM_0_NEG_A 0x00000001
#define CP_MEM_TO_MEM_0_NEG_B 0x00000002
#define CP_MEM_TO_MEM_0_NEG_C 0x00000004
#define CP_MEM_TO_MEM_0_DOUBLE 0x20000000
#define REG_CP_COND_WRITE_0 0x00000000
#define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007
#define CP_COND_WRITE_0_FUNCTION__SHIFT 0
static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
{
return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
}
#define CP_COND_WRITE_0_POLL_MEMORY 0x00000010
#define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100
#define REG_CP_COND_WRITE_1 0x00000001
#define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff
#define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0
static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
{
return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
}
#define REG_CP_COND_WRITE_2 0x00000002
#define CP_COND_WRITE_2_REF__MASK 0xffffffff
#define CP_COND_WRITE_2_REF__SHIFT 0
static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
{
return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
}
#define REG_CP_COND_WRITE_3 0x00000003
#define CP_COND_WRITE_3_MASK__MASK 0xffffffff
#define CP_COND_WRITE_3_MASK__SHIFT 0
static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
{
return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
}
#define REG_CP_COND_WRITE_4 0x00000004
#define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff
#define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0
static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
{
return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
}
#define REG_CP_COND_WRITE_5 0x00000005
#define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff
#define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0
static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
{
return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
}
#define REG_CP_COND_WRITE5_0 0x00000000
#define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007
#define CP_COND_WRITE5_0_FUNCTION__SHIFT 0
static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
{
return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
}
#define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010
#define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100
#define REG_CP_COND_WRITE5_1 0x00000001
#define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff
#define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0
static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
{
return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
}
#define REG_CP_COND_WRITE5_2 0x00000002
#define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff
#define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0
static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
{
return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
}
#define REG_CP_COND_WRITE5_3 0x00000003
#define CP_COND_WRITE5_3_REF__MASK 0xffffffff
#define CP_COND_WRITE5_3_REF__SHIFT 0
static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
{
return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
}
#define REG_CP_COND_WRITE5_4 0x00000004
#define CP_COND_WRITE5_4_MASK__MASK 0xffffffff
#define CP_COND_WRITE5_4_MASK__SHIFT 0
static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
{
return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
}
#define REG_CP_COND_WRITE5_5 0x00000005
#define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff
#define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0
static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
{
return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
}
#define REG_CP_COND_WRITE5_6 0x00000006
#define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff
#define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0
static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
{
return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
}
#define REG_CP_COND_WRITE5_7 0x00000007
#define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff
#define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0
static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
{
return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
}
#define REG_CP_DISPATCH_COMPUTE_0 0x00000000
#define REG_CP_DISPATCH_COMPUTE_1 0x00000001
......@@ -645,6 +905,7 @@ static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
}
#define REG_CP_SET_RENDER_MODE_3 0x00000003
#define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008
#define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
#define REG_CP_SET_RENDER_MODE_4 0x00000004
......@@ -673,6 +934,50 @@ static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
}
#define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000
#define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff
#define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0
static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)
{
return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK;
}
#define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001
#define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff
#define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0
static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
{
return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK;
}
#define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002
#define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003
#define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004
#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK 0xffffffff
#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT 0
static inline uint32_t CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(uint32_t val)
{
return ((val) << CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK;
}
#define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005
#define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff
#define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0
static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)
{
return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK;
}
#define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006
#define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff
#define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0
static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
{
return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK;
}
#define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
#define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
......@@ -698,6 +1003,7 @@ static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
{
return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
}
#define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000
#define REG_CP_EVENT_WRITE_1 0x00000001
#define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
......@@ -781,5 +1087,31 @@ static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
}
#define REG_CP_EXEC_CS_0 0x00000000
#define REG_CP_EXEC_CS_1 0x00000001
#define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff
#define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0
static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)
{
return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;
}
#define REG_CP_EXEC_CS_2 0x00000002
#define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff
#define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0
static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)
{
return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;
}
#define REG_CP_EXEC_CS_3 0x00000003
#define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff
#define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0
static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
{
return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
}
#endif /* ADRENO_PM4_XML */
drivers/gpu/drm/msm/dsi/dsi.xml.h
View file @ 52260ae4
......@@ -8,8 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-01-11 05:19:19)
- /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-05-09 06:32:54)
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
Copyright (C) 2013-2017 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
......
drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
View file @ 52260ae4
......@@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
Copyright (C) 2013-2015 by the following authors:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
Copyright (C) 2013-2017 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
......
drivers/gpu/drm/msm/dsi/sfpb.xml.h
View file @ 52260ae4
......@@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
Copyright (C) 2013-2015 by the following authors:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
Copyright (C) 2013-2017 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
......
drivers/gpu/drm/msm/edp/edp.xml.h
View file @ 52260ae4
......@@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
Copyright (C) 2013-2015 by the following authors:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
Copyright (C) 2013-2017 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
......
drivers/gpu/drm/msm/hdmi/hdmi.xml.h
View file @ 52260ae4
......@@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
Copyright (C) 2013-2016 by the following authors:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
Copyright (C) 2013-2017 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
......@@ -111,6 +111,32 @@ static inline uint32_t HDMI_ACR_PKT_CTRL_N_MULTIPLIER(uint32_t val)
#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_SOURCE 0x00000040
#define HDMI_INFOFRAME_CTRL0_AUDIO_INFO_UPDATE 0x00000080
#define REG_HDMI_INFOFRAME_CTRL1 0x00000030
#define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK 0x0000003f
#define HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT 0
static inline uint32_t HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(uint32_t val)
{
return ((val) << HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK;
}
#define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK 0x00003f00
#define HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT 8
static inline uint32_t HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE(uint32_t val)
{
return ((val) << HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_AUDIO_INFO_LINE__MASK;
}
#define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK 0x003f0000
#define HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT 16
static inline uint32_t HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE(uint32_t val)
{
return ((val) << HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_MPEG_INFO_LINE__MASK;
}
#define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK 0x3f000000
#define HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT 24
static inline uint32_t HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE(uint32_t val)
{
return ((val) << HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__SHIFT) & HDMI_INFOFRAME_CTRL1_VENSPEC_INFO_LINE__MASK;
}
#define REG_HDMI_GEN_PKT_CTRL 0x00000034
#define HDMI_GEN_PKT_CTRL_GENERIC0_SEND 0x00000001
#define HDMI_GEN_PKT_CTRL_GENERIC0_CONT 0x00000002
......@@ -463,7 +489,7 @@ static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val)
#define REG_HDMI_CEC_RD_FILTER 0x000002b0
#define REG_HDMI_ACTIVE_HSYNC 0x000002b4
#define HDMI_ACTIVE_HSYNC_START__MASK 0x00000fff
#define HDMI_ACTIVE_HSYNC_START__MASK 0x00001fff
#define HDMI_ACTIVE_HSYNC_START__SHIFT 0
static inline uint32_t HDMI_ACTIVE_HSYNC_START(uint32_t val)
{
......@@ -477,13 +503,13 @@ static inline uint32_t HDMI_ACTIVE_HSYNC_END(uint32_t val)
}
#define REG_HDMI_ACTIVE_VSYNC 0x000002b8
#define HDMI_ACTIVE_VSYNC_START__MASK 0x00000fff
#define HDMI_ACTIVE_VSYNC_START__MASK 0x00001fff
#define HDMI_ACTIVE_VSYNC_START__SHIFT 0
static inline uint32_t HDMI_ACTIVE_VSYNC_START(uint32_t val)
{
return ((val) << HDMI_ACTIVE_VSYNC_START__SHIFT) & HDMI_ACTIVE_VSYNC_START__MASK;
}
#define HDMI_ACTIVE_VSYNC_END__MASK 0x0fff0000
#define HDMI_ACTIVE_VSYNC_END__MASK 0x1fff0000
#define HDMI_ACTIVE_VSYNC_END__SHIFT 16
static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val)
{
......@@ -491,13 +517,13 @@ static inline uint32_t HDMI_ACTIVE_VSYNC_END(uint32_t val)
}
#define REG_HDMI_VSYNC_ACTIVE_F2 0x000002bc
#define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00000fff
#define HDMI_VSYNC_ACTIVE_F2_START__MASK 0x00001fff
#define HDMI_VSYNC_ACTIVE_F2_START__SHIFT 0
static inline uint32_t HDMI_VSYNC_ACTIVE_F2_START(uint32_t val)
{
return ((val) << HDMI_VSYNC_ACTIVE_F2_START__SHIFT) & HDMI_VSYNC_ACTIVE_F2_START__MASK;
}
#define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x0fff0000
#define HDMI_VSYNC_ACTIVE_F2_END__MASK 0x1fff0000
#define HDMI_VSYNC_ACTIVE_F2_END__SHIFT 16
static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val)
{
......@@ -505,13 +531,13 @@ static inline uint32_t HDMI_VSYNC_ACTIVE_F2_END(uint32_t val)
}
#define REG_HDMI_TOTAL 0x000002c0
#define HDMI_TOTAL_H_TOTAL__MASK 0x00000fff
#define HDMI_TOTAL_H_TOTAL__MASK 0x00001fff
#define HDMI_TOTAL_H_TOTAL__SHIFT 0
static inline uint32_t HDMI_TOTAL_H_TOTAL(uint32_t val)
{
return ((val) << HDMI_TOTAL_H_TOTAL__SHIFT) & HDMI_TOTAL_H_TOTAL__MASK;
}
#define HDMI_TOTAL_V_TOTAL__MASK 0x0fff0000
#define HDMI_TOTAL_V_TOTAL__MASK 0x1fff0000
#define HDMI_TOTAL_V_TOTAL__SHIFT 16
static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val)
{
......@@ -519,7 +545,7 @@ static inline uint32_t HDMI_TOTAL_V_TOTAL(uint32_t val)
}
#define REG_HDMI_VSYNC_TOTAL_F2 0x000002c4
#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00000fff
#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__MASK 0x00001fff
#define HDMI_VSYNC_TOTAL_F2_V_TOTAL__SHIFT 0
static inline uint32_t HDMI_VSYNC_TOTAL_F2_V_TOTAL(uint32_t val)
{
......
drivers/gpu/drm/msm/hdmi/qfprom.xml.h
View file @ 52260ae4
......@@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
Copyright (C) 2013-2015 by the following authors:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
Copyright (C) 2013-2017 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
......
drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
View file @ 52260ae4
......@@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
Copyright (C) 2013-2015 by the following authors:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
Copyright (C) 2013-2017 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
......
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
View file @ 52260ae4
......@@ -8,9 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /local/mnt/workspace/source_trees/envytools/rnndb/../rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-01-11 05:19:19)
- /local/mnt/workspace/source_trees/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-05-09 06:32:54)
- /local/mnt/workspace/source_trees/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2016-01-07 08:45:55)
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
Copyright (C) 2013-2017 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
......
drivers/gpu/drm/msm/mdp/mdp_common.xml.h
View file @ 52260ae4
......@@ -8,19 +8,19 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2015-09-18 12:07:28)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 36965 bytes, from 2016-11-26 23:01:08)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 27887 bytes, from 2015-10-22 16:34:52)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2015-10-22 16:35:02)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2015-05-20 20:03:14)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2015-05-20 20:03:07)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41472 bytes, from 2016-01-22 18:18:18)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-20 20:03:14)
Copyright (C) 2013-2015 by the following authors:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 33004 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2017-05-17 13:21:27)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2017-06-16 12:32:42)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2017-05-17 13:21:27)
Copyright (C) 2013-2017 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
......
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