Commit 65578d0d authored by Gustavo Sousa's avatar Gustavo Sousa Committed by Lucas De Marchi

drm/i915/xe2lpd: Add fake PCH

Xe2_LPD doesn't have south display engine on a PCH, it's actually
on the SoC die (while north display engine is on compute die). As
such it makes no sense to go through the PCI devices looking for
an ISA bridge. The approach used by BXT/GLK can't be used here since
leaving it with PCH_NONE would mean taking the wrong code paths.

For the places we currently use a PCH check, it's enough for now to just
check the north display version. Use that to define a fake PCH to be
used across the driver. Eventually these PCH checks may need to be
re-designed as this is already the third platform using/needing a
fake PCH.

v2: Match on display IP version rather than on platform (Matt Roper)
v3: Extend and clarify commit message (Matt Roper / Ville)
Signed-off-by: default avatarGustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230919192128.2045154-6-lucas.demarchi@intel.com
parent 8dde2e68
...@@ -222,7 +222,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv) ...@@ -222,7 +222,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
* South display engine on the same PCI device: just assign the fake * South display engine on the same PCI device: just assign the fake
* PCH. * PCH.
*/ */
if (IS_DG2(dev_priv)) { if (DISPLAY_VER(dev_priv) >= 20) {
dev_priv->pch_type = PCH_LNL;
return;
} else if (IS_DG2(dev_priv)) {
dev_priv->pch_type = PCH_DG2; dev_priv->pch_type = PCH_DG2;
return; return;
} else if (IS_DG1(dev_priv)) { } else if (IS_DG1(dev_priv)) {
......
...@@ -30,6 +30,7 @@ enum intel_pch { ...@@ -30,6 +30,7 @@ enum intel_pch {
/* Fake PCHs, functionality handled on the same PCI dev */ /* Fake PCHs, functionality handled on the same PCI dev */
PCH_DG1 = 1024, PCH_DG1 = 1024,
PCH_DG2, PCH_DG2,
PCH_LNL,
}; };
#define INTEL_PCH_DEVICE_ID_MASK 0xff80 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
...@@ -66,6 +67,7 @@ enum intel_pch { ...@@ -66,6 +67,7 @@ enum intel_pch {
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
#define HAS_PCH_LNL(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LNL)
#define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP) #define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP)
#define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2) #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP) #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment