Commit 6f871f0d authored by Bjorn Andersson's avatar Bjorn Andersson

Merge branch '20240202-x1e80100-clock-controllers-v4-5-7fb08c861c7c@linaro.org' into arm64-for-6.9

Merge the X1E clock binding topic branch, to gain access to the many
clock defines.
parents f9491ad2 7180f368
......@@ -17,6 +17,7 @@ description: |
include/dt-bindings/clock/qcom,sm8450-camcc.h
include/dt-bindings/clock/qcom,sm8550-camcc.h
include/dt-bindings/clock/qcom,sc8280xp-camcc.h
include/dt-bindings/clock/qcom,x1e80100-camcc.h
allOf:
- $ref: qcom,gcc.yaml#
......@@ -27,6 +28,7 @@ properties:
- qcom,sc8280xp-camcc
- qcom,sm8450-camcc
- qcom,sm8550-camcc
- qcom,x1e80100-camcc
clocks:
items:
......
......@@ -18,6 +18,7 @@ description: |
include/dt-bindings/clock/qcom,sm8550-gpucc.h
include/dt-bindings/reset/qcom,sm8450-gpucc.h
include/dt-bindings/reset/qcom,sm8650-gpucc.h
include/dt-bindings/reset/qcom,x1e80100-gpucc.h
properties:
compatible:
......@@ -25,6 +26,7 @@ properties:
- qcom,sm8450-gpucc
- qcom,sm8550-gpucc
- qcom,sm8650-gpucc
- qcom,x1e80100-gpucc
clocks:
items:
......
......@@ -14,12 +14,17 @@ description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8550.
See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h
See also:
- include/dt-bindings/clock/qcom,sm8550-dispcc.h
- include/dt-bindings/clock/qcom,sm8650-dispcc.h
- include/dt-bindings/clock/qcom,x1e80100-dispcc.h
properties:
compatible:
enum:
- qcom,sm8550-dispcc
- qcom,sm8650-dispcc
- qcom,x1e80100-dispcc
clocks:
items:
......
......@@ -23,6 +23,7 @@ properties:
- enum:
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
- qcom,x1e80100-tcsr
- const: syscon
clocks:
......
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,sm8650-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller for SM8650
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Neil Armstrong <neil.armstrong@linaro.org>
description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8650.
See also:: include/dt-bindings/clock/qcom,sm8650-dispcc.h
properties:
compatible:
enum:
- qcom,sm8650-dispcc
clocks:
items:
- description: Board XO source
- description: Board Always On XO source
- description: Display's AHB clock
- description: sleep clock
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Byte clock from DSI PHY1
- description: Pixel clock from DSI PHY1
- description: Link clock from DP PHY0
- description: VCO DIV clock from DP PHY0
- description: Link clock from DP PHY1
- description: VCO DIV clock from DP PHY1
- description: Link clock from DP PHY2
- description: VCO DIV clock from DP PHY2
- description: Link clock from DP PHY3
- description: VCO DIV clock from DP PHY3
'#clock-cells':
const: 1
'#reset-cells':
const: 1
'#power-domain-cells':
const: 1
reg:
maxItems: 1
power-domains:
description:
A phandle and PM domain specifier for the MMCX power domain.
maxItems: 1
required-opps:
description:
A phandle to an OPP node describing required MMCX performance point.
maxItems: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
- '#reset-cells'
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm8650-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@af00000 {
compatible = "qcom,sm8650-dispcc";
reg = <0x0af00000 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&gcc GCC_DISP_AHB_CLK>,
<&sleep_clk>,
<&dsi0_phy 0>,
<&dsi0_phy 1>,
<&dsi1_phy 0>,
<&dsi1_phy 1>,
<&dp0_phy 0>,
<&dp0_phy 1>,
<&dp1_phy 0>,
<&dp1_phy 1>,
<&dp2_phy 0>,
<&dp2_phy 1>,
<&dp3_phy 0>,
<&dp3_phy 1>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_X1E80100_H
#define _DT_BINDINGS_CLK_QCOM_CAM_CC_X1E80100_H
/* CAM_CC clocks */
#define CAM_CC_BPS_AHB_CLK 0
#define CAM_CC_BPS_CLK 1
#define CAM_CC_BPS_CLK_SRC 2
#define CAM_CC_BPS_FAST_AHB_CLK 3
#define CAM_CC_CAMNOC_AXI_NRT_CLK 4
#define CAM_CC_CAMNOC_AXI_RT_CLK 5
#define CAM_CC_CAMNOC_AXI_RT_CLK_SRC 6
#define CAM_CC_CAMNOC_DCD_XO_CLK 7
#define CAM_CC_CAMNOC_XO_CLK 8
#define CAM_CC_CCI_0_CLK 9
#define CAM_CC_CCI_0_CLK_SRC 10
#define CAM_CC_CCI_1_CLK 11
#define CAM_CC_CCI_1_CLK_SRC 12
#define CAM_CC_CORE_AHB_CLK 13
#define CAM_CC_CPAS_AHB_CLK 14
#define CAM_CC_CPAS_BPS_CLK 15
#define CAM_CC_CPAS_FAST_AHB_CLK 16
#define CAM_CC_CPAS_IFE_0_CLK 17
#define CAM_CC_CPAS_IFE_1_CLK 18
#define CAM_CC_CPAS_IFE_LITE_CLK 19
#define CAM_CC_CPAS_IPE_NPS_CLK 20
#define CAM_CC_CPAS_SFE_0_CLK 21
#define CAM_CC_CPHY_RX_CLK_SRC 22
#define CAM_CC_CSI0PHYTIMER_CLK 23
#define CAM_CC_CSI0PHYTIMER_CLK_SRC 24
#define CAM_CC_CSI1PHYTIMER_CLK 25
#define CAM_CC_CSI1PHYTIMER_CLK_SRC 26
#define CAM_CC_CSI2PHYTIMER_CLK 27
#define CAM_CC_CSI2PHYTIMER_CLK_SRC 28
#define CAM_CC_CSI3PHYTIMER_CLK 29
#define CAM_CC_CSI3PHYTIMER_CLK_SRC 30
#define CAM_CC_CSI4PHYTIMER_CLK 31
#define CAM_CC_CSI4PHYTIMER_CLK_SRC 32
#define CAM_CC_CSI5PHYTIMER_CLK 33
#define CAM_CC_CSI5PHYTIMER_CLK_SRC 34
#define CAM_CC_CSID_CLK 35
#define CAM_CC_CSID_CLK_SRC 36
#define CAM_CC_CSID_CSIPHY_RX_CLK 37
#define CAM_CC_CSIPHY0_CLK 38
#define CAM_CC_CSIPHY1_CLK 39
#define CAM_CC_CSIPHY2_CLK 40
#define CAM_CC_CSIPHY3_CLK 41
#define CAM_CC_CSIPHY4_CLK 42
#define CAM_CC_CSIPHY5_CLK 43
#define CAM_CC_FAST_AHB_CLK_SRC 44
#define CAM_CC_GDSC_CLK 45
#define CAM_CC_ICP_AHB_CLK 46
#define CAM_CC_ICP_CLK 47
#define CAM_CC_ICP_CLK_SRC 48
#define CAM_CC_IFE_0_CLK 49
#define CAM_CC_IFE_0_CLK_SRC 50
#define CAM_CC_IFE_0_DSP_CLK 51
#define CAM_CC_IFE_0_FAST_AHB_CLK 52
#define CAM_CC_IFE_1_CLK 53
#define CAM_CC_IFE_1_CLK_SRC 54
#define CAM_CC_IFE_1_DSP_CLK 55
#define CAM_CC_IFE_1_FAST_AHB_CLK 56
#define CAM_CC_IFE_LITE_AHB_CLK 57
#define CAM_CC_IFE_LITE_CLK 58
#define CAM_CC_IFE_LITE_CLK_SRC 59
#define CAM_CC_IFE_LITE_CPHY_RX_CLK 60
#define CAM_CC_IFE_LITE_CSID_CLK 61
#define CAM_CC_IFE_LITE_CSID_CLK_SRC 62
#define CAM_CC_IPE_NPS_AHB_CLK 63
#define CAM_CC_IPE_NPS_CLK 64
#define CAM_CC_IPE_NPS_CLK_SRC 65
#define CAM_CC_IPE_NPS_FAST_AHB_CLK 66
#define CAM_CC_IPE_PPS_CLK 67
#define CAM_CC_IPE_PPS_FAST_AHB_CLK 68
#define CAM_CC_JPEG_CLK 69
#define CAM_CC_JPEG_CLK_SRC 70
#define CAM_CC_MCLK0_CLK 71
#define CAM_CC_MCLK0_CLK_SRC 72
#define CAM_CC_MCLK1_CLK 73
#define CAM_CC_MCLK1_CLK_SRC 74
#define CAM_CC_MCLK2_CLK 75
#define CAM_CC_MCLK2_CLK_SRC 76
#define CAM_CC_MCLK3_CLK 77
#define CAM_CC_MCLK3_CLK_SRC 78
#define CAM_CC_MCLK4_CLK 79
#define CAM_CC_MCLK4_CLK_SRC 80
#define CAM_CC_MCLK5_CLK 81
#define CAM_CC_MCLK5_CLK_SRC 82
#define CAM_CC_MCLK6_CLK 83
#define CAM_CC_MCLK6_CLK_SRC 84
#define CAM_CC_MCLK7_CLK 85
#define CAM_CC_MCLK7_CLK_SRC 86
#define CAM_CC_PLL0 87
#define CAM_CC_PLL0_OUT_EVEN 88
#define CAM_CC_PLL0_OUT_ODD 89
#define CAM_CC_PLL1 90
#define CAM_CC_PLL1_OUT_EVEN 91
#define CAM_CC_PLL2 92
#define CAM_CC_PLL3 93
#define CAM_CC_PLL3_OUT_EVEN 94
#define CAM_CC_PLL4 95
#define CAM_CC_PLL4_OUT_EVEN 96
#define CAM_CC_PLL6 97
#define CAM_CC_PLL6_OUT_EVEN 98
#define CAM_CC_PLL8 99
#define CAM_CC_PLL8_OUT_EVEN 100
#define CAM_CC_SFE_0_CLK 101
#define CAM_CC_SFE_0_CLK_SRC 102
#define CAM_CC_SFE_0_FAST_AHB_CLK 103
#define CAM_CC_SLEEP_CLK 104
#define CAM_CC_SLEEP_CLK_SRC 105
#define CAM_CC_SLOW_AHB_CLK_SRC 106
#define CAM_CC_XO_CLK_SRC 107
/* CAM_CC power domains */
#define CAM_CC_BPS_GDSC 0
#define CAM_CC_IFE_0_GDSC 1
#define CAM_CC_IFE_1_GDSC 2
#define CAM_CC_IPE_0_GDSC 3
#define CAM_CC_SFE_0_GDSC 4
#define CAM_CC_TITAN_TOP_GDSC 5
/* CAM_CC resets */
#define CAM_CC_BPS_BCR 0
#define CAM_CC_ICP_BCR 1
#define CAM_CC_IFE_0_BCR 2
#define CAM_CC_IFE_1_BCR 3
#define CAM_CC_IPE_0_BCR 4
#define CAM_CC_SFE_0_BCR 5
#endif
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H
#define _DT_BINDINGS_CLK_QCOM_X1E80100_DISP_CC_H
/* DISP_CC clocks */
#define DISP_CC_MDSS_ACCU_CLK 0
#define DISP_CC_MDSS_AHB1_CLK 1
#define DISP_CC_MDSS_AHB_CLK 2
#define DISP_CC_MDSS_AHB_CLK_SRC 3
#define DISP_CC_MDSS_BYTE0_CLK 4
#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
#define DISP_CC_MDSS_BYTE1_CLK 8
#define DISP_CC_MDSS_BYTE1_CLK_SRC 9
#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 10
#define DISP_CC_MDSS_BYTE1_INTF_CLK 11
#define DISP_CC_MDSS_DPTX0_AUX_CLK 12
#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 13
#define DISP_CC_MDSS_DPTX0_LINK_CLK 14
#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 15
#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 16
#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 17
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 18
#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 19
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 20
#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 21
#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 22
#define DISP_CC_MDSS_DPTX1_AUX_CLK 23
#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 24
#define DISP_CC_MDSS_DPTX1_LINK_CLK 25
#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 26
#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 27
#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 28
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 29
#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 30
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 31
#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 32
#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 33
#define DISP_CC_MDSS_DPTX2_AUX_CLK 34
#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 35
#define DISP_CC_MDSS_DPTX2_LINK_CLK 36
#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 37
#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 38
#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 39
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 40
#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 41
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 42
#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 43
#define DISP_CC_MDSS_DPTX2_USB_ROUTER_LINK_INTF_CLK 44
#define DISP_CC_MDSS_DPTX3_AUX_CLK 45
#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 46
#define DISP_CC_MDSS_DPTX3_LINK_CLK 47
#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 48
#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 49
#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 50
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 51
#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 52
#define DISP_CC_MDSS_ESC0_CLK 53
#define DISP_CC_MDSS_ESC0_CLK_SRC 54
#define DISP_CC_MDSS_ESC1_CLK 55
#define DISP_CC_MDSS_ESC1_CLK_SRC 56
#define DISP_CC_MDSS_MDP1_CLK 57
#define DISP_CC_MDSS_MDP_CLK 58
#define DISP_CC_MDSS_MDP_CLK_SRC 59
#define DISP_CC_MDSS_MDP_LUT1_CLK 60
#define DISP_CC_MDSS_MDP_LUT_CLK 61
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 62
#define DISP_CC_MDSS_PCLK0_CLK 63
#define DISP_CC_MDSS_PCLK0_CLK_SRC 64
#define DISP_CC_MDSS_PCLK1_CLK 65
#define DISP_CC_MDSS_PCLK1_CLK_SRC 66
#define DISP_CC_MDSS_RSCC_AHB_CLK 67
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 68
#define DISP_CC_MDSS_VSYNC1_CLK 69
#define DISP_CC_MDSS_VSYNC_CLK 70
#define DISP_CC_MDSS_VSYNC_CLK_SRC 71
#define DISP_CC_PLL0 72
#define DISP_CC_PLL1 73
#define DISP_CC_SLEEP_CLK 74
#define DISP_CC_SLEEP_CLK_SRC 75
#define DISP_CC_XO_CLK 76
#define DISP_CC_XO_CLK_SRC 77
/* DISP_CC resets */
#define DISP_CC_MDSS_CORE_BCR 0
#define DISP_CC_MDSS_CORE_INT2_BCR 1
#define DISP_CC_MDSS_RSCC_BCR 2
/* DISP_CC GDSCR */
#define MDSS_GDSC 0
#define MDSS_INT2_GDSC 1
#endif
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H
#define _DT_BINDINGS_CLK_QCOM_X1E80100_GPU_CC_H
/* GPU_CC clocks */
#define GPU_CC_AHB_CLK 0
#define GPU_CC_CB_CLK 1
#define GPU_CC_CRC_AHB_CLK 2
#define GPU_CC_CX_FF_CLK 3
#define GPU_CC_CX_GMU_CLK 4
#define GPU_CC_CXO_AON_CLK 5
#define GPU_CC_CXO_CLK 6
#define GPU_CC_DEMET_CLK 7
#define GPU_CC_DEMET_DIV_CLK_SRC 8
#define GPU_CC_FF_CLK_SRC 9
#define GPU_CC_FREQ_MEASURE_CLK 10
#define GPU_CC_GMU_CLK_SRC 11
#define GPU_CC_GX_GMU_CLK 12
#define GPU_CC_GX_VSENSE_CLK 13
#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 14
#define GPU_CC_HUB_AON_CLK 15
#define GPU_CC_HUB_CLK_SRC 16
#define GPU_CC_HUB_CX_INT_CLK 17
#define GPU_CC_MEMNOC_GFX_CLK 18
#define GPU_CC_MND1X_0_GFX3D_CLK 19
#define GPU_CC_MND1X_1_GFX3D_CLK 20
#define GPU_CC_PLL0 21
#define GPU_CC_PLL1 22
#define GPU_CC_SLEEP_CLK 23
#define GPU_CC_XO_CLK_SRC 24
#define GPU_CC_XO_DIV_CLK_SRC 25
/* GDSCs */
#define GPU_CX_GDSC 0
#define GPU_GX_GDSC 1
#endif
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Linaro Limited
*/
#ifndef _DT_BINDINGS_CLK_QCOM_X1E80100_TCSR_CC_H
#define _DT_BINDINGS_CLK_QCOM_X1E80100_TCSR_CC_H
/* TCSR CC clocks */
#define TCSR_PCIE_2L_4_CLKREF_EN 0
#define TCSR_PCIE_2L_5_CLKREF_EN 1
#define TCSR_PCIE_8L_CLKREF_EN 2
#define TCSR_USB3_MP0_CLKREF_EN 3
#define TCSR_USB3_MP1_CLKREF_EN 4
#define TCSR_USB2_1_CLKREF_EN 5
#define TCSR_UFS_PHY_CLKREF_EN 6
#define TCSR_USB4_1_CLKREF_EN 7
#define TCSR_USB4_2_CLKREF_EN 8
#define TCSR_USB2_2_CLKREF_EN 9
#define TCSR_PCIE_4L_CLKREF_EN 10
#define TCSR_EDP_CLKREF_EN 11
#endif
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H
#define _DT_BINDINGS_RESET_QCOM_X1E80100_GPU_CC_H
#define GPUCC_GPU_CC_ACD_BCR 0
#define GPUCC_GPU_CC_CB_BCR 1
#define GPUCC_GPU_CC_CX_BCR 2
#define GPUCC_GPU_CC_FAST_HUB_BCR 3
#define GPUCC_GPU_CC_FF_BCR 4
#define GPUCC_GPU_CC_GFX3D_AON_BCR 5
#define GPUCC_GPU_CC_GMU_BCR 6
#define GPUCC_GPU_CC_GX_BCR 7
#define GPUCC_GPU_CC_XO_BCR 8
#endif
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