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Commit 6fa91f64 authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
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perf vendor events intel: Refresh bonnell events 

Update the bonnell events using the new tooling from:

  https://github.com/intel/perfmon

The events are unchanged but unused json values are removed and
implicit umasks of 0 are dropped. This increases consistency across
the json files.
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Acked-by: default avatarKan Liang <kan.liang@linux.intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20221215064755.1620246-5-irogers@google.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent a5abef62
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Showing with 18 additions and 306 deletions
tools/perf/pmu-events/arch/x86/bonnell/floating-point.json
View file @ 6fa91f64
[ [
{ {
"BriefDescription": "Floating point assists for retired operations.", "BriefDescription": "Floating point assists for retired operations.",
"Counter": "0,1",
"EventCode": "0x11", "EventCode": "0x11",
"EventName": "FP_ASSIST.AR", "EventName": "FP_ASSIST.AR",
"SampleAfterValue": "10000", "SampleAfterValue": "10000",
...@@ -9,7 +8,6 @@ ...@@ -9,7 +8,6 @@
}, },
{ {
"BriefDescription": "Floating point assists.", "BriefDescription": "Floating point assists.",
"Counter": "0,1",
"EventCode": "0x11", "EventCode": "0x11",
"EventName": "FP_ASSIST.S", "EventName": "FP_ASSIST.S",
"SampleAfterValue": "10000", "SampleAfterValue": "10000",
...@@ -17,15 +15,12 @@ ...@@ -17,15 +15,12 @@
}, },
{ {
"BriefDescription": "SIMD assists invoked.", "BriefDescription": "SIMD assists invoked.",
"Counter": "0,1",
"EventCode": "0xCD", "EventCode": "0xCD",
"EventName": "SIMD_ASSIST", "EventName": "SIMD_ASSIST",
"SampleAfterValue": "100000", "SampleAfterValue": "100000"
"UMask": "0x0"
}, },
{ {
"BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.", "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.",
"Counter": "0,1",
"EventCode": "0xCA", "EventCode": "0xCA",
"EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE", "EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -33,7 +28,6 @@ ...@@ -33,7 +28,6 @@
}, },
{ {
"BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.", "BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
"Counter": "0,1",
"EventCode": "0xCA", "EventCode": "0xCA",
"EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE", "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -41,7 +35,6 @@ ...@@ -41,7 +35,6 @@
}, },
{ {
"BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.", "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.",
"Counter": "0,1",
"EventCode": "0xCA", "EventCode": "0xCA",
"EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE", "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -49,15 +42,12 @@ ...@@ -49,15 +42,12 @@
}, },
{ {
"BriefDescription": "SIMD Instructions retired.", "BriefDescription": "SIMD Instructions retired.",
"Counter": "0,1",
"EventCode": "0xCE", "EventCode": "0xCE",
"EventName": "SIMD_INSTR_RETIRED", "EventName": "SIMD_INSTR_RETIRED",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000"
"UMask": "0x0"
}, },
{ {
"BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions.", "BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions.",
"Counter": "0,1",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "SIMD_INST_RETIRED.PACKED_SINGLE", "EventName": "SIMD_INST_RETIRED.PACKED_SINGLE",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -65,7 +55,6 @@ ...@@ -65,7 +55,6 @@
}, },
{ {
"BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.", "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
"Counter": "0,1",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE", "EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -73,7 +62,6 @@ ...@@ -73,7 +62,6 @@
}, },
{ {
"BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions.", "BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions.",
"Counter": "0,1",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE", "EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -81,7 +69,6 @@ ...@@ -81,7 +69,6 @@
}, },
{ {
"BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.", "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.",
"Counter": "0,1",
"EventCode": "0xC7", "EventCode": "0xC7",
"EventName": "SIMD_INST_RETIRED.VECTOR", "EventName": "SIMD_INST_RETIRED.VECTOR",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -89,15 +76,12 @@ ...@@ -89,15 +76,12 @@
}, },
{ {
"BriefDescription": "Saturated arithmetic instructions retired.", "BriefDescription": "Saturated arithmetic instructions retired.",
"Counter": "0,1",
"EventCode": "0xCF", "EventCode": "0xCF",
"EventName": "SIMD_SAT_INSTR_RETIRED", "EventName": "SIMD_SAT_INSTR_RETIRED",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000"
"UMask": "0x0"
}, },
{ {
"BriefDescription": "SIMD saturated arithmetic micro-ops retired.", "BriefDescription": "SIMD saturated arithmetic micro-ops retired.",
"Counter": "0,1",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "SIMD_SAT_UOP_EXEC.AR", "EventName": "SIMD_SAT_UOP_EXEC.AR",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -105,15 +89,12 @@ ...@@ -105,15 +89,12 @@
}, },
{ {
"BriefDescription": "SIMD saturated arithmetic micro-ops executed.", "BriefDescription": "SIMD saturated arithmetic micro-ops executed.",
"Counter": "0,1",
"EventCode": "0xB1", "EventCode": "0xB1",
"EventName": "SIMD_SAT_UOP_EXEC.S", "EventName": "SIMD_SAT_UOP_EXEC.S",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000"
"UMask": "0x0"
}, },
{ {
"BriefDescription": "SIMD micro-ops retired (excluding stores).", "BriefDescription": "SIMD micro-ops retired (excluding stores).",
"Counter": "0,1",
"EventCode": "0xB0", "EventCode": "0xB0",
"EventName": "SIMD_UOPS_EXEC.AR", "EventName": "SIMD_UOPS_EXEC.AR",
"PEBS": "2", "PEBS": "2",
...@@ -122,15 +103,12 @@ ...@@ -122,15 +103,12 @@
}, },
{ {
"BriefDescription": "SIMD micro-ops executed (excluding stores).", "BriefDescription": "SIMD micro-ops executed (excluding stores).",
"Counter": "0,1",
"EventCode": "0xB0", "EventCode": "0xB0",
"EventName": "SIMD_UOPS_EXEC.S", "EventName": "SIMD_UOPS_EXEC.S",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000"
"UMask": "0x0"
}, },
{ {
"BriefDescription": "SIMD packed arithmetic micro-ops retired", "BriefDescription": "SIMD packed arithmetic micro-ops retired",
"Counter": "0,1",
"EventCode": "0xB3", "EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR", "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -138,7 +116,6 @@ ...@@ -138,7 +116,6 @@
}, },
{ {
"BriefDescription": "SIMD packed arithmetic micro-ops executed", "BriefDescription": "SIMD packed arithmetic micro-ops executed",
"Counter": "0,1",
"EventCode": "0xB3", "EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S", "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -146,7 +123,6 @@ ...@@ -146,7 +123,6 @@
}, },
{ {
"BriefDescription": "SIMD packed logical micro-ops retired", "BriefDescription": "SIMD packed logical micro-ops retired",
"Counter": "0,1",
"EventCode": "0xB3", "EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR", "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -154,7 +130,6 @@ ...@@ -154,7 +130,6 @@
}, },
{ {
"BriefDescription": "SIMD packed logical micro-ops executed", "BriefDescription": "SIMD packed logical micro-ops executed",
"Counter": "0,1",
"EventCode": "0xB3", "EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S", "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -162,7 +137,6 @@ ...@@ -162,7 +137,6 @@
}, },
{ {
"BriefDescription": "SIMD packed multiply micro-ops retired", "BriefDescription": "SIMD packed multiply micro-ops retired",
"Counter": "0,1",
"EventCode": "0xB3", "EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR", "EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -170,7 +144,6 @@ ...@@ -170,7 +144,6 @@
}, },
{ {
"BriefDescription": "SIMD packed multiply micro-ops executed", "BriefDescription": "SIMD packed multiply micro-ops executed",
"Counter": "0,1",
"EventCode": "0xB3", "EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.MUL.S", "EventName": "SIMD_UOP_TYPE_EXEC.MUL.S",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -178,7 +151,6 @@ ...@@ -178,7 +151,6 @@
}, },
{ {
"BriefDescription": "SIMD packed micro-ops retired", "BriefDescription": "SIMD packed micro-ops retired",
"Counter": "0,1",
"EventCode": "0xB3", "EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR", "EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -186,7 +158,6 @@ ...@@ -186,7 +158,6 @@
}, },
{ {
"BriefDescription": "SIMD packed micro-ops executed", "BriefDescription": "SIMD packed micro-ops executed",
"Counter": "0,1",
"EventCode": "0xB3", "EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.PACK.S", "EventName": "SIMD_UOP_TYPE_EXEC.PACK.S",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -194,7 +165,6 @@ ...@@ -194,7 +165,6 @@
}, },
{ {
"BriefDescription": "SIMD packed shift micro-ops retired", "BriefDescription": "SIMD packed shift micro-ops retired",
"Counter": "0,1",
"EventCode": "0xB3", "EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR", "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -202,7 +172,6 @@ ...@@ -202,7 +172,6 @@
}, },
{ {
"BriefDescription": "SIMD packed shift micro-ops executed", "BriefDescription": "SIMD packed shift micro-ops executed",
"Counter": "0,1",
"EventCode": "0xB3", "EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S", "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -210,7 +179,6 @@ ...@@ -210,7 +179,6 @@
}, },
{ {
"BriefDescription": "SIMD unpacked micro-ops retired", "BriefDescription": "SIMD unpacked micro-ops retired",
"Counter": "0,1",
"EventCode": "0xB3", "EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR", "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -218,7 +186,6 @@ ...@@ -218,7 +186,6 @@
}, },
{ {
"BriefDescription": "SIMD unpacked micro-ops executed", "BriefDescription": "SIMD unpacked micro-ops executed",
"Counter": "0,1",
"EventCode": "0xB3", "EventCode": "0xB3",
"EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S", "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -226,7 +193,6 @@ ...@@ -226,7 +193,6 @@
}, },
{ {
"BriefDescription": "Floating point computational micro-ops retired.", "BriefDescription": "Floating point computational micro-ops retired.",
"Counter": "0,1",
"EventCode": "0x10", "EventCode": "0x10",
"EventName": "X87_COMP_OPS_EXE.ANY.AR", "EventName": "X87_COMP_OPS_EXE.ANY.AR",
"PEBS": "2", "PEBS": "2",
...@@ -235,7 +201,6 @@ ...@@ -235,7 +201,6 @@
}, },
{ {
"BriefDescription": "Floating point computational micro-ops executed.", "BriefDescription": "Floating point computational micro-ops executed.",
"Counter": "0,1",
"EventCode": "0x10", "EventCode": "0x10",
"EventName": "X87_COMP_OPS_EXE.ANY.S", "EventName": "X87_COMP_OPS_EXE.ANY.S",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -243,7 +208,6 @@ ...@@ -243,7 +208,6 @@
}, },
{ {
"BriefDescription": "FXCH uops retired.", "BriefDescription": "FXCH uops retired.",
"Counter": "0,1",
"EventCode": "0x10", "EventCode": "0x10",
"EventName": "X87_COMP_OPS_EXE.FXCH.AR", "EventName": "X87_COMP_OPS_EXE.FXCH.AR",
"PEBS": "2", "PEBS": "2",
...@@ -252,7 +216,6 @@ ...@@ -252,7 +216,6 @@
}, },
{ {
"BriefDescription": "FXCH uops executed.", "BriefDescription": "FXCH uops executed.",
"Counter": "0,1",
"EventCode": "0x10", "EventCode": "0x10",
"EventName": "X87_COMP_OPS_EXE.FXCH.S", "EventName": "X87_COMP_OPS_EXE.FXCH.S",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
......
tools/perf/pmu-events/arch/x86/bonnell/frontend.json
View file @ 6fa91f64
[ [
{ {
"BriefDescription": "BACLEARS asserted.", "BriefDescription": "BACLEARS asserted.",
"Counter": "0,1",
"EventCode": "0xE6", "EventCode": "0xE6",
"EventName": "BACLEARS.ANY", "EventName": "BACLEARS.ANY",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -9,7 +8,6 @@ ...@@ -9,7 +8,6 @@
}, },
{ {
"BriefDescription": "Cycles during which instruction fetches are stalled.", "BriefDescription": "Cycles during which instruction fetches are stalled.",
"Counter": "0,1",
"EventCode": "0x86", "EventCode": "0x86",
"EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED", "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -17,7 +15,6 @@ ...@@ -17,7 +15,6 @@
}, },
{ {
"BriefDescription": "Decode stall due to IQ full", "BriefDescription": "Decode stall due to IQ full",
"Counter": "0,1",
"EventCode": "0x87", "EventCode": "0x87",
"EventName": "DECODE_STALL.IQ_FULL", "EventName": "DECODE_STALL.IQ_FULL",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -25,7 +22,6 @@ ...@@ -25,7 +22,6 @@
}, },
{ {
"BriefDescription": "Decode stall due to PFB empty", "BriefDescription": "Decode stall due to PFB empty",
"Counter": "0,1",
"EventCode": "0x87", "EventCode": "0x87",
"EventName": "DECODE_STALL.PFB_EMPTY", "EventName": "DECODE_STALL.PFB_EMPTY",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -33,7 +29,6 @@ ...@@ -33,7 +29,6 @@
}, },
{ {
"BriefDescription": "Instruction fetches.", "BriefDescription": "Instruction fetches.",
"Counter": "0,1",
"EventCode": "0x80", "EventCode": "0x80",
"EventName": "ICACHE.ACCESSES", "EventName": "ICACHE.ACCESSES",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -41,7 +36,6 @@ ...@@ -41,7 +36,6 @@
}, },
{ {
"BriefDescription": "Icache hit", "BriefDescription": "Icache hit",
"Counter": "0,1",
"EventCode": "0x80", "EventCode": "0x80",
"EventName": "ICACHE.HIT", "EventName": "ICACHE.HIT",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -49,7 +43,6 @@ ...@@ -49,7 +43,6 @@
}, },
{ {
"BriefDescription": "Icache miss", "BriefDescription": "Icache miss",
"Counter": "0,1",
"EventCode": "0x80", "EventCode": "0x80",
"EventName": "ICACHE.MISSES", "EventName": "ICACHE.MISSES",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -57,7 +50,6 @@ ...@@ -57,7 +50,6 @@
}, },
{ {
"BriefDescription": "All Instructions decoded", "BriefDescription": "All Instructions decoded",
"Counter": "0,1",
"EventCode": "0xAA", "EventCode": "0xAA",
"EventName": "MACRO_INSTS.ALL_DECODED", "EventName": "MACRO_INSTS.ALL_DECODED",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -65,7 +57,6 @@ ...@@ -65,7 +57,6 @@
}, },
{ {
"BriefDescription": "CISC macro instructions decoded", "BriefDescription": "CISC macro instructions decoded",
"Counter": "0,1",
"EventCode": "0xAA", "EventCode": "0xAA",
"EventName": "MACRO_INSTS.CISC_DECODED", "EventName": "MACRO_INSTS.CISC_DECODED",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -73,7 +64,6 @@ ...@@ -73,7 +64,6 @@
}, },
{ {
"BriefDescription": "Non-CISC nacro instructions decoded", "BriefDescription": "Non-CISC nacro instructions decoded",
"Counter": "0,1",
"EventCode": "0xAA", "EventCode": "0xAA",
"EventName": "MACRO_INSTS.NON_CISC_DECODED", "EventName": "MACRO_INSTS.NON_CISC_DECODED",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -81,7 +71,6 @@ ...@@ -81,7 +71,6 @@
}, },
{ {
"BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.", "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
"Counter": "0,1",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0xA9", "EventCode": "0xA9",
"EventName": "UOPS.MS_CYCLES", "EventName": "UOPS.MS_CYCLES",
......
tools/perf/pmu-events/arch/x86/bonnell/memory.json
View file @ 6fa91f64
[ [
{ {
"BriefDescription": "Nonzero segbase 1 bubble", "BriefDescription": "Nonzero segbase 1 bubble",
"Counter": "0,1",
"EventCode": "0x5", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.BUBBLE", "EventName": "MISALIGN_MEM_REF.BUBBLE",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -9,7 +8,6 @@ ...@@ -9,7 +8,6 @@
}, },
{ {
"BriefDescription": "Nonzero segbase load 1 bubble", "BriefDescription": "Nonzero segbase load 1 bubble",
"Counter": "0,1",
"EventCode": "0x5", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.LD_BUBBLE", "EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -17,7 +15,6 @@ ...@@ -17,7 +15,6 @@
}, },
{ {
"BriefDescription": "Load splits", "BriefDescription": "Load splits",
"Counter": "0,1",
"EventCode": "0x5", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.LD_SPLIT", "EventName": "MISALIGN_MEM_REF.LD_SPLIT",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -25,7 +22,6 @@ ...@@ -25,7 +22,6 @@
}, },
{ {
"BriefDescription": "Load splits (At Retirement)", "BriefDescription": "Load splits (At Retirement)",
"Counter": "0,1",
"EventCode": "0x5", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR", "EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -33,7 +29,6 @@ ...@@ -33,7 +29,6 @@
}, },
{ {
"BriefDescription": "Nonzero segbase ld-op-st 1 bubble", "BriefDescription": "Nonzero segbase ld-op-st 1 bubble",
"Counter": "0,1",
"EventCode": "0x5", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.RMW_BUBBLE", "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -41,7 +36,6 @@ ...@@ -41,7 +36,6 @@
}, },
{ {
"BriefDescription": "ld-op-st splits", "BriefDescription": "ld-op-st splits",
"Counter": "0,1",
"EventCode": "0x5", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.RMW_SPLIT", "EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -49,7 +43,6 @@ ...@@ -49,7 +43,6 @@
}, },
{ {
"BriefDescription": "Memory references that cross an 8-byte boundary.", "BriefDescription": "Memory references that cross an 8-byte boundary.",
"Counter": "0,1",
"EventCode": "0x5", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.SPLIT", "EventName": "MISALIGN_MEM_REF.SPLIT",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -57,7 +50,6 @@ ...@@ -57,7 +50,6 @@
}, },
{ {
"BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)", "BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)",
"Counter": "0,1",
"EventCode": "0x5", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.SPLIT.AR", "EventName": "MISALIGN_MEM_REF.SPLIT.AR",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -65,7 +57,6 @@ ...@@ -65,7 +57,6 @@
}, },
{ {
"BriefDescription": "Nonzero segbase store 1 bubble", "BriefDescription": "Nonzero segbase store 1 bubble",
"Counter": "0,1",
"EventCode": "0x5", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.ST_BUBBLE", "EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -73,7 +64,6 @@ ...@@ -73,7 +64,6 @@
}, },
{ {
"BriefDescription": "Store splits", "BriefDescription": "Store splits",
"Counter": "0,1",
"EventCode": "0x5", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.ST_SPLIT", "EventName": "MISALIGN_MEM_REF.ST_SPLIT",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -81,7 +71,6 @@ ...@@ -81,7 +71,6 @@
}, },
{ {
"BriefDescription": "Store splits (Ar Retirement)", "BriefDescription": "Store splits (Ar Retirement)",
"Counter": "0,1",
"EventCode": "0x5", "EventCode": "0x5",
"EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR", "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -89,7 +78,6 @@ ...@@ -89,7 +78,6 @@
}, },
{ {
"BriefDescription": "L1 hardware prefetch request", "BriefDescription": "L1 hardware prefetch request",
"Counter": "0,1",
"EventCode": "0x7", "EventCode": "0x7",
"EventName": "PREFETCH.HW_PREFETCH", "EventName": "PREFETCH.HW_PREFETCH",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -97,7 +85,6 @@ ...@@ -97,7 +85,6 @@
}, },
{ {
"BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed", "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
"Counter": "0,1",
"EventCode": "0x7", "EventCode": "0x7",
"EventName": "PREFETCH.PREFETCHNTA", "EventName": "PREFETCH.PREFETCHNTA",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -105,7 +92,6 @@ ...@@ -105,7 +92,6 @@
}, },
{ {
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.", "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
"Counter": "0,1",
"EventCode": "0x7", "EventCode": "0x7",
"EventName": "PREFETCH.PREFETCHT0", "EventName": "PREFETCH.PREFETCHT0",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -113,7 +99,6 @@ ...@@ -113,7 +99,6 @@
}, },
{ {
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.", "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
"Counter": "0,1",
"EventCode": "0x7", "EventCode": "0x7",
"EventName": "PREFETCH.PREFETCHT1", "EventName": "PREFETCH.PREFETCHT1",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -121,7 +106,6 @@ ...@@ -121,7 +106,6 @@
}, },
{ {
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.", "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
"Counter": "0,1",
"EventCode": "0x7", "EventCode": "0x7",
"EventName": "PREFETCH.PREFETCHT2", "EventName": "PREFETCH.PREFETCHT2",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -129,7 +113,6 @@ ...@@ -129,7 +113,6 @@
}, },
{ {
"BriefDescription": "Any Software prefetch", "BriefDescription": "Any Software prefetch",
"Counter": "0,1",
"EventCode": "0x7", "EventCode": "0x7",
"EventName": "PREFETCH.SOFTWARE_PREFETCH", "EventName": "PREFETCH.SOFTWARE_PREFETCH",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -137,7 +120,6 @@ ...@@ -137,7 +120,6 @@
}, },
{ {
"BriefDescription": "Any Software prefetch", "BriefDescription": "Any Software prefetch",
"Counter": "0,1",
"EventCode": "0x7", "EventCode": "0x7",
"EventName": "PREFETCH.SOFTWARE_PREFETCH.AR", "EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -145,7 +127,6 @@ ...@@ -145,7 +127,6 @@
}, },
{ {
"BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed", "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
"Counter": "0,1",
"EventCode": "0x7", "EventCode": "0x7",
"EventName": "PREFETCH.SW_L2", "EventName": "PREFETCH.SW_L2",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
......
tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json
View file @ 6fa91f64
[ [
{ {
"BriefDescription": "Memory accesses that missed the DTLB.", "BriefDescription": "Memory accesses that missed the DTLB.",
"Counter": "0,1",
"EventCode": "0x8", "EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.DTLB_MISS", "EventName": "DATA_TLB_MISSES.DTLB_MISS",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -9,7 +8,6 @@ ...@@ -9,7 +8,6 @@
}, },
{ {
"BriefDescription": "DTLB misses due to load operations.", "BriefDescription": "DTLB misses due to load operations.",
"Counter": "0,1",
"EventCode": "0x8", "EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.DTLB_MISS_LD", "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -17,7 +15,6 @@ ...@@ -17,7 +15,6 @@
}, },
{ {
"BriefDescription": "DTLB misses due to store operations.", "BriefDescription": "DTLB misses due to store operations.",
"Counter": "0,1",
"EventCode": "0x8", "EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.DTLB_MISS_ST", "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -25,7 +22,6 @@ ...@@ -25,7 +22,6 @@
}, },
{ {
"BriefDescription": "L0 DTLB misses due to load operations.", "BriefDescription": "L0 DTLB misses due to load operations.",
"Counter": "0,1",
"EventCode": "0x8", "EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD", "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -33,7 +29,6 @@ ...@@ -33,7 +29,6 @@
}, },
{ {
"BriefDescription": "L0 DTLB misses due to store operations", "BriefDescription": "L0 DTLB misses due to store operations",
"Counter": "0,1",
"EventCode": "0x8", "EventCode": "0x8",
"EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST", "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -41,7 +36,6 @@ ...@@ -41,7 +36,6 @@
}, },
{ {
"BriefDescription": "ITLB flushes.", "BriefDescription": "ITLB flushes.",
"Counter": "0,1",
"EventCode": "0x82", "EventCode": "0x82",
"EventName": "ITLB.FLUSH", "EventName": "ITLB.FLUSH",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -49,7 +43,6 @@ ...@@ -49,7 +43,6 @@
}, },
{ {
"BriefDescription": "ITLB hits.", "BriefDescription": "ITLB hits.",
"Counter": "0,1",
"EventCode": "0x82", "EventCode": "0x82",
"EventName": "ITLB.HIT", "EventName": "ITLB.HIT",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -57,7 +50,6 @@ ...@@ -57,7 +50,6 @@
}, },
{ {
"BriefDescription": "ITLB misses.", "BriefDescription": "ITLB misses.",
"Counter": "0,1",
"EventCode": "0x82", "EventCode": "0x82",
"EventName": "ITLB.MISSES", "EventName": "ITLB.MISSES",
"PEBS": "2", "PEBS": "2",
...@@ -66,7 +58,6 @@ ...@@ -66,7 +58,6 @@
}, },
{ {
"BriefDescription": "Retired loads that miss the DTLB (precise event).", "BriefDescription": "Retired loads that miss the DTLB (precise event).",
"Counter": "0,1",
"EventCode": "0xCB", "EventCode": "0xCB",
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
"PEBS": "1", "PEBS": "1",
...@@ -75,7 +66,6 @@ ...@@ -75,7 +66,6 @@
}, },
{ {
"BriefDescription": "Duration of page-walks in core cycles", "BriefDescription": "Duration of page-walks in core cycles",
"Counter": "0,1",
"EventCode": "0xC", "EventCode": "0xC",
"EventName": "PAGE_WALKS.CYCLES", "EventName": "PAGE_WALKS.CYCLES",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -83,7 +73,6 @@ ...@@ -83,7 +73,6 @@
}, },
{ {
"BriefDescription": "Duration of D-side only page walks", "BriefDescription": "Duration of D-side only page walks",
"Counter": "0,1",
"EventCode": "0xC", "EventCode": "0xC",
"EventName": "PAGE_WALKS.D_SIDE_CYCLES", "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -91,7 +80,6 @@ ...@@ -91,7 +80,6 @@
}, },
{ {
"BriefDescription": "Number of D-side only page walks", "BriefDescription": "Number of D-side only page walks",
"Counter": "0,1",
"EventCode": "0xC", "EventCode": "0xC",
"EventName": "PAGE_WALKS.D_SIDE_WALKS", "EventName": "PAGE_WALKS.D_SIDE_WALKS",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -99,7 +87,6 @@ ...@@ -99,7 +87,6 @@
}, },
{ {
"BriefDescription": "Duration of I-Side page walks", "BriefDescription": "Duration of I-Side page walks",
"Counter": "0,1",
"EventCode": "0xC", "EventCode": "0xC",
"EventName": "PAGE_WALKS.I_SIDE_CYCLES", "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
"SampleAfterValue": "2000000", "SampleAfterValue": "2000000",
...@@ -107,7 +94,6 @@ ...@@ -107,7 +94,6 @@
}, },
{ {
"BriefDescription": "Number of I-Side page walks", "BriefDescription": "Number of I-Side page walks",
"Counter": "0,1",
"EventCode": "0xC", "EventCode": "0xC",
"EventName": "PAGE_WALKS.I_SIDE_WALKS", "EventName": "PAGE_WALKS.I_SIDE_WALKS",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
...@@ -115,7 +101,6 @@ ...@@ -115,7 +101,6 @@
}, },
{ {
"BriefDescription": "Number of page-walks executed.", "BriefDescription": "Number of page-walks executed.",
"Counter": "0,1",
"EventCode": "0xC", "EventCode": "0xC",
"EventName": "PAGE_WALKS.WALKS", "EventName": "PAGE_WALKS.WALKS",
"SampleAfterValue": "200000", "SampleAfterValue": "200000",
......
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