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Kirill Smelkov
linux
Commits
70d4f2e5
Commit
70d4f2e5
authored
Dec 19, 2013
by
Simon Horman
Browse files
Options
Browse Files
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Plain Diff
Merge branch 'heads/soc2' into boards2-base
parents
be0647d5
250d829f
Changes
12
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12 changed files
with
356 additions
and
8 deletions
+356
-8
arch/arm/mach-shmobile/Kconfig
arch/arm/mach-shmobile/Kconfig
+5
-0
arch/arm/mach-shmobile/board-bockw.c
arch/arm/mach-shmobile/board-bockw.c
+1
-0
arch/arm/mach-shmobile/clock-r7s72100.c
arch/arm/mach-shmobile/clock-r7s72100.c
+0
-1
arch/arm/mach-shmobile/clock-r8a7790.c
arch/arm/mach-shmobile/clock-r8a7790.c
+4
-0
arch/arm/mach-shmobile/clock-r8a7791.c
arch/arm/mach-shmobile/clock-r8a7791.c
+3
-0
arch/arm/mach-shmobile/clock-sh73a0.c
arch/arm/mach-shmobile/clock-sh73a0.c
+1
-0
arch/arm/mach-shmobile/include/mach/r8a7778.h
arch/arm/mach-shmobile/include/mach/r8a7778.h
+20
-1
arch/arm/mach-shmobile/setup-r8a7778.c
arch/arm/mach-shmobile/setup-r8a7778.c
+69
-0
arch/arm/mach-shmobile/setup-r8a7790.c
arch/arm/mach-shmobile/setup-r8a7790.c
+25
-0
arch/arm/mach-shmobile/setup-rcar-gen2.c
arch/arm/mach-shmobile/setup-rcar-gen2.c
+23
-6
include/dt-bindings/clock/r8a7790-clock.h
include/dt-bindings/clock/r8a7790-clock.h
+100
-0
include/dt-bindings/clock/r8a7791-clock.h
include/dt-bindings/clock/r8a7791-clock.h
+105
-0
No files found.
arch/arm/mach-shmobile/Kconfig
View file @
70d4f2e5
...
@@ -12,6 +12,7 @@ config ARCH_SHMOBILE_MULTI
...
@@ -12,6 +12,7 @@ config ARCH_SHMOBILE_MULTI
select HAVE_SMP
select HAVE_SMP
select ARM_GIC
select ARM_GIC
select MIGHT_HAVE_CACHE_L2X0
select MIGHT_HAVE_CACHE_L2X0
select MIGHT_HAVE_PCI
select NO_IOPORT
select NO_IOPORT
select PINCTRL
select PINCTRL
select ARCH_REQUIRE_GPIOLIB
select ARCH_REQUIRE_GPIOLIB
...
@@ -111,6 +112,7 @@ config ARCH_R8A7790
...
@@ -111,6 +112,7 @@ config ARCH_R8A7790
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_GIC
select ARM_GIC
select CPU_V7
select CPU_V7
select MIGHT_HAVE_PCI
select SH_CLK_CPG
select SH_CLK_CPG
select RENESAS_IRQC
select RENESAS_IRQC
...
@@ -119,6 +121,7 @@ config ARCH_R8A7791
...
@@ -119,6 +121,7 @@ config ARCH_R8A7791
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_GIC
select ARM_GIC
select CPU_V7
select CPU_V7
select MIGHT_HAVE_PCI
select SH_CLK_CPG
select SH_CLK_CPG
select RENESAS_IRQC
select RENESAS_IRQC
...
@@ -127,6 +130,7 @@ config ARCH_EMEV2
...
@@ -127,6 +130,7 @@ config ARCH_EMEV2
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARCH_WANT_OPTIONAL_GPIOLIB
select ARM_GIC
select ARM_GIC
select CPU_V7
select CPU_V7
select MIGHT_HAVE_PCI
select USE_OF
select USE_OF
select AUTO_ZRELADDR
select AUTO_ZRELADDR
...
@@ -265,6 +269,7 @@ config MACH_KOELSCH
...
@@ -265,6 +269,7 @@ config MACH_KOELSCH
bool "Koelsch board"
bool "Koelsch board"
depends on ARCH_R8A7791
depends on ARCH_R8A7791
select USE_OF
select USE_OF
select MICREL_PHY if SH_ETH
config MACH_KOELSCH_REFERENCE
config MACH_KOELSCH_REFERENCE
bool "Koelsch board - Reference Device Tree Implementation"
bool "Koelsch board - Reference Device Tree Implementation"
...
...
arch/arm/mach-shmobile/board-bockw.c
View file @
70d4f2e5
...
@@ -25,6 +25,7 @@
...
@@ -25,6 +25,7 @@
#include <linux/mmc/sh_mmcif.h>
#include <linux/mmc/sh_mmcif.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/partitions.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_data/camera-rcar.h>
#include <linux/platform_data/usb-rcar-phy.h>
#include <linux/platform_data/usb-rcar-phy.h>
#include <linux/platform_device.h>
#include <linux/platform_device.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/fixed.h>
...
...
arch/arm/mach-shmobile/clock-r7s72100.c
View file @
70d4f2e5
...
@@ -181,7 +181,6 @@ static struct clk_lookup lookups[] = {
...
@@ -181,7 +181,6 @@ static struct clk_lookup lookups[] = {
CLKDEV_ICK_ID
(
"sci_fck"
,
"sh-sci.5"
,
&
mstp_clks
[
MSTP42
]),
CLKDEV_ICK_ID
(
"sci_fck"
,
"sh-sci.5"
,
&
mstp_clks
[
MSTP42
]),
CLKDEV_ICK_ID
(
"sci_fck"
,
"sh-sci.6"
,
&
mstp_clks
[
MSTP41
]),
CLKDEV_ICK_ID
(
"sci_fck"
,
"sh-sci.6"
,
&
mstp_clks
[
MSTP41
]),
CLKDEV_ICK_ID
(
"sci_fck"
,
"sh-sci.7"
,
&
mstp_clks
[
MSTP40
]),
CLKDEV_ICK_ID
(
"sci_fck"
,
"sh-sci.7"
,
&
mstp_clks
[
MSTP40
]),
CLKDEV_CON_ID
(
"mtu2_fck"
,
&
mstp_clks
[
MSTP33
]),
};
};
void
__init
r7s72100_clock_init
(
void
)
void
__init
r7s72100_clock_init
(
void
)
...
...
arch/arm/mach-shmobile/clock-r8a7790.c
View file @
70d4f2e5
...
@@ -292,9 +292,13 @@ static struct clk_lookup lookups[] = {
...
@@ -292,9 +292,13 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID
(
"sh-sci.8"
,
&
mstp_clks
[
MSTP717
]),
CLKDEV_DEV_ID
(
"sh-sci.8"
,
&
mstp_clks
[
MSTP717
]),
CLKDEV_DEV_ID
(
"sh-sci.9"
,
&
mstp_clks
[
MSTP716
]),
CLKDEV_DEV_ID
(
"sh-sci.9"
,
&
mstp_clks
[
MSTP716
]),
CLKDEV_DEV_ID
(
"e6508000.i2c"
,
&
mstp_clks
[
MSTP931
]),
CLKDEV_DEV_ID
(
"e6508000.i2c"
,
&
mstp_clks
[
MSTP931
]),
CLKDEV_DEV_ID
(
"i2c-rcar.0"
,
&
mstp_clks
[
MSTP931
]),
CLKDEV_DEV_ID
(
"e6518000.i2c"
,
&
mstp_clks
[
MSTP930
]),
CLKDEV_DEV_ID
(
"e6518000.i2c"
,
&
mstp_clks
[
MSTP930
]),
CLKDEV_DEV_ID
(
"i2c-rcar.1"
,
&
mstp_clks
[
MSTP930
]),
CLKDEV_DEV_ID
(
"e6530000.i2c"
,
&
mstp_clks
[
MSTP929
]),
CLKDEV_DEV_ID
(
"e6530000.i2c"
,
&
mstp_clks
[
MSTP929
]),
CLKDEV_DEV_ID
(
"i2c-rcar.2"
,
&
mstp_clks
[
MSTP929
]),
CLKDEV_DEV_ID
(
"e6540000.i2c"
,
&
mstp_clks
[
MSTP928
]),
CLKDEV_DEV_ID
(
"e6540000.i2c"
,
&
mstp_clks
[
MSTP928
]),
CLKDEV_DEV_ID
(
"i2c-rcar.3"
,
&
mstp_clks
[
MSTP928
]),
CLKDEV_DEV_ID
(
"r8a7790-ether"
,
&
mstp_clks
[
MSTP813
]),
CLKDEV_DEV_ID
(
"r8a7790-ether"
,
&
mstp_clks
[
MSTP813
]),
CLKDEV_DEV_ID
(
"e61f0000.thermal"
,
&
mstp_clks
[
MSTP522
]),
CLKDEV_DEV_ID
(
"e61f0000.thermal"
,
&
mstp_clks
[
MSTP522
]),
CLKDEV_DEV_ID
(
"rcar_thermal"
,
&
mstp_clks
[
MSTP522
]),
CLKDEV_DEV_ID
(
"rcar_thermal"
,
&
mstp_clks
[
MSTP522
]),
...
...
arch/arm/mach-shmobile/clock-r8a7791.c
View file @
70d4f2e5
...
@@ -122,6 +122,7 @@ static struct clk *main_clks[] = {
...
@@ -122,6 +122,7 @@ static struct clk *main_clks[] = {
/* MSTP */
/* MSTP */
enum
{
enum
{
MSTP813
,
MSTP726
,
MSTP724
,
MSTP723
,
MSTP721
,
MSTP720
,
MSTP726
,
MSTP724
,
MSTP723
,
MSTP721
,
MSTP720
,
MSTP719
,
MSTP718
,
MSTP715
,
MSTP714
,
MSTP719
,
MSTP718
,
MSTP715
,
MSTP714
,
MSTP522
,
MSTP522
,
...
@@ -132,6 +133,7 @@ enum {
...
@@ -132,6 +133,7 @@ enum {
};
};
static
struct
clk
mstp_clks
[
MSTP_NR
]
=
{
static
struct
clk
mstp_clks
[
MSTP_NR
]
=
{
[
MSTP813
]
=
SH_CLK_MSTP32
(
&
p_clk
,
SMSTPCR8
,
13
,
0
),
/* Ether */
[
MSTP726
]
=
SH_CLK_MSTP32
(
&
zx_clk
,
SMSTPCR7
,
26
,
0
),
/* LVDS0 */
[
MSTP726
]
=
SH_CLK_MSTP32
(
&
zx_clk
,
SMSTPCR7
,
26
,
0
),
/* LVDS0 */
[
MSTP724
]
=
SH_CLK_MSTP32
(
&
zx_clk
,
SMSTPCR7
,
24
,
0
),
/* DU0 */
[
MSTP724
]
=
SH_CLK_MSTP32
(
&
zx_clk
,
SMSTPCR7
,
24
,
0
),
/* DU0 */
[
MSTP723
]
=
SH_CLK_MSTP32
(
&
zx_clk
,
SMSTPCR7
,
23
,
0
),
/* DU1 */
[
MSTP723
]
=
SH_CLK_MSTP32
(
&
zx_clk
,
SMSTPCR7
,
23
,
0
),
/* DU1 */
...
@@ -192,6 +194,7 @@ static struct clk_lookup lookups[] = {
...
@@ -192,6 +194,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID
(
"sh_cmt.0"
,
&
mstp_clks
[
MSTP124
]),
CLKDEV_DEV_ID
(
"sh_cmt.0"
,
&
mstp_clks
[
MSTP124
]),
CLKDEV_DEV_ID
(
"e61f0000.thermal"
,
&
mstp_clks
[
MSTP522
]),
CLKDEV_DEV_ID
(
"e61f0000.thermal"
,
&
mstp_clks
[
MSTP522
]),
CLKDEV_DEV_ID
(
"rcar_thermal"
,
&
mstp_clks
[
MSTP522
]),
CLKDEV_DEV_ID
(
"rcar_thermal"
,
&
mstp_clks
[
MSTP522
]),
CLKDEV_DEV_ID
(
"r8a7791-ether"
,
&
mstp_clks
[
MSTP813
]),
/* Ether */
};
};
#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
#define R8A7791_CLOCK_ROOT(e, m, p0, p1, p30, p31) \
...
...
arch/arm/mach-shmobile/clock-sh73a0.c
View file @
70d4f2e5
...
@@ -652,6 +652,7 @@ static struct clk_lookup lookups[] = {
...
@@ -652,6 +652,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID
(
"sh-sci.6"
,
&
mstp_clks
[
MSTP331
]),
/* SCIFA6 */
CLKDEV_DEV_ID
(
"sh-sci.6"
,
&
mstp_clks
[
MSTP331
]),
/* SCIFA6 */
CLKDEV_DEV_ID
(
"sh_cmt.10"
,
&
mstp_clks
[
MSTP329
]),
/* CMT10 */
CLKDEV_DEV_ID
(
"sh_cmt.10"
,
&
mstp_clks
[
MSTP329
]),
/* CMT10 */
CLKDEV_DEV_ID
(
"sh_fsi2"
,
&
mstp_clks
[
MSTP328
]),
/* FSI */
CLKDEV_DEV_ID
(
"sh_fsi2"
,
&
mstp_clks
[
MSTP328
]),
/* FSI */
CLKDEV_DEV_ID
(
"ec230000.sound"
,
&
mstp_clks
[
MSTP328
]),
/* FSI */
CLKDEV_DEV_ID
(
"sh_irda.0"
,
&
mstp_clks
[
MSTP325
]),
/* IrDA */
CLKDEV_DEV_ID
(
"sh_irda.0"
,
&
mstp_clks
[
MSTP325
]),
/* IrDA */
CLKDEV_DEV_ID
(
"i2c-sh_mobile.1"
,
&
mstp_clks
[
MSTP323
]),
/* I2C1 */
CLKDEV_DEV_ID
(
"i2c-sh_mobile.1"
,
&
mstp_clks
[
MSTP323
]),
/* I2C1 */
CLKDEV_DEV_ID
(
"e6822000.i2c"
,
&
mstp_clks
[
MSTP323
]),
/* I2C1 */
CLKDEV_DEV_ID
(
"e6822000.i2c"
,
&
mstp_clks
[
MSTP323
]),
/* I2C1 */
...
...
arch/arm/mach-shmobile/include/mach/r8a7778.h
View file @
70d4f2e5
...
@@ -20,13 +20,30 @@
...
@@ -20,13 +20,30 @@
#define __ASM_R8A7778_H__
#define __ASM_R8A7778_H__
#include <linux/sh_eth.h>
#include <linux/sh_eth.h>
#include <linux/platform_data/camera-rcar.h>
/* HPB-DMA slave IDs */
/* HPB-DMA slave IDs */
enum
{
enum
{
HPBDMA_SLAVE_DUMMY
,
HPBDMA_SLAVE_DUMMY
,
HPBDMA_SLAVE_SDHI0_TX
,
HPBDMA_SLAVE_SDHI0_TX
,
HPBDMA_SLAVE_SDHI0_RX
,
HPBDMA_SLAVE_SDHI0_RX
,
HPBDMA_SLAVE_SSI0_TX
,
HPBDMA_SLAVE_SSI0_RX
,
HPBDMA_SLAVE_SSI1_TX
,
HPBDMA_SLAVE_SSI1_RX
,
HPBDMA_SLAVE_SSI2_TX
,
HPBDMA_SLAVE_SSI2_RX
,
HPBDMA_SLAVE_SSI3_TX
,
HPBDMA_SLAVE_SSI3_RX
,
HPBDMA_SLAVE_SSI4_TX
,
HPBDMA_SLAVE_SSI4_RX
,
HPBDMA_SLAVE_SSI5_TX
,
HPBDMA_SLAVE_SSI5_RX
,
HPBDMA_SLAVE_SSI6_TX
,
HPBDMA_SLAVE_SSI6_RX
,
HPBDMA_SLAVE_SSI7_TX
,
HPBDMA_SLAVE_SSI7_RX
,
HPBDMA_SLAVE_SSI8_TX
,
HPBDMA_SLAVE_SSI8_RX
,
HPBDMA_SLAVE_HPBIF0_TX
,
HPBDMA_SLAVE_HPBIF0_TX
,
HPBDMA_SLAVE_HPBIF0_RX
,
HPBDMA_SLAVE_HPBIF0_RX
,
HPBDMA_SLAVE_HPBIF1_TX
,
HPBDMA_SLAVE_HPBIF1_TX
,
...
@@ -45,6 +62,8 @@ enum {
...
@@ -45,6 +62,8 @@ enum {
HPBDMA_SLAVE_HPBIF7_RX
,
HPBDMA_SLAVE_HPBIF7_RX
,
HPBDMA_SLAVE_HPBIF8_TX
,
HPBDMA_SLAVE_HPBIF8_TX
,
HPBDMA_SLAVE_HPBIF8_RX
,
HPBDMA_SLAVE_HPBIF8_RX
,
HPBDMA_SLAVE_USBFUNC_TX
,
HPBDMA_SLAVE_USBFUNC_RX
,
};
};
extern
void
r8a7778_add_standard_devices
(
void
);
extern
void
r8a7778_add_standard_devices
(
void
);
...
...
arch/arm/mach-shmobile/setup-r8a7778.c
View file @
70d4f2e5
...
@@ -319,6 +319,29 @@ void __init r8a7778_add_dt_devices(void)
...
@@ -319,6 +319,29 @@ void __init r8a7778_add_dt_devices(void)
#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1)
/* SDHI0 */
#define HPB_DMAE_ASYNCMDR_ASMD21_SINGLE BIT(1)
/* SDHI0 */
#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0
/* SDHI0 */
#define HPB_DMAE_ASYNCMDR_ASMD21_MULTI 0
/* SDHI0 */
#define HPBDMA_SSI(_id) \
{ \
.id = HPBDMA_SLAVE_SSI## _id ##_TX, \
.addr = 0xffd91008 + (_id * 0x40), \
.dcr = HPB_DMAE_DCR_CT | \
HPB_DMAE_DCR_DIP | \
HPB_DMAE_DCR_SPDS_32BIT | \
HPB_DMAE_DCR_DMDL | \
HPB_DMAE_DCR_DPDS_32BIT, \
.port = _id + (_id << 8), \
.dma_ch = (28 + _id), \
}, { \
.id = HPBDMA_SLAVE_SSI## _id ##_RX, \
.addr = 0xffd9100c + (_id * 0x40), \
.dcr = HPB_DMAE_DCR_CT | \
HPB_DMAE_DCR_DIP | \
HPB_DMAE_DCR_SMDL | \
HPB_DMAE_DCR_SPDS_32BIT | \
HPB_DMAE_DCR_DPDS_32BIT, \
.port = _id + (_id << 8), \
.dma_ch = (28 + _id), \
}
#define HPBDMA_HPBIF(_id) \
#define HPBDMA_HPBIF(_id) \
{ \
{ \
.id = HPBDMA_SLAVE_HPBIF## _id ##_TX, \
.id = HPBDMA_SLAVE_HPBIF## _id ##_TX, \
...
@@ -371,8 +394,34 @@ static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
...
@@ -371,8 +394,34 @@ static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
.
port
=
0x0D0C
,
.
port
=
0x0D0C
,
.
flags
=
HPB_DMAE_SET_ASYNC_RESET
|
HPB_DMAE_SET_ASYNC_MODE
,
.
flags
=
HPB_DMAE_SET_ASYNC_RESET
|
HPB_DMAE_SET_ASYNC_MODE
,
.
dma_ch
=
22
,
.
dma_ch
=
22
,
},
{
.
id
=
HPBDMA_SLAVE_USBFUNC_TX
,
/* for D0 */
.
addr
=
0xffe60018
,
.
dcr
=
HPB_DMAE_DCR_SPDS_32BIT
|
HPB_DMAE_DCR_DMDL
|
HPB_DMAE_DCR_DPDS_32BIT
,
.
port
=
0x0000
,
.
dma_ch
=
14
,
},
{
.
id
=
HPBDMA_SLAVE_USBFUNC_RX
,
/* for D1 */
.
addr
=
0xffe6001c
,
.
dcr
=
HPB_DMAE_DCR_SMDL
|
HPB_DMAE_DCR_SPDS_32BIT
|
HPB_DMAE_DCR_DPDS_32BIT
,
.
port
=
0x0101
,
.
dma_ch
=
15
,
},
},
HPBDMA_SSI
(
0
),
HPBDMA_SSI
(
1
),
HPBDMA_SSI
(
2
),
HPBDMA_SSI
(
3
),
HPBDMA_SSI
(
4
),
HPBDMA_SSI
(
5
),
HPBDMA_SSI
(
6
),
HPBDMA_SSI
(
7
),
HPBDMA_SSI
(
8
),
HPBDMA_HPBIF
(
0
),
HPBDMA_HPBIF
(
0
),
HPBDMA_HPBIF
(
1
),
HPBDMA_HPBIF
(
1
),
HPBDMA_HPBIF
(
2
),
HPBDMA_HPBIF
(
2
),
...
@@ -385,24 +434,44 @@ static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
...
@@ -385,24 +434,44 @@ static const struct hpb_dmae_slave_config hpb_dmae_slaves[] = {
};
};
static
const
struct
hpb_dmae_channel
hpb_dmae_channels
[]
=
{
static
const
struct
hpb_dmae_channel
hpb_dmae_channels
[]
=
{
HPB_DMAE_CHANNEL
(
0x7c
,
HPBDMA_SLAVE_USBFUNC_TX
),
/* ch. 14 */
HPB_DMAE_CHANNEL
(
0x7c
,
HPBDMA_SLAVE_USBFUNC_RX
),
/* ch. 15 */
HPB_DMAE_CHANNEL
(
0x7e
,
HPBDMA_SLAVE_SDHI0_TX
),
/* ch. 21 */
HPB_DMAE_CHANNEL
(
0x7e
,
HPBDMA_SLAVE_SDHI0_TX
),
/* ch. 21 */
HPB_DMAE_CHANNEL
(
0x7e
,
HPBDMA_SLAVE_SDHI0_RX
),
/* ch. 22 */
HPB_DMAE_CHANNEL
(
0x7e
,
HPBDMA_SLAVE_SDHI0_RX
),
/* ch. 22 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_SSI0_TX
),
/* ch. 28 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_SSI0_RX
),
/* ch. 28 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF0_TX
),
/* ch. 28 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF0_TX
),
/* ch. 28 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF0_RX
),
/* ch. 28 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF0_RX
),
/* ch. 28 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_SSI1_TX
),
/* ch. 29 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_SSI1_RX
),
/* ch. 29 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF1_TX
),
/* ch. 29 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF1_TX
),
/* ch. 29 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF1_RX
),
/* ch. 29 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF1_RX
),
/* ch. 29 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_SSI2_TX
),
/* ch. 30 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_SSI2_RX
),
/* ch. 30 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF2_TX
),
/* ch. 30 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF2_TX
),
/* ch. 30 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF2_RX
),
/* ch. 30 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF2_RX
),
/* ch. 30 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_SSI3_TX
),
/* ch. 31 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_SSI3_RX
),
/* ch. 31 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF3_TX
),
/* ch. 31 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF3_TX
),
/* ch. 31 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF3_RX
),
/* ch. 31 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF3_RX
),
/* ch. 31 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_SSI4_TX
),
/* ch. 32 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_SSI4_RX
),
/* ch. 32 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF4_TX
),
/* ch. 32 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF4_TX
),
/* ch. 32 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF4_RX
),
/* ch. 32 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF4_RX
),
/* ch. 32 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_SSI5_TX
),
/* ch. 33 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_SSI5_RX
),
/* ch. 33 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF5_TX
),
/* ch. 33 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF5_TX
),
/* ch. 33 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF5_RX
),
/* ch. 33 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF5_RX
),
/* ch. 33 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_SSI6_TX
),
/* ch. 34 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_SSI6_RX
),
/* ch. 34 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF6_TX
),
/* ch. 34 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF6_TX
),
/* ch. 34 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF6_RX
),
/* ch. 34 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF6_RX
),
/* ch. 34 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_SSI7_TX
),
/* ch. 35 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_SSI7_RX
),
/* ch. 35 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF7_TX
),
/* ch. 35 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF7_TX
),
/* ch. 35 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF7_RX
),
/* ch. 35 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF7_RX
),
/* ch. 35 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_SSI8_TX
),
/* ch. 36 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_SSI8_RX
),
/* ch. 36 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF8_TX
),
/* ch. 36 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF8_TX
),
/* ch. 36 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF8_RX
),
/* ch. 36 */
HPB_DMAE_CHANNEL
(
0x7f
,
HPBDMA_SLAVE_HPBIF8_RX
),
/* ch. 36 */
};
};
...
...
arch/arm/mach-shmobile/setup-r8a7790.c
View file @
70d4f2e5
...
@@ -67,6 +67,27 @@ R8A7790_GPIO(5);
...
@@ -67,6 +67,27 @@ R8A7790_GPIO(5);
&r8a7790_gpio##idx##_platform_data, \
&r8a7790_gpio##idx##_platform_data, \
sizeof(r8a7790_gpio##idx##_platform_data))
sizeof(r8a7790_gpio##idx##_platform_data))
static
struct
resource
i2c_resources
[]
__initdata
=
{
/* I2C0 */
DEFINE_RES_MEM
(
0xE6508000
,
0x40
),
DEFINE_RES_IRQ
(
gic_spi
(
287
)),
/* I2C1 */
DEFINE_RES_MEM
(
0xE6518000
,
0x40
),
DEFINE_RES_IRQ
(
gic_spi
(
288
)),
/* I2C2 */
DEFINE_RES_MEM
(
0xE6530000
,
0x40
),
DEFINE_RES_IRQ
(
gic_spi
(
286
)),
/* I2C3 */
DEFINE_RES_MEM
(
0xE6540000
,
0x40
),
DEFINE_RES_IRQ
(
gic_spi
(
290
)),
};
#define r8a7790_register_i2c(idx) \
platform_device_register_simple( \
"i2c-rcar", idx, \
i2c_resources + (2 * idx), 2); \
void
__init
r8a7790_pinmux_init
(
void
)
void
__init
r8a7790_pinmux_init
(
void
)
{
{
r8a7790_register_pfc
();
r8a7790_register_pfc
();
...
@@ -76,6 +97,10 @@ void __init r8a7790_pinmux_init(void)
...
@@ -76,6 +97,10 @@ void __init r8a7790_pinmux_init(void)
r8a7790_register_gpio
(
3
);
r8a7790_register_gpio
(
3
);
r8a7790_register_gpio
(
4
);
r8a7790_register_gpio
(
4
);
r8a7790_register_gpio
(
5
);
r8a7790_register_gpio
(
5
);
r8a7790_register_i2c
(
0
);
r8a7790_register_i2c
(
1
);
r8a7790_register_i2c
(
2
);
r8a7790_register_i2c
(
3
);
}
}
#define SCIF_COMMON(scif_type, baseaddr, irq) \
#define SCIF_COMMON(scif_type, baseaddr, irq) \
...
...
arch/arm/mach-shmobile/setup-rcar-gen2.c
View file @
70d4f2e5
...
@@ -18,6 +18,7 @@
...
@@ -18,6 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
*/
#include <linux/clk/shmobile.h>
#include <linux/clocksource.h>
#include <linux/clocksource.h>
#include <linux/io.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/kernel.h>
...
@@ -44,8 +45,10 @@ u32 __init rcar_gen2_read_mode_pins(void)
...
@@ -44,8 +45,10 @@ u32 __init rcar_gen2_read_mode_pins(void)
void
__init
rcar_gen2_timer_init
(
void
)
void
__init
rcar_gen2_timer_init
(
void
)
{
{
#if
def CONFIG_ARM_ARCH_TIMER
#if
defined(CONFIG_ARM_ARCH_TIMER) || defined(CONFIG_COMMON_CLK)
u32
mode
=
rcar_gen2_read_mode_pins
();
u32
mode
=
rcar_gen2_read_mode_pins
();
#endif
#ifdef CONFIG_ARM_ARCH_TIMER
void
__iomem
*
base
;
void
__iomem
*
base
;
int
extal_mhz
=
0
;
int
extal_mhz
=
0
;
u32
freq
;
u32
freq
;
...
@@ -78,14 +81,28 @@ void __init rcar_gen2_timer_init(void)
...
@@ -78,14 +81,28 @@ void __init rcar_gen2_timer_init(void)
/* Remap "armgcnt address map" space */
/* Remap "armgcnt address map" space */
base
=
ioremap
(
0xe6080000
,
PAGE_SIZE
);
base
=
ioremap
(
0xe6080000
,
PAGE_SIZE
);
/* Update registers with correct frequency */
/*
iowrite32
(
freq
,
base
+
CNTFID0
);
* Update the timer if it is either not running, or is not at the
asm
volatile
(
"mcr p15, 0, %0, c14, c0, 0"
:
:
"r"
(
freq
));
* right frequency. The timer is only configurable in secure mode
* so this avoids an abort if the loader started the timer and
* entered the kernel in non-secure mode.
*/
if
((
ioread32
(
base
+
CNTCR
)
&
1
)
==
0
||
ioread32
(
base
+
CNTFID0
)
!=
freq
)
{
/* Update registers with correct frequency */
iowrite32
(
freq
,
base
+
CNTFID0
);
asm
volatile
(
"mcr p15, 0, %0, c14, c0, 0"
:
:
"r"
(
freq
));
/* make sure arch timer is started by setting bit 0 of CNTCR */
iowrite32
(
1
,
base
+
CNTCR
);
}
/* make sure arch timer is started by setting bit 0 of CNTCR */
iowrite32
(
1
,
base
+
CNTCR
);
iounmap
(
base
);
iounmap
(
base
);
#endif
/* CONFIG_ARM_ARCH_TIMER */
#endif
/* CONFIG_ARM_ARCH_TIMER */
#ifdef CONFIG_COMMON_CLK
rcar_gen2_clocks_init
(
mode
);
#endif
clocksource_of_init
();
clocksource_of_init
();
}
}
include/dt-bindings/clock/r8a7790-clock.h
0 → 100644
View file @
70d4f2e5
/*
* Copyright 2013 Ideas On Board SPRL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7790_H__
#define __DT_BINDINGS_CLOCK_R8A7790_H__
/* CPG */
#define R8A7790_CLK_MAIN 0
#define R8A7790_CLK_PLL0 1
#define R8A7790_CLK_PLL1 2
#define R8A7790_CLK_PLL3 3
#define R8A7790_CLK_LB 4
#define R8A7790_CLK_QSPI 5
#define R8A7790_CLK_SDH 6
#define R8A7790_CLK_SD0 7
#define R8A7790_CLK_SD1 8
#define R8A7790_CLK_Z 9
/* MSTP1 */
#define R8A7790_CLK_TMU1 11
#define R8A7790_CLK_TMU3 21
#define R8A7790_CLK_TMU2 22
#define R8A7790_CLK_CMT0 24
#define R8A7790_CLK_TMU0 25
#define R8A7790_CLK_VSP1_DU1 27
#define R8A7790_CLK_VSP1_DU0 28
#define R8A7790_CLK_VSP1_RT 30
#define R8A7790_CLK_VSP1_SY 31
/* MSTP2 */
#define R8A7790_CLK_SCIFA2 2
#define R8A7790_CLK_SCIFA1 3
#define R8A7790_CLK_SCIFA0 4
#define R8A7790_CLK_SCIFB0 6
#define R8A7790_CLK_SCIFB1 7
#define R8A7790_CLK_SCIFB2 16
#define R8A7790_CLK_SYS_DMAC0 18
#define R8A7790_CLK_SYS_DMAC1 19
/* MSTP3 */
#define R8A7790_CLK_TPU0 4
#define R8A7790_CLK_MMCIF1 5
#define R8A7790_CLK_SDHI3 11
#define R8A7790_CLK_SDHI2 12
#define R8A7790_CLK_SDHI1 13
#define R8A7790_CLK_SDHI0 14
#define R8A7790_CLK_MMCIF0 15
#define R8A7790_CLK_SSUSB 28
#define R8A7790_CLK_CMT1 29
#define R8A7790_CLK_USBDMAC0 30
#define R8A7790_CLK_USBDMAC1 31
/* MSTP5 */
#define R8A7790_CLK_THERMAL 22
#define R8A7790_CLK_PWM 23
/* MSTP7 */
#define R8A7790_CLK_EHCI 3
#define R8A7790_CLK_HSUSB 4
#define R8A7790_CLK_HSCIF1 16
#define R8A7790_CLK_HSCIF0 17
#define R8A7790_CLK_SCIF1 20
#define R8A7790_CLK_SCIF0 21
#define R8A7790_CLK_DU2 22
#define R8A7790_CLK_DU1 23
#define R8A7790_CLK_DU0 24
#define R8A7790_CLK_LVDS1 25
#define R8A7790_CLK_LVDS0 26
/* MSTP8 */
#define R8A7790_CLK_VIN3 8
#define R8A7790_CLK_VIN2 9
#define R8A7790_CLK_VIN1 10
#define R8A7790_CLK_VIN0 11
#define R8A7790_CLK_ETHER 13
#define R8A7790_CLK_SATA1 14
#define R8A7790_CLK_SATA0 15
/* MSTP9 */
#define R8A7790_CLK_GPIO5 7
#define R8A7790_CLK_GPIO4 8
#define R8A7790_CLK_GPIO3 9
#define R8A7790_CLK_GPIO2 10
#define R8A7790_CLK_GPIO1 11
#define R8A7790_CLK_GPIO0 12
#define R8A7790_CLK_RCAN1 15
#define R8A7790_CLK_RCAN0 16
#define R8A7790_CLK_IICDVFS 26
#define R8A7790_CLK_I2C3 28
#define R8A7790_CLK_I2C2 29
#define R8A7790_CLK_I2C1 30
#define R8A7790_CLK_I2C0 31
#endif
/* __DT_BINDINGS_CLOCK_R8A7790_H__ */
include/dt-bindings/clock/r8a7791-clock.h
0 → 100644
View file @
70d4f2e5
/*
* Copyright 2013 Ideas On Board SPRL
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef __DT_BINDINGS_CLOCK_R8A7791_H__
#define __DT_BINDINGS_CLOCK_R8A7791_H__
/* CPG */
#define R8A7791_CLK_MAIN 0
#define R8A7791_CLK_PLL0 1
#define R8A7791_CLK_PLL1 2
#define R8A7791_CLK_PLL3 3
#define R8A7791_CLK_LB 4
#define R8A7791_CLK_QSPI 5
#define R8A7791_CLK_SDH 6
#define R8A7791_CLK_SD0 7
#define R8A7791_CLK_Z 8
/* MSTP1 */
#define R8A7791_CLK_TMU1 11
#define R8A7791_CLK_TMU3 21
#define R8A7791_CLK_TMU2 22
#define R8A7791_CLK_CMT0 24
#define R8A7791_CLK_TMU0 25
#define R8A7791_CLK_VSP1_DU1 27
#define R8A7791_CLK_VSP1_DU0 28
#define R8A7791_CLK_VSP1_SY 31
/* MSTP2 */
#define R8A7791_CLK_SCIFA2 2
#define R8A7791_CLK_SCIFA1 3
#define R8A7791_CLK_SCIFA0 4
#define R8A7791_CLK_SCIFB0 6
#define R8A7791_CLK_SCIFB1 7
#define R8A7791_CLK_SCIFB2 16
#define R8A7791_CLK_DMAC 18
/* MSTP3 */
#define R8A7791_CLK_TPU0 4
#define R8A7791_CLK_SDHI2 11
#define R8A7791_CLK_SDHI1 12
#define R8A7791_CLK_SDHI0 14
#define R8A7791_CLK_MMCIF0 15
#define R8A7791_CLK_SSUSB 28
#define R8A7791_CLK_CMT1 29
#define R8A7791_CLK_USBDMAC0 30
#define R8A7791_CLK_USBDMAC1 31
/* MSTP5 */
#define R8A7791_CLK_THERMAL 22
#define R8A7791_CLK_PWM 23
/* MSTP7 */
#define R8A7791_CLK_HSUSB 4
#define R8A7791_CLK_HSCIF2 13
#define R8A7791_CLK_SCIF5 14
#define R8A7791_CLK_SCIF4 15
#define R8A7791_CLK_HSCIF1 16
#define R8A7791_CLK_HSCIF0 17
#define R8A7791_CLK_SCIF3 18
#define R8A7791_CLK_SCIF2 19
#define R8A7791_CLK_SCIF1 20
#define R8A7791_CLK_SCIF0 21
#define R8A7791_CLK_DU1 23
#define R8A7791_CLK_DU0 24
#define R8A7791_CLK_LVDS0 26
/* MSTP8 */
#define R8A7791_CLK_VIN2 9
#define R8A7791_CLK_VIN1 10
#define R8A7791_CLK_VIN0 11
#define R8A7791_CLK_ETHER 13
#define R8A7791_CLK_SATA1 14
#define R8A7791_CLK_SATA0 15
/* MSTP9 */
#define R8A7791_CLK_GPIO7 4
#define R8A7791_CLK_GPIO6 5
#define R8A7791_CLK_GPIO5 7
#define R8A7791_CLK_GPIO4 8
#define R8A7791_CLK_GPIO3 9
#define R8A7791_CLK_GPIO2 10
#define R8A7791_CLK_GPIO1 11
#define R8A7791_CLK_GPIO0 12
#define R8A7791_CLK_RCAN1 15
#define R8A7791_CLK_RCAN0 16
#define R8A7791_CLK_I2C5 25
#define R8A7791_CLK_IICDVFS 26
#define R8A7791_CLK_I2C4 27
#define R8A7791_CLK_I2C3 28
#define R8A7791_CLK_I2C2 29
#define R8A7791_CLK_I2C1 30
#define R8A7791_CLK_I2C0 31
/* MSTP11 */
#define R8A7791_CLK_SCIFA3 6
#define R8A7791_CLK_SCIFA4 7
#define R8A7791_CLK_SCIFA5 8
#endif
/* __DT_BINDINGS_CLOCK_R8A7791_H__ */
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