Commit 77cda4b9 authored by Mark Brown's avatar Mark Brown

Merge existing fixes from spi/for-6.1 into new branch

parents 9abf2313 6a43cd02
...@@ -1163,7 +1163,7 @@ static const struct aspeed_spi_data ast2500_spi_data = { ...@@ -1163,7 +1163,7 @@ static const struct aspeed_spi_data ast2500_spi_data = {
static const struct aspeed_spi_data ast2600_fmc_data = { static const struct aspeed_spi_data ast2600_fmc_data = {
.max_cs = 3, .max_cs = 3,
.hastype = false, .hastype = false,
.mode_bits = SPI_RX_QUAD | SPI_RX_QUAD, .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD,
.we0 = 16, .we0 = 16,
.ctl0 = CE0_CTRL_REG, .ctl0 = CE0_CTRL_REG,
.timing = CE0_TIMING_COMPENSATION_REG, .timing = CE0_TIMING_COMPENSATION_REG,
...@@ -1178,7 +1178,7 @@ static const struct aspeed_spi_data ast2600_fmc_data = { ...@@ -1178,7 +1178,7 @@ static const struct aspeed_spi_data ast2600_fmc_data = {
static const struct aspeed_spi_data ast2600_spi_data = { static const struct aspeed_spi_data ast2600_spi_data = {
.max_cs = 2, .max_cs = 2,
.hastype = false, .hastype = false,
.mode_bits = SPI_RX_QUAD | SPI_RX_QUAD, .mode_bits = SPI_RX_QUAD | SPI_TX_QUAD,
.we0 = 16, .we0 = 16,
.ctl0 = CE0_CTRL_REG, .ctl0 = CE0_CTRL_REG,
.timing = CE0_TIMING_COMPENSATION_REG, .timing = CE0_TIMING_COMPENSATION_REG,
......
// SPDX-License-Identifier: GPL-2.0=or-later // SPDX-License-Identifier: GPL-2.0-or-later
/* Copyright (C) 2022 Hewlett-Packard Development Company, L.P. */ /* Copyright (C) 2022 Hewlett-Packard Development Company, L.P. */
#include <linux/iopoll.h> #include <linux/iopoll.h>
......
...@@ -114,7 +114,7 @@ ...@@ -114,7 +114,7 @@
#define ERASE_OPCODE_SHIFT 8 #define ERASE_OPCODE_SHIFT 8
#define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) #define ERASE_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT)
#define ERASE_64K_OPCODE_SHIFT 16 #define ERASE_64K_OPCODE_SHIFT 16
#define ERASE_64K_OPCODE_MASK (0xff << ERASE_OPCODE_SHIFT) #define ERASE_64K_OPCODE_MASK (0xff << ERASE_64K_OPCODE_SHIFT)
/* Flash descriptor fields */ /* Flash descriptor fields */
#define FLVALSIG_MAGIC 0x0ff0a55a #define FLVALSIG_MAGIC 0x0ff0a55a
......
...@@ -151,7 +151,7 @@ mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data) ...@@ -151,7 +151,7 @@ mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
int spr, sppr; int spr, sppr;
u8 ctrl1; u8 ctrl1;
if (status && (irq != NO_IRQ)) if (status && irq)
dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n", dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
status); status);
......
...@@ -1157,6 +1157,11 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi, ...@@ -1157,6 +1157,11 @@ static int tegra_qspi_combined_seq_xfer(struct tegra_qspi *tqspi,
msg->actual_length += xfer->len; msg->actual_length += xfer->len;
transfer_phase++; transfer_phase++;
} }
if (!xfer->cs_change) {
tegra_qspi_transfer_end(spi);
spi_transfer_delay_exec(xfer);
}
ret = 0;
exit: exit:
msg->status = ret; msg->status = ret;
......
...@@ -225,7 +225,7 @@ static inline void *spi_mem_get_drvdata(struct spi_mem *mem) ...@@ -225,7 +225,7 @@ static inline void *spi_mem_get_drvdata(struct spi_mem *mem)
/** /**
* struct spi_controller_mem_ops - SPI memory operations * struct spi_controller_mem_ops - SPI memory operations
* @adjust_op_size: shrink the data xfer of an operation to match controller's * @adjust_op_size: shrink the data xfer of an operation to match controller's
* limitations (can be alignment of max RX/TX size * limitations (can be alignment or max RX/TX size
* limitations) * limitations)
* @supports_op: check if an operation is supported by the controller * @supports_op: check if an operation is supported by the controller
* @exec_op: execute a SPI memory operation * @exec_op: execute a SPI memory operation
......
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