Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Support
Keyboard shortcuts
?
Submit feedback
Contribute to GitLab
Sign in / Register
Toggle navigation
L
linux
Project overview
Project overview
Details
Activity
Releases
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Issues
0
Issues
0
List
Boards
Labels
Milestones
Merge Requests
0
Merge Requests
0
Analytics
Analytics
Repository
Value Stream
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Create a new issue
Commits
Issue Boards
Open sidebar
Kirill Smelkov
linux
Commits
7fb8ec8e
Commit
7fb8ec8e
authored
Jan 05, 2010
by
Ben Skeggs
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
drm/nv50: restore correct cache1 get/put address on fifoctx load
Signed-off-by:
Ben Skeggs
<
bskeggs@redhat.com
>
parent
846975a9
Changes
1
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
2 additions
and
4 deletions
+2
-4
drivers/gpu/drm/nouveau/nv50_fifo.c
drivers/gpu/drm/nouveau/nv50_fifo.c
+2
-4
No files found.
drivers/gpu/drm/nouveau/nv50_fifo.c
View file @
7fb8ec8e
...
@@ -384,8 +384,8 @@ nv50_fifo_load_context(struct nouveau_channel *chan)
...
@@ -384,8 +384,8 @@ nv50_fifo_load_context(struct nouveau_channel *chan)
nv_wr32
(
dev
,
NV40_PFIFO_CACHE1_DATA
(
ptr
),
nv_wr32
(
dev
,
NV40_PFIFO_CACHE1_DATA
(
ptr
),
nv_ro32
(
dev
,
cache
,
(
ptr
*
2
)
+
1
));
nv_ro32
(
dev
,
cache
,
(
ptr
*
2
)
+
1
));
}
}
nv_wr32
(
dev
,
0x3210
,
cnt
<<
2
);
nv_wr32
(
dev
,
NV03_PFIFO_CACHE1_PUT
,
cnt
<<
2
);
nv_wr32
(
dev
,
0x3270
,
0
);
nv_wr32
(
dev
,
NV03_PFIFO_CACHE1_GET
,
0
);
/* guessing that all the 0x34xx regs aren't on NV50 */
/* guessing that all the 0x34xx regs aren't on NV50 */
if
(
!
IS_G80
)
{
if
(
!
IS_G80
)
{
...
@@ -398,8 +398,6 @@ nv50_fifo_load_context(struct nouveau_channel *chan)
...
@@ -398,8 +398,6 @@ nv50_fifo_load_context(struct nouveau_channel *chan)
dev_priv
->
engine
.
instmem
.
finish_access
(
dev
);
dev_priv
->
engine
.
instmem
.
finish_access
(
dev
);
nv_wr32
(
dev
,
NV03_PFIFO_CACHE1_GET
,
0
);
nv_wr32
(
dev
,
NV03_PFIFO_CACHE1_PUT
,
0
);
nv_wr32
(
dev
,
NV03_PFIFO_CACHE1_PUSH1
,
chan
->
id
|
(
1
<<
16
));
nv_wr32
(
dev
,
NV03_PFIFO_CACHE1_PUSH1
,
chan
->
id
|
(
1
<<
16
));
return
0
;
return
0
;
}
}
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment