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Commit 8da0e500 authored by Alex Deucher's avatar Alex Deucher
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drm/radeon/dce8: crtc_set_base updates 

Some new fields and DESKTOP_HEIGHT register moved.
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d798f2f2
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Showing with 108 additions and 5 deletions
drivers/gpu/drm/radeon/atombios_crtc.c
View file @ 8da0e500
......@@ -1143,7 +1143,9 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
}
if (tiling_flags & RADEON_TILING_MACRO) {
if (rdev->family >= CHIP_TAHITI)
if (rdev->family >= CHIP_BONAIRE)
tmp = rdev->config.cik.tile_config;
else if (rdev->family >= CHIP_TAHITI)
tmp = rdev->config.si.tile_config;
else if (rdev->family >= CHIP_CAYMAN)
tmp = rdev->config.cayman.tile_config;
......@@ -1170,10 +1172,28 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
if (rdev->family >= CHIP_BONAIRE) {
/* XXX need to know more about the surface tiling mode */
fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
}
} else if (tiling_flags & RADEON_TILING_MICRO)
fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
if ((rdev->family == CHIP_TAHITI) ||
if (rdev->family >= CHIP_BONAIRE) {
u32 num_pipe_configs = rdev->config.cik.max_tile_pipes;
u32 num_rb = rdev->config.cik.max_backends_per_se;
if (num_pipe_configs > 8)
num_pipe_configs = 8;
if (num_pipe_configs == 8)
fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P8_32x32_16x16);
else if (num_pipe_configs == 4) {
if (num_rb == 4)
fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P4_16x16);
else if (num_rb < 4)
fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P4_8x16);
} else if (num_pipe_configs == 2)
fb_format |= CIK_GRPH_PIPE_CONFIG(CIK_ADDR_SURF_P2);
} else if ((rdev->family == CHIP_TAHITI) ||
(rdev->family == CHIP_PITCAIRN))
fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
else if (rdev->family == CHIP_VERDE)
......@@ -1224,6 +1244,10 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
if (rdev->family >= CHIP_BONAIRE)
WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
target_fb->height);
else
WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
target_fb->height);
x &= ~3;
......
drivers/gpu/drm/radeon/cik_reg.h
View file @ 8da0e500
......@@ -29,6 +29,83 @@
#define CIK_DC_GPIO_HPD_EN 0x65b8
#define CIK_DC_GPIO_HPD_Y 0x65bc
#define CIK_GRPH_CONTROL 0x6804
# define CIK_GRPH_DEPTH(x) (((x) & 0x3) << 0)
# define CIK_GRPH_DEPTH_8BPP 0
# define CIK_GRPH_DEPTH_16BPP 1
# define CIK_GRPH_DEPTH_32BPP 2
# define CIK_GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
# define CIK_ADDR_SURF_2_BANK 0
# define CIK_ADDR_SURF_4_BANK 1
# define CIK_ADDR_SURF_8_BANK 2
# define CIK_ADDR_SURF_16_BANK 3
# define CIK_GRPH_Z(x) (((x) & 0x3) << 4)
# define CIK_GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
# define CIK_ADDR_SURF_BANK_WIDTH_1 0
# define CIK_ADDR_SURF_BANK_WIDTH_2 1
# define CIK_ADDR_SURF_BANK_WIDTH_4 2
# define CIK_ADDR_SURF_BANK_WIDTH_8 3
# define CIK_GRPH_FORMAT(x) (((x) & 0x7) << 8)
/* 8 BPP */
# define CIK_GRPH_FORMAT_INDEXED 0
/* 16 BPP */
# define CIK_GRPH_FORMAT_ARGB1555 0
# define CIK_GRPH_FORMAT_ARGB565 1
# define CIK_GRPH_FORMAT_ARGB4444 2
# define CIK_GRPH_FORMAT_AI88 3
# define CIK_GRPH_FORMAT_MONO16 4
# define CIK_GRPH_FORMAT_BGRA5551 5
/* 32 BPP */
# define CIK_GRPH_FORMAT_ARGB8888 0
# define CIK_GRPH_FORMAT_ARGB2101010 1
# define CIK_GRPH_FORMAT_32BPP_DIG 2
# define CIK_GRPH_FORMAT_8B_ARGB2101010 3
# define CIK_GRPH_FORMAT_BGRA1010102 4
# define CIK_GRPH_FORMAT_8B_BGRA1010102 5
# define CIK_GRPH_FORMAT_RGB111110 6
# define CIK_GRPH_FORMAT_BGR101111 7
# define CIK_GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
# define CIK_ADDR_SURF_BANK_HEIGHT_1 0
# define CIK_ADDR_SURF_BANK_HEIGHT_2 1
# define CIK_ADDR_SURF_BANK_HEIGHT_4 2
# define CIK_ADDR_SURF_BANK_HEIGHT_8 3
# define CIK_GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)
# define CIK_ADDR_SURF_TILE_SPLIT_64B 0
# define CIK_ADDR_SURF_TILE_SPLIT_128B 1
# define CIK_ADDR_SURF_TILE_SPLIT_256B 2
# define CIK_ADDR_SURF_TILE_SPLIT_512B 3
# define CIK_ADDR_SURF_TILE_SPLIT_1KB 4
# define CIK_ADDR_SURF_TILE_SPLIT_2KB 5
# define CIK_ADDR_SURF_TILE_SPLIT_4KB 6
# define CIK_GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
# define CIK_ADDR_SURF_MACRO_TILE_ASPECT_1 0
# define CIK_ADDR_SURF_MACRO_TILE_ASPECT_2 1
# define CIK_ADDR_SURF_MACRO_TILE_ASPECT_4 2
# define CIK_ADDR_SURF_MACRO_TILE_ASPECT_8 3
# define CIK_GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
# define CIK_GRPH_ARRAY_LINEAR_GENERAL 0
# define CIK_GRPH_ARRAY_LINEAR_ALIGNED 1
# define CIK_GRPH_ARRAY_1D_TILED_THIN1 2
# define CIK_GRPH_ARRAY_2D_TILED_THIN1 4
# define CIK_GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24)
# define CIK_ADDR_SURF_P2 0
# define CIK_ADDR_SURF_P4_8x16 4
# define CIK_ADDR_SURF_P4_16x16 5
# define CIK_ADDR_SURF_P4_16x32 6
# define CIK_ADDR_SURF_P4_32x32 7
# define CIK_ADDR_SURF_P8_16x16_8x16 8
# define CIK_ADDR_SURF_P8_16x32_8x16 9
# define CIK_ADDR_SURF_P8_32x32_8x16 10
# define CIK_ADDR_SURF_P8_16x32_16x16 11
# define CIK_ADDR_SURF_P8_32x32_16x16 12
# define CIK_ADDR_SURF_P8_32x32_16x32 13
# define CIK_ADDR_SURF_P8_32x64_32x32 14
# define CIK_GRPH_MICRO_TILE_MODE(x) (((x) & 0x7) << 29)
# define CIK_DISPLAY_MICRO_TILING 0
# define CIK_THIN_MICRO_TILING 1
# define CIK_DEPTH_MICRO_TILING 2
# define CIK_ROTATED_MICRO_TILING 4
/* CUR blocks at 0x6998, 0x7598, 0x10198, 0x10d98, 0x11998, 0x12598 */
#define CIK_CUR_CONTROL 0x6998
# define CIK_CURSOR_EN (1 << 0)
......@@ -65,4 +142,6 @@
#define CIK_LB_DATA_FORMAT 0x6b00
# define CIK_INTERLEAVE_EN (1 << 3)
#define CIK_LB_DESKTOP_HEIGHT 0x6b0c
#endif
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