Commit 964a36d7 authored by Lang Yu's avatar Lang Yu Committed by Alex Deucher

drm/amdgpu: add PSP FW TYPE for VPE

Add PSP FW TYPE for Video Processing Engine.
Signed-off-by: default avatarLang Yu <Lang.Yu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4c63735f
...@@ -2390,6 +2390,12 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode, ...@@ -2390,6 +2390,12 @@ static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK: case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
*type = GFX_FW_TYPE_RS64_MEC_P3_STACK; *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
break; break;
case AMDGPU_UCODE_ID_VPE_CTX:
*type = GFX_FW_TYPE_VPEC_FW1;
break;
case AMDGPU_UCODE_ID_VPE_CTL:
*type = GFX_FW_TYPE_VPEC_FW2;
break;
case AMDGPU_UCODE_ID_MAXIMUM: case AMDGPU_UCODE_ID_MAXIMUM:
default: default:
return -EINVAL; return -EINVAL;
......
...@@ -293,6 +293,8 @@ enum psp_gfx_fw_type { ...@@ -293,6 +293,8 @@ enum psp_gfx_fw_type {
GFX_FW_TYPE_RS64_MEC_P1_STACK = 95, /* RS64 MEC stack P1 SOC21 */ GFX_FW_TYPE_RS64_MEC_P1_STACK = 95, /* RS64 MEC stack P1 SOC21 */
GFX_FW_TYPE_RS64_MEC_P2_STACK = 96, /* RS64 MEC stack P2 SOC21 */ GFX_FW_TYPE_RS64_MEC_P2_STACK = 96, /* RS64 MEC stack P2 SOC21 */
GFX_FW_TYPE_RS64_MEC_P3_STACK = 97, /* RS64 MEC stack P3 SOC21 */ GFX_FW_TYPE_RS64_MEC_P3_STACK = 97, /* RS64 MEC stack P3 SOC21 */
GFX_FW_TYPE_VPEC_FW1 = 100, /* VPEC FW1 To Save VPE */
GFX_FW_TYPE_VPEC_FW2 = 101, /* VPEC FW2 To Save VPE */
GFX_FW_TYPE_MAX GFX_FW_TYPE_MAX
}; };
......
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