Commit 96cd2dd6 authored by Lior Nahmanson's avatar Lior Nahmanson Committed by Leon Romanovsky

net/mlx5: Add DCS caps & fields support

This fields will be needed when adding a support for DCS offload

max_dci_stream_channels - maximum DCI stream channels supported per DCI.
max_dci_errored_streams - maximum DCI error stream channels
supported per DCI before a DCI move to error state.
Signed-off-by: default avatarLior Nahmanson <liorna@nvidia.com>
Signed-off-by: default avatarLeon Romanovsky <leonro@nvidia.com>
parent e73f0f0e
...@@ -1651,7 +1651,13 @@ struct mlx5_ifc_cmd_hca_cap_bits { ...@@ -1651,7 +1651,13 @@ struct mlx5_ifc_cmd_hca_cap_bits {
u8 max_geneve_tlv_option_data_len[0x5]; u8 max_geneve_tlv_option_data_len[0x5];
u8 reserved_at_570[0x10]; u8 reserved_at_570[0x10];
u8 reserved_at_580[0x33]; u8 reserved_at_580[0xb];
u8 log_max_dci_stream_channels[0x5];
u8 reserved_at_590[0x3];
u8 log_max_dci_errored_streams[0x5];
u8 reserved_at_598[0x8];
u8 reserved_at_5a0[0x13];
u8 log_max_dek[0x5]; u8 log_max_dek[0x5];
u8 reserved_at_5b8[0x4]; u8 reserved_at_5b8[0x4];
u8 mini_cqe_resp_stride_index[0x1]; u8 mini_cqe_resp_stride_index[0x1];
...@@ -3020,10 +3026,12 @@ struct mlx5_ifc_qpc_bits { ...@@ -3020,10 +3026,12 @@ struct mlx5_ifc_qpc_bits {
u8 reserved_at_3c0[0x8]; u8 reserved_at_3c0[0x8];
u8 next_send_psn[0x18]; u8 next_send_psn[0x18];
u8 reserved_at_3e0[0x8]; u8 reserved_at_3e0[0x3];
u8 log_num_dci_stream_channels[0x5];
u8 cqn_snd[0x18]; u8 cqn_snd[0x18];
u8 reserved_at_400[0x8]; u8 reserved_at_400[0x3];
u8 log_num_dci_errored_streams[0x5];
u8 deth_sqpn[0x18]; u8 deth_sqpn[0x18];
u8 reserved_at_420[0x20]; u8 reserved_at_420[0x20];
......
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