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Commit 9bf3fc50 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'devicetree-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 

Pull devicetree updates from Rob Herring:

 - Add Krzysztof Kozlowski as co-maintainer for DT bindings providing
   much needed help.

 - DT schema validation now takes DTB files as input rather than
   intermediate YAML files. This decouples the validation from the
   source level syntax information. There's a bunch of schema fixes as a
   result of switching to DTB based validation which exposed some errors
   and incomplete schemas and examples.

 - Kbuild improvements to explicitly warn users running 'make
   dt_binding_check' on missing yamllint

 - Expand DT_SCHEMA_FILES kbuild variable to take just a partial
   filename or path instead of the full path to 1 file.

 - Convert various bindings to schema format: mscc,vsc7514-switch,
   multiple GNSS bindings, ahci-platform, i2c-at91, multiple UFS
   bindings, cortina,gemini-sata-bridge, cortina,gemini-ethernet, Atmel
   SHA, Atmel TDES, Atmel AES, armv7m-systick, Samsung Exynos display
   subsystem, nuvoton,npcm7xx-timer, samsung,s3c2410-i2c, zynqmp_dma,
   msm/mdp4, rda,8810pl-uart

 - New schemas for u-boot environment variable partition, TI clksel

 - New compatible strings for Renesas RZ/V2L SoC

 - Vendor prefixes for Xen, HPE, deprecated Synopsys, deprecated
   HiSilicon

 - Add/fix schemas for QEMU Arm 'virt' machine

 - Drop unused of_alias_get_alias_list() function

 - Add a script to check DT unittest EXPECT message output. Pass
   messages also now print by default at PR_INFO level to help test
   automation.

* tag 'devicetree-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (96 commits)
  dt-bindings: kbuild: Make DT_SCHEMA_LINT a recursive variable
  dt-bindings: nvmem: add U-Boot environment variables binding
  dt-bindings: ufs: qcom: Add SM6350 compatible string
  dt-bindings: dmaengine: sifive,fu540-c000: include generic schema
  dt-bindings: gpio: pca95xx: drop useless consumer example
  Revert "of: base: Introduce of_alias_get_alias_list() to check alias IDs"
  dt-bindings: virtio,mmio: Allow setting devices 'dma-coherent'
  dt-bindings: gnss: Add two more chips
  dt-bindings: gnss: Rewrite sirfstar binding in YAML
  dt-bindings: gnss: Modify u-blox to use common bindings
  dt-bindings: gnss: Rewrite common bindings in YAML
  dt-bindings: ata: ahci-platform: Add rk3568-dwc-ahci compatible
  dt-bindings: ata: ahci-platform: Add power-domains property
  dt-bindings: ata: ahci-platform: Convert DT bindings to yaml
  dt-bindings: kbuild: Use DTB files for validation
  dt-bindings: kbuild: Pass DT_SCHEMA_FILES to dt-validate
  dt-bindings: Add QEMU virt machine compatible
  dt-bindings: arm: Convert QEMU fw-cfg to DT schema
  dt-bindings: i2c: at91: Add SAMA7G5 compatible strings list
  dt-bindings: i2c: convert i2c-at91 to json-schema
  ...
parents bddac7c1 6b49f340
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Showing with 4441 additions and 2034 deletions
Documentation/devicetree/bindings/Makefile
View file @ 9bf3fc50
......@@ -3,9 +3,10 @@ DT_DOC_CHECKER ?= dt-doc-validate
DT_EXTRACT_EX ?= dt-extract-example
DT_MK_SCHEMA ?= dt-mk-schema
DT_SCHEMA_LINT = $(shell which yamllint)
DT_SCHEMA_LINT = $(shell which yamllint || \
echo "warning: python package 'yamllint' not installed, skipping" >&2)
DT_SCHEMA_MIN_VERSION = 2021.2.1
DT_SCHEMA_MIN_VERSION = 2022.3
PHONY += check_dtschema_version
check_dtschema_version:
......@@ -24,18 +25,11 @@ quiet_cmd_extract_ex = DTEX $@
$(obj)/%.example.dts: $(src)/%.yaml check_dtschema_version FORCE
$(call if_changed,extract_ex)
# Use full schemas when checking %.example.dts
DT_TMP_SCHEMA := $(obj)/processed-schema-examples.json
find_all_cmd = find $(srctree)/$(src) \( -name '*.yaml' ! \
-name 'processed-schema*' ! \
-name '*.example.dt.yaml' \)
-name 'processed-schema*' \)
ifeq ($(DT_SCHEMA_FILES),)
find_cmd = $(find_all_cmd)
else
find_cmd = echo $(addprefix $(srctree)/, $(DT_SCHEMA_FILES))
endif
find_cmd = $(find_all_cmd) | grep -F "$(DT_SCHEMA_FILES)"
CHK_DT_DOCS := $(shell $(find_cmd))
quiet_cmd_yamllint = LINT $(src)
cmd_yamllint = ($(find_cmd) | \
......@@ -72,35 +66,14 @@ override DTC_FLAGS := \
# Disable undocumented compatible checks until warning free
override DT_CHECKER_FLAGS ?=
$(obj)/processed-schema-examples.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE
$(obj)/processed-schema.json: $(DT_DOCS) $(src)/.yamllint check_dtschema_version FORCE
$(call if_changed_rule,chkdt)
ifeq ($(DT_SCHEMA_FILES),)
# Unless DT_SCHEMA_FILES is specified, use the full schema for dtbs_check too.
# Just copy processed-schema-examples.json
$(obj)/processed-schema.json: $(obj)/processed-schema-examples.json FORCE
$(call if_changed,copy)
DT_SCHEMA_FILES = $(DT_DOCS)
else
# If DT_SCHEMA_FILES is specified, use it for processed-schema.json
$(obj)/processed-schema.json: DT_MK_SCHEMA_FLAGS := -u
$(obj)/processed-schema.json: $(DT_SCHEMA_FILES) check_dtschema_version FORCE
$(call if_changed,mk_schema)
endif
always-$(CHECK_DT_BINDING) += processed-schema-examples.json
always-$(CHECK_DTBS) += processed-schema.json
always-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dts, $(DT_SCHEMA_FILES))
always-$(CHECK_DT_BINDING) += $(patsubst $(src)/%.yaml,%.example.dt.yaml, $(DT_SCHEMA_FILES))
always-y += processed-schema.json
always-$(CHECK_DT_BINDING) += $(patsubst $(srctree)/$(src)/%.yaml,%.example.dts, $(CHK_DT_DOCS))
always-$(CHECK_DT_BINDING) += $(patsubst $(srctree)/$(src)/%.yaml,%.example.dtb, $(CHK_DT_DOCS))
# Hack: avoid 'Argument list too long' error for 'make clean'. Remove most of
# build artifacts here before they are processed by scripts/Makefile.clean
clean-files = $(shell find $(obj) \( -name '*.example.dts' -o \
-name '*.example.dt.yaml' \) -delete 2>/dev/null)
-name '*.example.dtb' \) -delete 2>/dev/null)
Documentation/devicetree/bindings/arm/arm,cci-400.yaml
View file @ 9bf3fc50
......@@ -119,6 +119,11 @@ examples:
arm,hbi = <0x249>;
interrupt-parent = <&gic>;
gic: interrupt-controller {
interrupt-controller;
#interrupt-cells = <3>;
};
/*
* This CCI node corresponds to a CCI component whose control
* registers sits at address 0x000000002c090000.
......
Documentation/devicetree/bindings/arm/cpu-capacity.txt
View file @ 9bf3fc50
......@@ -62,8 +62,8 @@ Example 1 (ARM 64-bit, 6-cpu system, two clusters):
The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
are 1024 and 578 for cluster0 and cluster1. Further normalization
is done by the operating system based on cluster0@max-freq=1100 and
custer1@max-freq=850, final capacities are 1024 for cluster0 and
446 for cluster1 (576*850/1100).
cluster1@max-freq=850, final capacities are 1024 for cluster0 and
446 for cluster1 (578*850/1100).
cpus {
#address-cells = <2>;
......
Documentation/devicetree/bindings/arm/cpus.yaml
View file @ 9bf3fc50
......@@ -233,17 +233,19 @@ properties:
- ti,am4372
cpu-release-addr:
$ref: '/schemas/types.yaml#/definitions/uint64'
oneOf:
- $ref: '/schemas/types.yaml#/definitions/uint32'
- $ref: '/schemas/types.yaml#/definitions/uint64'
description:
The DT specification defines this as 64-bit always, but some 32-bit Arm
systems have used a 32-bit value which must be supported.
Required for systems that have an "enable-method"
property value of "spin-table".
On ARM v8 64-bit systems must be a two cell
property identifying a 64-bit zero-initialised
memory location.
cpu-idle-states:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
items:
maxItems: 1
description: |
List of phandles to idle state nodes supported
by this cpu (see ./idle-states.yaml).
......
Documentation/devicetree/bindings/arm/fw-cfg.txt deleted 100644 → 0
View file @ bddac7c1
* QEMU Firmware Configuration bindings for ARM
QEMU's arm-softmmu and aarch64-softmmu emulation / virtualization targets
provide the following Firmware Configuration interface on the "virt" machine
type:
- A write-only, 16-bit wide selector (or control) register,
- a read-write, 64-bit wide data register.
QEMU exposes the control and data register to ARM guests as memory mapped
registers; their location is communicated to the guest's UEFI firmware in the
DTB that QEMU places at the bottom of the guest's DRAM.
The authoritative guest-side hardware interface documentation to the fw_cfg
device can be found in "docs/specs/fw_cfg.txt" in the QEMU source tree.
Required properties:
- compatible: "qemu,fw-cfg-mmio".
- reg: the MMIO region used by the device.
* Bytes 0x0 to 0x7 cover the data register.
* Bytes 0x8 to 0x9 cover the selector register.
* Further registers may be appended to the region in case of future interface
revisions / feature bits.
Example:
/ {
#size-cells = <0x2>;
#address-cells = <0x2>;
fw-cfg@9020000 {
compatible = "qemu,fw-cfg-mmio";
reg = <0x0 0x9020000 0x0 0xa>;
};
};
Documentation/devicetree/bindings/arm/idle-states.yaml
View file @ 9bf3fc50
......@@ -337,8 +337,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@1 {
......@@ -346,8 +346,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@100 {
......@@ -355,8 +355,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@101 {
......@@ -364,8 +364,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@10000 {
......@@ -373,8 +373,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x10000>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@10001 {
......@@ -382,8 +382,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x10001>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@10100 {
......@@ -391,8 +391,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x10100>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@10101 {
......@@ -400,8 +400,8 @@ examples:
compatible = "arm,cortex-a57";
reg = <0x0 0x10101>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
&CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
cpu-idle-states = <&CPU_RETENTION_0_0>, <&CPU_SLEEP_0_0>,
<&CLUSTER_RETENTION_0>, <&CLUSTER_SLEEP_0>;
};
cpu@100000000 {
......@@ -409,8 +409,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100000001 {
......@@ -418,8 +418,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100000100 {
......@@ -427,8 +427,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100000101 {
......@@ -436,8 +436,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100010000 {
......@@ -445,8 +445,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x10000>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100010001 {
......@@ -454,8 +454,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x10001>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100010100 {
......@@ -463,8 +463,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x10100>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
cpu@100010101 {
......@@ -472,8 +472,8 @@ examples:
compatible = "arm,cortex-a53";
reg = <0x1 0x10101>;
enable-method = "psci";
cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
&CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
cpu-idle-states = <&CPU_RETENTION_1_0>, <&CPU_SLEEP_1_0>,
<&CLUSTER_RETENTION_1>, <&CLUSTER_SLEEP_1>;
};
idle-states {
......@@ -567,56 +567,56 @@ examples:
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x2>;
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x3>;
cpu-idle-states = <&cpu_sleep_0_0 &cluster_sleep_0>;
cpu-idle-states = <&cpu_sleep_0_0>, <&cluster_sleep_0>;
};
cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x100>;
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
};
cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
};
cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
};
cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x103>;
cpu-idle-states = <&cpu_sleep_1_0 &cluster_sleep_1>;
cpu-idle-states = <&cpu_sleep_1_0>, <&cluster_sleep_1>;
};
idle-states {
......
Documentation/devicetree/bindings/arm/linux,dummy-virt.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/linux,dummy-virt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: QEMU virt machine
maintainers:
- Rob Herring <robh@kernel.org>
properties:
$nodename:
const: "/"
compatible:
const: linux,dummy-virt
additionalProperties: true
...
Documentation/devicetree/bindings/arm/pmu.yaml
View file @ 9bf3fc50
......@@ -68,6 +68,8 @@ properties:
interrupt-affinity:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description:
When using SPIs, specifies a list of phandles to CPU
nodes corresponding directly to the affinity of
......
Documentation/devicetree/bindings/ata/ahci-platform.txt deleted 100644 → 0
View file @ bddac7c1
* AHCI SATA Controller
SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.
It is possible, but not required, to represent each port as a sub-node.
It allows to enable each port independently when dealing with multiple
PHYs.
Required properties:
- compatible : compatible string, one of:
- "brcm,iproc-ahci"
- "hisilicon,hisi-ahci"
- "cavium,octeon-7130-ahci"
- "ibm,476gtr-ahci"
- "marvell,armada-380-ahci"
- "marvell,armada-3700-ahci"
- "snps,dwc-ahci"
- "snps,spear-ahci"
- "generic-ahci"
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>
Please note that when using "generic-ahci" you must also specify a SoC specific
compatible:
compatible = "manufacturer,soc-model-ahci", "generic-ahci";
Optional properties:
- dma-coherent : Present if dma operations are coherent
- clocks : a list of phandle + clock specifier pairs
- resets : a list of phandle + reset specifier pairs
- target-supply : regulator for SATA target power
- phy-supply : regulator for PHY power
- phys : reference to the SATA PHY node
- phy-names : must be "sata-phy"
- ahci-supply : regulator for AHCI controller
- ports-implemented : Mask that indicates which ports that the HBA supports
are available for software to use. Useful if PORTS_IMPL
is not programmed by the BIOS, which is true with
some embedded SOC's.
Required properties when using sub-nodes:
- #address-cells : number of cells to encode an address
- #size-cells : number of cells representing the size of an address
Sub-nodes required properties:
- reg : the port number
And at least one of the following properties:
- phys : reference to the SATA PHY node
- target-supply : regulator for SATA target power
Examples:
sata@ffe08000 {
compatible = "snps,spear-ahci";
reg = <0xffe08000 0x1000>;
interrupts = <115>;
};
With sub-nodes:
sata@f7e90000 {
compatible = "marvell,berlin2q-achi", "generic-ahci";
reg = <0xe90000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip CLKID_SATA>;
#address-cells = <1>;
#size-cells = <0>;
sata0: sata-port@0 {
reg = <0>;
phys = <&sata_phy 0>;
target-supply = <&reg_sata0>;
};
sata1: sata-port@1 {
reg = <1>;
phys = <&sata_phy 1>;
target-supply = <&reg_sata1>;;
};
};
Documentation/devicetree/bindings/ata/ahci-platform.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: AHCI SATA Controller
description: |
SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.
It is possible, but not required, to represent each port as a sub-node.
It allows to enable each port independently when dealing with multiple
PHYs.
maintainers:
- Hans de Goede <hdegoede@redhat.com>
- Jens Axboe <axboe@kernel.dk>
select:
properties:
compatible:
contains:
enum:
- brcm,iproc-ahci
- cavium,octeon-7130-ahci
- hisilicon,hisi-ahci
- ibm,476gtr-ahci
- marvell,armada-3700-ahci
- marvell,armada-8k-ahci
- marvell,berlin2q-ahci
- snps,dwc-ahci
- snps,spear-ahci
required:
- compatible
allOf:
- $ref: "sata-common.yaml#"
properties:
compatible:
oneOf:
- items:
- enum:
- brcm,iproc-ahci
- marvell,armada-8k-ahci
- marvell,berlin2-ahci
- marvell,berlin2q-ahci
- const: generic-ahci
- items:
- enum:
- rockchip,rk3568-dwc-ahci
- const: snps,dwc-ahci
- enum:
- cavium,octeon-7130-ahci
- hisilicon,hisi-ahci
- ibm,476gtr-ahci
- marvell,armada-3700-ahci
- snps,dwc-ahci
- snps,spear-ahci
reg:
minItems: 1
maxItems: 2
reg-names:
maxItems: 1
clocks:
description:
Clock IDs array as required by the controller.
minItems: 1
maxItems: 3
clock-names:
description:
Names of clocks corresponding to IDs in the clock property.
minItems: 1
maxItems: 3
interrupts:
maxItems: 1
ahci-supply:
description:
regulator for AHCI controller
dma-coherent: true
phy-supply:
description:
regulator for PHY power
phys:
description:
List of all PHYs on this controller
maxItems: 1
phy-names:
description:
Name specifier for the PHYs
maxItems: 1
ports-implemented:
$ref: '/schemas/types.yaml#/definitions/uint32'
description: |
Mask that indicates which ports that the HBA supports
are available for software to use. Useful if PORTS_IMPL
is not programmed by the BIOS, which is true with
some embedded SoCs.
maximum: 0x1f
power-domains:
maxItems: 1
resets:
maxItems: 1
target-supply:
description:
regulator for SATA target power
required:
- compatible
- reg
- interrupts
patternProperties:
"^sata-port@[0-9a-f]+$":
type: object
additionalProperties: false
description:
Subnode with configuration of the Ports.
properties:
reg:
maxItems: 1
phys:
maxItems: 1
phy-names:
maxItems: 1
target-supply:
description:
regulator for SATA target power
required:
- reg
anyOf:
- required: [ phys ]
- required: [ target-supply ]
unevaluatedProperties: false
examples:
- |
sata@ffe08000 {
compatible = "snps,spear-ahci";
reg = <0xffe08000 0x1000>;
interrupts = <115>;
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/berlin2q.h>
sata@f7e90000 {
compatible = "marvell,berlin2q-ahci", "generic-ahci";
reg = <0xf7e90000 0x1000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&chip CLKID_SATA>;
#address-cells = <1>;
#size-cells = <0>;
sata0: sata-port@0 {
reg = <0>;
phys = <&sata_phy 0>;
target-supply = <&reg_sata0>;
};
sata1: sata-port@1 {
reg = <1>;
phys = <&sata_phy 1>;
target-supply = <&reg_sata1>;
};
};
Documentation/devicetree/bindings/ata/cortina,gemini-sata-bridge.txt deleted 100644 → 0
View file @ bddac7c1
* Cortina Systems Gemini SATA Bridge
The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
takes two Faraday Technology FTIDE010 PATA controllers and bridges
them in different configurations to two SATA ports.
Required properties:
- compatible: should be
"cortina,gemini-sata-bridge"
- reg: registers and size for the block
- resets: phandles to the reset lines for both SATA bridges
- reset-names: must be "sata0", "sata1"
- clocks: phandles to the compulsory peripheral clocks
- clock-names: must be "SATA0_PCLK", "SATA1_PCLK"
- syscon: a phandle to the global Gemini system controller
- cortina,gemini-ata-muxmode: tell the desired multiplexing mode for
the ATA controller and SATA bridges. Values 0..3:
Mode 0: ata0 master <-> sata0
ata1 master <-> sata1
ata0 slave interface brought out on IDE pads
Mode 1: ata0 master <-> sata0
ata1 master <-> sata1
ata1 slave interface brought out on IDE pads
Mode 2: ata1 master <-> sata1
ata1 slave <-> sata0
ata0 master and slave interfaces brought out
on IDE pads
Mode 3: ata0 master <-> sata0
ata0 slave <-> sata1
ata1 master and slave interfaces brought out
on IDE pads
Optional boolean properties:
- cortina,gemini-enable-ide-pins: enables the PATA to IDE connection.
The muxmode setting decides whether ATA0 or ATA1 is brought out,
and whether master, slave or both interfaces get brought out.
- cortina,gemini-enable-sata-bridge: enables the PATA to SATA bridge
inside the Gemnini SoC. The Muxmode decides what PATA blocks will
be muxed out and how.
Example:
sata: sata@46000000 {
compatible = "cortina,gemini-sata-bridge";
reg = <0x46000000 0x100>;
resets = <&rcon 26>, <&rcon 27>;
reset-names = "sata0", "sata1";
clocks = <&gcc GEMINI_CLK_GATE_SATA0>,
<&gcc GEMINI_CLK_GATE_SATA1>;
clock-names = "SATA0_PCLK", "SATA1_PCLK";
syscon = <&syscon>;
cortina,gemini-ata-muxmode = <3>;
cortina,gemini-enable-ide-pins;
cortina,gemini-enable-sata-bridge;
};
Documentation/devicetree/bindings/ata/cortina,gemini-sata-bridge.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/cortina,gemini-sata-bridge.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cortina Systems Gemini SATA Bridge
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: |
The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
takes two Faraday Technology FTIDE010 PATA controllers and bridges
them in different configurations to two SATA ports.
properties:
compatible:
const: cortina,gemini-sata-bridge
reg:
maxItems: 1
resets:
minItems: 2
maxItems: 2
description: phandles to the reset lines for both SATA bridges
reset-names:
items:
- const: sata0
- const: sata1
clocks:
minItems: 2
maxItems: 2
description: phandles to the compulsory peripheral clocks
clock-names:
items:
- const: SATA0_PCLK
- const: SATA1_PCLK
syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description: a phandle to the global Gemini system controller
cortina,gemini-ata-muxmode:
$ref: /schemas/types.yaml#/definitions/uint32
enum:
- 0
- 1
- 2
- 3
description: |
Tell the desired multiplexing mode for the ATA controller and SATA
bridges.
Mode 0: ata0 master <-> sata0
ata1 master <-> sata1
ata0 slave interface brought out on IDE pads
Mode 1: ata0 master <-> sata0
ata1 master <-> sata1
ata1 slave interface brought out on IDE pads
Mode 2: ata1 master <-> sata1
ata1 slave <-> sata0
ata0 master and slave interfaces brought out on IDE pads
Mode 3: ata0 master <-> sata0
ata0 slave <-> sata1
ata1 master and slave interfaces brought out on IDE pads
cortina,gemini-enable-ide-pins:
type: boolean
description: Enables the PATA to IDE connection.
The muxmode setting decides whether ATA0 or ATA1 is brought out,
and whether master, slave or both interfaces get brought out.
cortina,gemini-enable-sata-bridge:
type: boolean
description: Enables the PATA to SATA bridge inside the Gemnini SoC.
The Muxmode decides what PATA blocks will be muxed out and how.
required:
- clocks
- clock-names
- cortina,gemini-ata-muxmode
- resets
- reset-names
- compatible
- reg
- syscon
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/cortina,gemini-clock.h>
sata@46000000 {
compatible = "cortina,gemini-sata-bridge";
reg = <0x46000000 0x100>;
resets = <&rcon 26>, <&rcon 27>;
reset-names = "sata0", "sata1";
clocks = <&gcc GEMINI_CLK_GATE_SATA0>,
<&gcc GEMINI_CLK_GATE_SATA1>;
clock-names = "SATA0_PCLK", "SATA1_PCLK";
syscon = <&syscon>;
cortina,gemini-ata-muxmode = <3>;
cortina,gemini-enable-ide-pins;
cortina,gemini-enable-sata-bridge;
};
Documentation/devicetree/bindings/ata/sata_highbank.yaml
View file @ 9bf3fc50
......@@ -51,6 +51,9 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 8
items:
minItems: 2
maxItems: 2
calxeda,tx-atten:
description: |
......
Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml
View file @ 9bf3fc50
......@@ -35,7 +35,10 @@ properties:
The SRAM that needs to be claimed to access the display engine
bus.
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
items:
- items:
- description: phandle to SRAM
- description: register value for device
ranges: true
......
Documentation/devicetree/bindings/clock/ti/ti,clksel.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/ti/ti,clksel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Binding for TI clksel clock
maintainers:
- Tony Lindgren <tony@atomide.com>
description: |
The TI CLKSEL clocks consist of consist of input clock mux bits, and in some
cases also has divider, multiplier and gate bits.
properties:
compatible:
const: ti,clksel
reg:
maxItems: 1
description: The CLKSEL register range
'#address-cells':
enum: [ 0, 1, 2 ]
'#size-cells':
enum: [ 0, 1, 2 ]
ranges: true
"#clock-cells":
const: 2
description: The CLKSEL register and bit offset
required:
- compatible
- reg
- "#clock-cells"
additionalProperties:
type: object
examples:
- |
clksel_gfx_fclk: clock@52c {
compatible = "ti,clksel";
reg = <0x25c 0x4>;
#clock-cells = <2>;
};
...
Documentation/devicetree/bindings/connector/usb-connector.yaml
View file @ 9bf3fc50
......@@ -104,8 +104,7 @@ properties:
- "1.5A" and "3.0A", 5V 1.5A and 5V 3.0A respectively, as defined in USB
Type-C Cable and Connector specification, when Power Delivery is not
supported.
allOf:
- $ref: /schemas/types.yaml#/definitions/string
$ref: /schemas/types.yaml#/definitions/string
enum:
- default
- 1.5A
......
Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-aes.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel Advanced Encryption Standard (AES) HW cryptographic accelerator
maintainers:
- Tudor Ambarus <tudor.ambarus@microchip.com>
properties:
compatible:
const: atmel,at91sam9g46-aes
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: aes_clk
dmas:
items:
- description: TX DMA Channel
- description: RX DMA Channel
dma-names:
items:
- const: tx
- const: rx
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- dmas
- dma-names
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/dma/at91.h>
aes: crypto@e1810000 {
compatible = "atmel,at91sam9g46-aes";
reg = <0xe1810000 0x100>;
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
clock-names = "aes_clk";
dmas = <&dma0 AT91_XDMAC_DT_PERID(1)>,
<&dma0 AT91_XDMAC_DT_PERID(2)>;
dma-names = "tx", "rx";
};
Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-sha.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel Secure Hash Algorithm (SHA) HW cryptographic accelerator
maintainers:
- Tudor Ambarus <tudor.ambarus@microchip.com>
properties:
compatible:
const: atmel,at91sam9g46-sha
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: sha_clk
dmas:
maxItems: 1
description: TX DMA Channel
dma-names:
const: tx
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/dma/at91.h>
sha: crypto@e1814000 {
compatible = "atmel,at91sam9g46-sha";
reg = <0xe1814000 0x100>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 83>;
clock-names = "sha_clk";
dmas = <&dma0 AT91_XDMAC_DT_PERID(48)>;
dma-names = "tx";
};
Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/atmel,at91sam9g46-tdes.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel Triple Data Encryption Standard (TDES) HW cryptographic accelerator
maintainers:
- Tudor Ambarus <tudor.ambarus@microchip.com>
properties:
compatible:
const: atmel,at91sam9g46-tdes
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: tdes_clk
dmas:
items:
- description: TX DMA Channel
- description: RX DMA Channel
dma-names:
items:
- const: tx
- const: rx
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/dma/at91.h>
tdes: crypto@e2014000 {
compatible = "atmel,at91sam9g46-tdes";
reg = <0xe2014000 0x100>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 96>;
clock-names = "tdes_clk";
dmas = <&dma0 AT91_XDMAC_DT_PERID(54)>,
<&dma0 AT91_XDMAC_DT_PERID(53)>;
dma-names = "tx", "rx";
};
Documentation/devicetree/bindings/crypto/atmel-crypto.txt deleted 100644 → 0
View file @ bddac7c1
* Atmel HW cryptographic accelerators
These are the HW cryptographic accelerators found on some Atmel products.
* Advanced Encryption Standard (AES)
Required properties:
- compatible : Should be "atmel,at91sam9g46-aes".
- reg: Should contain AES registers location and length.
- interrupts: Should contain the IRQ line for the AES.
- dmas: List of two DMA specifiers as described in
atmel-dma.txt and dma.txt files.
- dma-names: Contains one identifier string for each DMA specifier
in the dmas property.
Example:
aes@f8038000 {
compatible = "atmel,at91sam9g46-aes";
reg = <0xf8038000 0x100>;
interrupts = <43 4 0>;
dmas = <&dma1 2 18>,
<&dma1 2 19>;
dma-names = "tx", "rx";
* Triple Data Encryption Standard (Triple DES)
Required properties:
- compatible : Should be "atmel,at91sam9g46-tdes".
- reg: Should contain TDES registers location and length.
- interrupts: Should contain the IRQ line for the TDES.
Optional properties:
- dmas: List of two DMA specifiers as described in
atmel-dma.txt and dma.txt files.
- dma-names: Contains one identifier string for each DMA specifier
in the dmas property.
Example:
tdes@f803c000 {
compatible = "atmel,at91sam9g46-tdes";
reg = <0xf803c000 0x100>;
interrupts = <44 4 0>;
dmas = <&dma1 2 20>,
<&dma1 2 21>;
dma-names = "tx", "rx";
};
* Secure Hash Algorithm (SHA)
Required properties:
- compatible : Should be "atmel,at91sam9g46-sha".
- reg: Should contain SHA registers location and length.
- interrupts: Should contain the IRQ line for the SHA.
Optional properties:
- dmas: One DMA specifiers as described in
atmel-dma.txt and dma.txt files.
- dma-names: Contains one identifier string for each DMA specifier
in the dmas property. Only one "tx" string needed.
Example:
sha@f8034000 {
compatible = "atmel,at91sam9g46-sha";
reg = <0xf8034000 0x100>;
interrupts = <42 4 0>;
dmas = <&dma1 2 17>;
dma-names = "tx";
};
Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
View file @ 9bf3fc50
......@@ -22,19 +22,28 @@ properties:
intel,npe-handle:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
maxItems: 1
items:
- items:
- description: phandle to the NPE this crypto engine
- description: the NPE instance number
description: phandle to the NPE this crypto engine is using, the cell
describing the NPE instance to be used.
queue-rx:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
items:
- items:
- description: phandle to the RX queue on the NPE
- description: the queue instance number
description: phandle to the RX queue on the NPE, the cell describing
the queue instance to be used.
queue-txready:
$ref: /schemas/types.yaml#/definitions/phandle-array
maxItems: 1
items:
- items:
- description: phandle to the TX READY queue on the NPE
- description: the queue instance number
description: phandle to the TX READY queue on the NPE, the cell describing
the queue instance to be used.
......
Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml
View file @ 9bf3fc50
......@@ -69,6 +69,8 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 2
items:
maxItems: 1
description: |
Available display engine frontends (DE 1.0) or mixers (DE
2.0/3.0) available.
......
Documentation/devicetree/bindings/display/brcm,bcm2711-hdmi.yaml
View file @ 9bf3fc50
......@@ -72,8 +72,7 @@ properties:
- const: hpd-removed
ddc:
allOf:
- $ref: /schemas/types.yaml#/definitions/phandle
$ref: /schemas/types.yaml#/definitions/phandle
description: >
Phandle of the I2C controller used for DDC EDID probing
......
Documentation/devicetree/bindings/display/bridge/adi,adv7511.yaml
View file @ 9bf3fc50
......@@ -76,9 +76,8 @@ properties:
adi,input-depth:
description: Number of bits per color component at the input.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [ 8, 10, 12 ]
$ref: /schemas/types.yaml#/definitions/uint32
enum: [ 8, 10, 12 ]
adi,input-colorspace:
description: Input color space.
......
Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml
View file @ 9bf3fc50
......@@ -26,9 +26,8 @@ properties:
reg-io-width:
description:
Width (in bytes) of the registers specified by the reg property.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [1, 4]
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 4]
default: 1
clocks:
......
Documentation/devicetree/bindings/display/bridge/toshiba,tc358768.yaml
View file @ 9bf3fc50
......@@ -77,7 +77,10 @@ required:
- vddio-supply
- ports
additionalProperties: false
allOf:
- $ref: ../dsi-controller.yaml#
unevaluatedProperties: false
examples:
- |
......@@ -87,7 +90,7 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
dsi_bridge: dsi-bridge@e {
dsi_bridge: dsi@e {
compatible = "toshiba,tc358768";
reg = <0xe>;
......
Documentation/devicetree/bindings/display/exynos/exynos-mic.txt deleted 100644 → 0
View file @ bddac7c1
Device-Tree bindings for Samsung Exynos SoC mobile image compressor (MIC)
MIC (mobile image compressor) resides between decon and mipi dsi. Mipi dsi is
not capable to transfer high resoltuion frame data as decon can send. MIC
solves this problem by compressing the frame data by 1/2 before it is
transferred through mipi dsi. The compressed frame data must be uncompressed in
the panel PCB.
Required properties:
- compatible: value should be "samsung,exynos5433-mic".
- reg: physical base address and length of the MIC registers set and system
register of mic.
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
- clock-names: list of clock names sorted in the same order as the clocks
property. Must contain "pclk_mic0", "sclk_rgb_vclk_to_mic0".
- samsung,disp-syscon: the reference node for syscon for DISP block.
- ports: contains a port which is connected to decon node and dsi node.
address-cells and size-cells must 1 and 0, respectively.
- port: contains an endpoint node which is connected to the endpoint in the
decon node or dsi node. The reg value must be 0 and 1 respectively.
Example:
SoC specific DT entry:
mic: mic@13930000 {
compatible = "samsung,exynos5433-mic";
reg = <0x13930000 0x48>;
clocks = <&cmu_disp CLK_PCLK_MIC0>,
<&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
samsung,disp-syscon = <&syscon_disp>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mic_to_decon: endpoint {
remote-endpoint = <&decon_to_mic>;
};
};
port@1 {
reg = <1>;
mic_to_dsi: endpoint {
remote-endpoint = <&dsi_to_mic>;
};
};
};
};
Documentation/devicetree/bindings/display/exynos/exynos5433-decon.txt deleted 100644 → 0
View file @ bddac7c1
Device-Tree bindings for Samsung Exynos SoC display controller (DECON)
DECON (Display and Enhancement Controller) is the Display Controller for the
Exynos series of SoCs which transfers the image data from a video memory
buffer to an external LCD interface.
Required properties:
- compatible: value should be one of:
"samsung,exynos5433-decon", "samsung,exynos5433-decon-tv";
- reg: physical base address and length of the DECON registers set.
- interrupt-names: should contain the interrupt names depending on mode of work:
video mode: "vsync",
command mode: "lcd_sys",
command mode with software trigger: "lcd_sys", "te".
- interrupts or interrupts-extended: list of interrupt specifiers corresponding
to names privided in interrupt-names, as described in
interrupt-controller/interrupts.txt
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
- clock-names: list of clock names sorted in the same order as the clocks
property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x",
"aclk_xiu_decon0x", "pclk_smmu_decon0x", "aclk_smmu_decon1x",
"aclk_xiu_decon1x", "pclk_smmu_decon1x", clk_decon_vclk",
"sclk_decon_eclk"
- ports: contains a port which is connected to mic node. address-cells and
size-cells must 1 and 0, respectively.
- port: contains an endpoint node which is connected to the endpoint in the mic
node. The reg value muset be 0.
Example:
SoC specific DT entry:
decon: decon@13800000 {
compatible = "samsung,exynos5433-decon";
reg = <0x13800000 0x2104>;
clocks = <&cmu_disp CLK_ACLK_DECON>, <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
<&cmu_disp CLK_ACLK_XIU_DECON0X>,
<&cmu_disp CLK_PCLK_SMMU_DECON0X>,
<&cmu_disp CLK_ACLK_SMMU_DECON1X>,
<&cmu_disp CLK_ACLK_XIU_DECON1X>,
<&cmu_disp CLK_PCLK_SMMU_DECON1X>,
<&cmu_disp CLK_SCLK_DECON_VCLK>,
<&cmu_disp CLK_SCLK_DECON_ECLK>;
clock-names = "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x",
"pclk_smmu_decon0x", "aclk_smmu_decon1x", "aclk_xiu_decon1x",
"pclk_smmu_decon1x", "sclk_decon_vclk", "sclk_decon_eclk";
interrupt-names = "vsync", "lcd_sys";
interrupts = <0 202 0>, <0 203 0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
decon_to_mic: endpoint {
remote-endpoint = <&mic_to_decon>;
};
};
};
};
Documentation/devicetree/bindings/display/exynos/exynos7-decon.txt deleted 100644 → 0
View file @ bddac7c1
Device-Tree bindings for Samsung Exynos7 SoC display controller (DECON)
DECON (Display and Enhancement Controller) is the Display Controller for the
Exynos7 series of SoCs which transfers the image data from a video memory
buffer to an external LCD interface.
Required properties:
- compatible: value should be "samsung,exynos7-decon";
- reg: physical base address and length of the DECON registers set.
- interrupts: should contain a list of all DECON IP block interrupts in the
order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
format depends on the interrupt controller used.
- interrupt-names: should contain the interrupt names: "fifo", "vsync",
"lcd_sys", in the same order as they were listed in the interrupts
property.
- pinctrl-0: pin control group to be used for this controller.
- pinctrl-names: must contain a "default" entry.
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
- clock-names: list of clock names sorted in the same order as the clocks
property. Must contain "pclk_decon0", "aclk_decon0",
"decon0_eclk", "decon0_vclk".
- i80-if-timings: timing configuration for lcd i80 interface support.
Optional Properties:
- power-domains: a phandle to DECON power domain node.
- display-timings: timing settings for DECON, as described in document [1].
Can be used in case timings cannot be provided otherwise
or to override timings provided by the panel.
[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
Example:
SoC specific DT entry:
decon@13930000 {
compatible = "samsung,exynos7-decon";
interrupt-parent = <&combiner>;
reg = <0x13930000 0x1000>;
interrupt-names = "lcd_sys", "vsync", "fifo";
interrupts = <0 188 0>, <0 189 0>, <0 190 0>;
clocks = <&clock_disp PCLK_DECON_INT>,
<&clock_disp ACLK_DECON_INT>,
<&clock_disp SCLK_DECON_INT_ECLK>,
<&clock_disp SCLK_DECON_INT_EXTCLKPLL>;
clock-names = "pclk_decon0", "aclk_decon0", "decon0_eclk",
"decon0_vclk";
status = "disabled";
};
Board specific DT entry:
decon@13930000 {
pinctrl-0 = <&lcd_clk &pwm1_out>;
pinctrl-names = "default";
status = "okay";
};
Documentation/devicetree/bindings/display/exynos/exynos_hdmi.txt deleted 100644 → 0
View file @ bddac7c1
Device-Tree bindings for drm hdmi driver
Required properties:
- compatible: value should be one among the following:
1) "samsung,exynos4210-hdmi"
2) "samsung,exynos4212-hdmi"
3) "samsung,exynos5420-hdmi"
4) "samsung,exynos5433-hdmi"
- reg: physical base address of the hdmi and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
- hpd-gpios: following information about the hotplug gpio pin.
a) phandle of the gpio controller node.
b) pin number within the gpio controller.
c) optional flags and pull up/down.
- ddc: phandle to the hdmi ddc node
- phy: phandle to the hdmi phy node
- samsung,syscon-phandle: phandle for system controller node for PMU.
- #sound-dai-cells: should be 0.
Required properties for Exynos 4210, 4212, 5420 and 5433:
- clocks: list of clock IDs from SoC clock driver.
a) hdmi: Gate of HDMI IP bus clock.
b) sclk_hdmi: Gate of HDMI special clock.
c) sclk_pixel: Pixel special clock, one of the two possible inputs of
HDMI clock mux.
d) sclk_hdmiphy: HDMI PHY clock output, one of two possible inputs of
HDMI clock mux.
e) mout_hdmi: It is required by the driver to switch between the 2
parents i.e. sclk_pixel and sclk_hdmiphy. If hdmiphy is stable
after configuration, parent is set to sclk_hdmiphy else
sclk_pixel.
- clock-names: aliases as per driver requirements for above clock IDs:
"hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy" and "mout_hdmi".
Required properties for Exynos 5433:
- clocks: list of clock specifiers according to common clock bindings.
a) hdmi_pclk: Gate of HDMI IP APB bus.
b) hdmi_i_pclk: Gate of HDMI-PHY IP APB bus.
d) i_tmds_clk: Gate of HDMI TMDS clock.
e) i_pixel_clk: Gate of HDMI pixel clock.
f) i_spdif_clk: Gate of HDMI SPDIF clock.
g) oscclk: Oscillator clock, used as parent of following *_user clocks
in case HDMI-PHY is not operational.
h) tmds_clko: TMDS clock generated by HDMI-PHY.
i) tmds_clko_user: MUX used to switch between oscclk and tmds_clko,
respectively if HDMI-PHY is off and operational.
j) pixel_clko: Pixel clock generated by HDMI-PHY.
k) pixel_clko_user: MUX used to switch between oscclk and pixel_clko,
respectively if HDMI-PHY is off and operational.
- clock-names: aliases for above clock specfiers.
- samsung,sysreg: handle to syscon used to control the system registers.
Example:
hdmi {
compatible = "samsung,exynos4212-hdmi";
reg = <0x14530000 0x100000>;
interrupts = <0 95 0>;
hpd-gpios = <&gpx3 7 1>;
ddc = <&hdmi_ddc_node>;
phy = <&hdmi_phy_node>;
samsung,syscon-phandle = <&pmu_system_controller>;
};
Documentation/devicetree/bindings/display/exynos/exynos_hdmiddc.txt deleted 100644 → 0
View file @ bddac7c1
Device-Tree bindings for hdmiddc driver
Required properties:
- compatible: value should be one of the following
1) "samsung,exynos5-hdmiddc" <DEPRECATED>
2) "samsung,exynos4210-hdmiddc"
- reg: I2C address of the hdmiddc device.
Example:
hdmiddc {
compatible = "samsung,exynos4210-hdmiddc";
reg = <0x50>;
};
Documentation/devicetree/bindings/display/exynos/exynos_hdmiphy.txt deleted 100644 → 0
View file @ bddac7c1
Device-Tree bindings for hdmiphy driver
Required properties:
- compatible: value should be one of the following:
1) "samsung,exynos5-hdmiphy" <DEPRECATED>
2) "samsung,exynos4210-hdmiphy".
3) "samsung,exynos4212-hdmiphy".
- reg: I2C address of the hdmiphy device.
Example:
hdmiphy {
compatible = "samsung,exynos4210-hdmiphy";
reg = <0x38>;
};
Documentation/devicetree/bindings/display/exynos/exynos_mixer.txt deleted 100644 → 0
View file @ bddac7c1
Device-Tree bindings for mixer driver
Required properties:
- compatible: value should be one of the following:
1) "samsung,exynos5-mixer" <DEPRECATED>
2) "samsung,exynos4210-mixer"
3) "samsung,exynos4212-mixer"
4) "samsung,exynos5250-mixer"
5) "samsung,exynos5420-mixer"
- reg: physical base address of the mixer and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
- clocks: list of clock IDs from SoC clock driver.
a) mixer: Gate of Mixer IP bus clock.
b) sclk_hdmi: HDMI Special clock, one of the two possible inputs of
mixer mux.
c) hdmi: Gate of HDMI IP bus clock, needed together with sclk_hdmi.
Example:
mixer {
compatible = "samsung,exynos5250-mixer";
reg = <0x14450000 0x10000>;
interrupts = <0 94 0>;
};
Documentation/devicetree/bindings/display/exynos/samsung-fimd.txt deleted 100644 → 0
View file @ bddac7c1
Device-Tree bindings for Samsung SoC display controller (FIMD)
FIMD (Fully Interactive Mobile Display) is the Display Controller for the
Samsung series of SoCs which transfers the image data from a video memory
buffer to an external LCD interface.
Required properties:
- compatible: value should be one of the following
"samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
"samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
"samsung,s5pv210-fimd"; /* for S5PV210 SoC */
"samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
"samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
"samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */
"samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */
- reg: physical base address and length of the FIMD registers set.
- interrupts: should contain a list of all FIMD IP block interrupts in the
order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
format depends on the interrupt controller used.
- interrupt-names: should contain the interrupt names: "fifo", "vsync",
"lcd_sys", in the same order as they were listed in the interrupts
property.
- pinctrl-0: pin control group to be used for this controller.
- pinctrl-names: must contain a "default" entry.
- clocks: must include clock specifiers corresponding to entries in the
clock-names property.
- clock-names: list of clock names sorted in the same order as the clocks
property. Must contain "sclk_fimd" and "fimd".
Optional Properties:
- power-domains: a phandle to FIMD power domain node.
- samsung,invert-vden: video enable signal is inverted
- samsung,invert-vclk: video clock signal is inverted
- display-timings: timing settings for FIMD, as described in document [1].
Can be used in case timings cannot be provided otherwise
or to override timings provided by the panel.
- samsung,sysreg: handle to syscon used to control the system registers
- i80-if-timings: timing configuration for lcd i80 interface support.
- cs-setup: clock cycles for the active period of address signal is enabled
until chip select is enabled.
If not specified, the default value(0) will be used.
- wr-setup: clock cycles for the active period of CS signal is enabled until
write signal is enabled.
If not specified, the default value(0) will be used.
- wr-active: clock cycles for the active period of CS is enabled.
If not specified, the default value(1) will be used.
- wr-hold: clock cycles for the active period of CS is disabled until write
signal is disabled.
If not specified, the default value(0) will be used.
The parameters are defined as:
VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??
: : : : :
Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
| cs-setup+1 | : : :
|<---------->| : : :
Chip Select ???????????????|____________:____________:____________|??
| wr-setup+1 | | wr-hold+1 |
|<---------->| |<---------->|
Write Enable ????????????????????????????|____________|???????????????
| wr-active+1|
|<---------->|
Video Data ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--
The device node can contain 'port' child nodes according to the bindings defined
in [2]. The following are properties specific to those nodes:
- reg: (required) port index, can be:
0 - for CAMIF0 input,
1 - for CAMIF1 input,
2 - for CAMIF2 input,
3 - for parallel output,
4 - for write-back interface
[1]: Documentation/devicetree/bindings/display/panel/display-timing.txt
[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
Example:
SoC specific DT entry:
fimd@11c00000 {
compatible = "samsung,exynos4210-fimd";
interrupt-parent = <&combiner>;
reg = <0x11c00000 0x20000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <11 0>, <11 1>, <11 2>;
clocks = <&clock 140>, <&clock 283>;
clock-names = "sclk_fimd", "fimd";
power-domains = <&pd_lcd0>;
status = "disabled";
};
Board specific DT entry:
fimd@11c00000 {
pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
pinctrl-names = "default";
status = "okay";
};
Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml
View file @ 9bf3fc50
......@@ -51,7 +51,10 @@ properties:
mediatek,syscon-hdmi:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
maxItems: 1
items:
- items:
- description: phandle to system configuration registers
- description: register offset in the system configuration registers
description: |
phandle link and register offset to the system configuration registers.
......
Documentation/devicetree/bindings/display/msm/gpu.yaml
View file @ 9bf3fc50
......@@ -64,6 +64,8 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 4
items:
maxItems: 1
description: |
phandles to one or more reserved on-chip SRAM regions.
phandle to the On Chip Memory (OCMEM) that's present on some a3xx and
......
Documentation/devicetree/bindings/display/msm/mdp4.txt deleted 100644 → 0
View file @ bddac7c1
Qualcomm adreno/snapdragon MDP4 display controller
Description:
This is the bindings documentation for the MDP4 display controller found in
SoCs like MSM8960, APQ8064 and MSM8660.
Required properties:
- compatible:
* "qcom,mdp4" - mdp4
- reg: Physical base address and length of the controller's registers.
- interrupts: The interrupt signal from the display controller.
- clocks: device clocks
See ../clocks/clock-bindings.txt for details.
- clock-names: the following clocks are required.
* "core_clk"
* "iface_clk"
* "bus_clk"
* "lut_clk"
* "hdmi_clk"
* "tv_clk"
- ports: contains the list of output ports from MDP. These connect to interfaces
that are external to the MDP hardware, such as HDMI, DSI, EDP etc (LVDS is a
special case since it is a part of the MDP block itself).
Each output port contains an endpoint that describes how it is connected to an
external interface. These are described by the standard properties documented
here:
Documentation/devicetree/bindings/graph.txt
Documentation/devicetree/bindings/media/video-interfaces.txt
The output port mappings are:
Port 0 -> LCDC/LVDS
Port 1 -> DSI1 Cmd/Video
Port 2 -> DSI2 Cmd/Video
Port 3 -> DTV
Optional properties:
- clock-names: the following clocks are optional:
* "lut_clk"
- qcom,lcdc-align-lsb: Boolean value indicating that LSB alignment should be
used for LCDC. This is only valid for 18bpp panels.
Example:
/ {
...
hdmi: hdmi@4a00000 {
...
ports {
...
port@0 {
reg = <0>;
hdmi_in: endpoint {
remote-endpoint = <&mdp_dtv_out>;
};
};
...
};
...
};
...
mdp: mdp@5100000 {
compatible = "qcom,mdp4";
reg = <0x05100000 0xf0000>;
interrupts = <GIC_SPI 75 0>;
clock-names =
"core_clk",
"iface_clk",
"lut_clk",
"hdmi_clk",
"tv_clk";
clocks =
<&mmcc MDP_CLK>,
<&mmcc MDP_AHB_CLK>,
<&mmcc MDP_AXI_CLK>,
<&mmcc MDP_LUT_CLK>,
<&mmcc HDMI_TV_CLK>,
<&mmcc MDP_TV_CLK>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdp_lvds_out: endpoint {
};
};
port@1 {
reg = <1>;
mdp_dsi1_out: endpoint {
};
};
port@2 {
reg = <2>;
mdp_dsi2_out: endpoint {
};
};
port@3 {
reg = <3>;
mdp_dtv_out: endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};
};
};
Documentation/devicetree/bindings/display/msm/mdp4.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/display/msm/mdp4.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Qualcomm Adreno/Snapdragon MDP4 display controller
description: >
MDP4 display controller found in SoCs like MSM8960, APQ8064 and MSM8660.
maintainers:
- Rob Clark <robdclark@gmail.com>
properties:
compatible:
const: qcom,mdp4
clocks:
minItems: 6
maxItems: 6
clock-names:
items:
- const: core_clk
- const: iface_clk
- const: bus_clk
- const: lut_clk
- const: hdmi_clk
- const: tv_clk
reg:
maxItems: 1
interrupts:
maxItems: 1
iommus:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: LCDC/LVDS
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: DSI1 Cmd / Video
port@2:
$ref: /schemas/graph.yaml#/properties/port
description: DSI2 Cmd / Video
port@3:
$ref: /schemas/graph.yaml#/properties/port
description: Digital TV
qcom,lcdc-align-lsb:
type: boolean
description: >
Indication that LSB alignment should be used for LCDC.
This is only valid for 18bpp panels.
required:
- compatible
- reg
- clocks
- ports
additionalProperties: false
examples:
- |
mdp: mdp@5100000 {
compatible = "qcom,mdp4";
reg = <0x05100000 0xf0000>;
interrupts = <0 75 0>;
clock-names =
"core_clk",
"iface_clk",
"bus_clk",
"lut_clk",
"hdmi_clk",
"tv_clk";
clocks =
<&mmcc 77>,
<&mmcc 86>,
<&mmcc 102>,
<&mmcc 75>,
<&mmcc 97>,
<&mmcc 12>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdp_lvds_out: endpoint {
};
};
port@1 {
reg = <1>;
mdp_dsi1_out: endpoint {
};
};
port@2 {
reg = <2>;
mdp_dsi2_out: endpoint {
};
};
port@3 {
reg = <3>;
mdp_dtv_out: endpoint {
remote-endpoint = <&hdmi_in>;
};
};
};
};
Documentation/devicetree/bindings/display/panel/display-timings.yaml
View file @ 9bf3fc50
......@@ -31,8 +31,7 @@ properties:
patternProperties:
"^timing":
type: object
allOf:
- $ref: panel-timing.yaml#
$ref: panel-timing.yaml#
additionalProperties: false
......
Documentation/devicetree/bindings/display/panel/leadtek,ltk050h3146w.yaml
View file @ 9bf3fc50
......@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Leadtek LTK050H3146W 5.0in 720x1280 DSI panel
maintainers:
- Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
- Quentin Schulz <quentin.schulz@theobroma-systems.com>
allOf:
- $ref: panel-common.yaml#
......
Documentation/devicetree/bindings/display/renesas,du.yaml
View file @ 9bf3fc50
......@@ -76,17 +76,21 @@ properties:
renesas,cmms:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
items:
maxItems: 1
description:
A list of phandles to the CMM instances present in the SoC, one for each
available DU channel.
renesas,vsps:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
items:
items:
- description: phandle to VSP instance that serves the DU channel
- description: Channel index identifying the LIF instance in that VSP
description:
A list of phandle and channel index tuples to the VSPs that handle the
memory interfaces for the DU channels. The phandle identifies the VSP
instance that serves the DU channel, and the channel index identifies
the LIF instance in that VSP.
memory interfaces for the DU channels.
required:
- compatible
......
Documentation/devicetree/bindings/display/rockchip/rockchip-drm.yaml
View file @ 9bf3fc50
......@@ -21,6 +21,8 @@ properties:
ports:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description: |
Should contain a list of phandles pointing to display interface port
of vop devices. vop definitions as defined in
......
Documentation/devicetree/bindings/display/samsung/samsung,exynos-hdmi-ddc.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi-ddc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC HDMI DDC
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
properties:
compatible:
oneOf:
- const: samsung,exynos4210-hdmiddc
- const: samsung,exynos5-hdmiddc
deprecated: true
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
ddc@50 {
compatible = "samsung,exynos4210-hdmiddc";
reg = <0x50>;
};
};
Documentation/devicetree/bindings/display/samsung/samsung,exynos-hdmi.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC HDMI
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
properties:
compatible:
enum:
- samsung,exynos4210-hdmi
- samsung,exynos4212-hdmi
- samsung,exynos5420-hdmi
- samsung,exynos5433-hdmi
clocks:
minItems: 5
maxItems: 10
clock-names:
minItems: 5
maxItems: 10
ddc:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the HDMI DDC node.
hdmi-en-supply:
description:
Provides voltage source for DCC lines available on HDMI connector. When
there is no power provided for DDC epprom, some TV-sets do not pulls up
HPD (hot plug detect) line, what causes HDMI block to stay turned off.
When provided, the regulator allows TV-set correctly signal HPD event.
hpd-gpios:
maxItems: 1
description:
A GPIO line connected to HPD
interrupts:
maxItems: 1
phy:
$ref: /schemas/types.yaml#/definitions/phandle
description: Phandle to the HDMI PHY node.
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Contains a port which is connected to mic node.
power-domains:
maxItems: 1
reg:
maxItems: 1
samsung,syscon-phandle:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the PMU system controller node.
samsung,sysreg-phandle:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to DISP system controller interface.
'#sound-dai-cells':
const: 0
vdd-supply:
description:
VDD 1.0V HDMI TX.
vdd_osc-supply:
description:
VDD 1.8V HDMI OSC.
vdd_pll-supply:
description:
VDD 1.0V HDMI PLL.
required:
- compatible
- clocks
- clock-names
- ddc
- hpd-gpios
- interrupts
- phy
- reg
- samsung,syscon-phandle
- '#sound-dai-cells'
- vdd-supply
- vdd_osc-supply
- vdd_pll-supply
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos5433-hdmi
then:
properties:
clocks:
items:
- description: Gate of HDMI IP APB bus.
- description: Gate of HDMI-PHY IP APB bus.
- description: Gate of HDMI TMDS clock.
- description: Gate of HDMI pixel clock.
- description: TMDS clock generated by HDMI-PHY.
- description: MUX used to switch between oscclk and tmds_clko,
respectively if HDMI-PHY is off and operational.
- description: Pixel clock generated by HDMI-PHY.
- description: MUX used to switch between oscclk and pixel_clko,
respectively if HDMI-PHY is off and operational.
- description: Oscillator clock, used as parent of following *_user
clocks in case HDMI-PHY is not operational.
- description: Gate of HDMI SPDIF clock.
clock-names:
items:
- const: hdmi_pclk
- const: hdmi_i_pclk
- const: i_tmds_clk
- const: i_pixel_clk
- const: tmds_clko
- const: tmds_clko_user
- const: pixel_clko
- const: pixel_clko_user
- const: oscclk
- const: i_spdif_clk
required:
- samsung,sysreg-phandle
else:
properties:
clocks:
items:
- description: Gate of HDMI IP bus clock.
- description: Gate of HDMI special clock.
- description: Pixel special clock, one of the two possible inputs
of HDMI clock mux.
- description: HDMI PHY clock output, one of two possible inputs of
HDMI clock mux.
- description: It is required by the driver to switch between the 2
parents i.e. sclk_pixel and sclk_hdmiphy. If hdmiphy is stable
after configuration, parent is set to sclk_hdmiphy else
sclk_pixel.
clock-names:
items:
- const: hdmi
- const: sclk_hdmi
- const: sclk_pixel
- const: sclk_hdmiphy
- const: mout_hdmi
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5433.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
hdmi@13970000 {
compatible = "samsung,exynos5433-hdmi";
reg = <0x13970000 0x70000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu_disp CLK_PCLK_HDMI>,
<&cmu_disp CLK_PCLK_HDMIPHY>,
<&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
<&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
<&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
<&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
<&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
<&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
<&xxti>,
<&cmu_disp CLK_SCLK_HDMI_SPDIF>;
clock-names = "hdmi_pclk",
"hdmi_i_pclk",
"i_tmds_clk",
"i_pixel_clk",
"tmds_clko",
"tmds_clko_user",
"pixel_clko",
"pixel_clko_user",
"oscclk",
"i_spdif_clk";
phy = <&hdmiphy>;
ddc = <&hsi2c_11>;
samsung,syscon-phandle = <&pmu_system_controller>;
samsung,sysreg-phandle = <&syscon_disp>;
#sound-dai-cells = <0>;
hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>;
vdd-supply = <&ldo6_reg>;
vdd_osc-supply = <&ldo7_reg>;
vdd_pll-supply = <&ldo6_reg>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_to_tv: endpoint {
remote-endpoint = <&tv_to_hdmi>;
};
};
port@1 {
reg = <1>;
hdmi_to_mhl: endpoint {
remote-endpoint = <&mhl_to_hdmi>;
};
};
};
};
Documentation/devicetree/bindings/display/samsung/samsung,exynos-mixer.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,exynos-mixer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos SoC Mixer
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
description:
Samsung Exynos SoC Mixer is responsible for mixing and blending multiple data
inputs before passing it to an output device. The output is passed to HDMI.
properties:
compatible:
oneOf:
- enum:
- samsung,exynos4210-mixer
- samsung,exynos4212-mixer
- samsung,exynos5250-mixer
- samsung,exynos5420-mixer
- const: samsung,exynos5-mixer
deprecated: true
clocks:
minItems: 3
items:
- description: Gate of Mixer IP bus clock.
- description: Gate of HDMI IP bus clock, needed together with sclk_hdmi.
- description: HDMI Special clock, one of the two possible inputs of
mixer mux.
- description: Video Processor clock.
- description: Mixer mux clock.
- description: Mixer Special clock.
clock-names:
minItems: 3
items:
- const: mixer
- const: hdmi
- const: sclk_hdmi
- const: vp
- const: mout_mixer
- const: sclk_mixer
interconnects:
maxItems: 1
interrupts:
maxItems: 1
iommus:
maxItems: 1
power-domains:
maxItems: 1
reg:
minItems: 1
items:
- description: Mixer memory region.
- description: Video Processor memory region.
required:
- compatible
- clocks
- clock-names
- interrupts
- reg
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos4210-mixer
- samsung,exynos4212-mixer
then:
properties:
clocks:
minItems: 6
maxItems: 6
regs:
minItems: 2
maxItems: 2
- if:
properties:
compatible:
contains:
const: samsung,exynos4212-mixer
then:
properties:
clocks:
minItems: 4
maxItems: 4
regs:
minItems: 2
maxItems: 2
- if:
properties:
compatible:
contains:
enum:
- samsung,exynos5-mixer
- samsung,exynos5250-mixer
- samsung,exynos5420-mixer
then:
properties:
clocks:
minItems: 3
maxItems: 3
regs:
minItems: 1
maxItems: 1
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5250.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
mixer@14450000 {
compatible = "samsung,exynos5250-mixer";
reg = <0x14450000 0x10000>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MIXER>,
<&clock CLK_HDMI>,
<&clock CLK_SCLK_HDMI>;
clock-names = "mixer",
"hdmi",
"sclk_hdmi";
iommus = <&sysmmu_tv>;
power-domains = <&pd_disp1>;
};
Documentation/devicetree/bindings/display/samsung/samsung,exynos5433-decon.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,exynos5433-decon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos5433 SoC Display and Enhancement Controller (DECON)
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
description: |
DECON (Display and Enhancement Controller) is the Display Controller for the
Exynos5433 series of SoCs which transfers the image data from a video memory
buffer to an external LCD interface.
properties:
compatible:
enum:
- samsung,exynos5433-decon
- samsung,exynos5433-decon-tv
clocks:
minItems: 11
maxItems: 11
clock-names:
items:
- const: pclk
- const: aclk_decon
- const: aclk_smmu_decon0x
- const: aclk_xiu_decon0x
- const: pclk_smmu_decon0x
- const: aclk_smmu_decon1x
- const: aclk_xiu_decon1x
- const: pclk_smmu_decon1x
- const: sclk_decon_vclk
- const: sclk_decon_eclk
- const: dsd
interrupts:
minItems: 3
maxItems: 4
description: |
Interrupts depend on mode of work:
- video mode: vsync
- command mode: lcd_sys
- command mode with software trigger: lcd_sys, te
interrupt-names:
minItems: 3
items:
- const: fifo
- const: vsync
- const: lcd_sys
- const: te
iommus:
minItems: 2
maxItems: 2
iommu-names:
items:
- const: m0
- const: m1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Contains a port which is connected to mic node.
power-domains:
maxItems: 1
reg:
maxItems: 1
samsung,disp-sysreg:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to DISP system controller interface.
required:
- compatible
- clocks
- clock-names
- interrupts
- interrupt-names
- ports
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5433.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
display-controller@13800000 {
compatible = "samsung,exynos5433-decon";
reg = <0x13800000 0x2104>;
clocks = <&cmu_disp CLK_PCLK_DECON>,
<&cmu_disp CLK_ACLK_DECON>,
<&cmu_disp CLK_ACLK_SMMU_DECON0X>,
<&cmu_disp CLK_ACLK_XIU_DECON0X>,
<&cmu_disp CLK_PCLK_SMMU_DECON0X>,
<&cmu_disp CLK_ACLK_SMMU_DECON1X>,
<&cmu_disp CLK_ACLK_XIU_DECON1X>,
<&cmu_disp CLK_PCLK_SMMU_DECON1X>,
<&cmu_disp CLK_SCLK_DECON_VCLK>,
<&cmu_disp CLK_SCLK_DECON_ECLK>,
<&cmu_disp CLK_SCLK_DSD>;
clock-names = "pclk",
"aclk_decon",
"aclk_smmu_decon0x",
"aclk_xiu_decon0x",
"pclk_smmu_decon0x",
"aclk_smmu_decon1x",
"aclk_xiu_decon1x",
"pclk_smmu_decon1x",
"sclk_decon_vclk",
"sclk_decon_eclk",
"dsd";
power-domains = <&pd_disp>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
samsung,disp-sysreg = <&syscon_disp>;
iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
iommu-names = "m0", "m1";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
decon_to_mic: endpoint {
remote-endpoint = <&mic_to_decon>;
};
};
};
};
Documentation/devicetree/bindings/display/samsung/samsung,exynos5433-mic.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,exynos5433-mic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos5433 SoC Mobile Image Compressor (MIC)
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
description: |
MIC (Mobile Image Compressor) resides between DECON and MIPI DSI. MIPI DSI is
not capable of transferring high resoltuion frame data as DECON can send. MIC
solves this problem by compressing the frame data by 1/2 before it is
transferred through MIPI DSI. The compressed frame data must be uncompressed
in the panel PCB.
properties:
compatible:
const: samsung,exynos5433-mic
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: pclk_mic0
- const: sclk_rgb_vclk_to_mic0
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
Contains a port which is connected to mic node.
power-domains:
maxItems: 1
reg:
maxItems: 1
samsung,disp-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to DISP system controller interface.
required:
- compatible
- clocks
- clock-names
- ports
- reg
- samsung,disp-syscon
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5433.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
image-processor@13930000 {
compatible = "samsung,exynos5433-mic";
reg = <0x13930000 0x48>;
clocks = <&cmu_disp CLK_PCLK_MIC0>,
<&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
clock-names = "pclk_mic0",
"sclk_rgb_vclk_to_mic0";
power-domains = <&pd_disp>;
samsung,disp-syscon = <&syscon_disp>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mic_to_decon: endpoint {
remote-endpoint = <&decon_to_mic>;
};
};
port@1 {
reg = <1>;
mic_to_dsi: endpoint {
remote-endpoint = <&dsi_to_mic>;
};
};
};
};
Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,exynos7-decon.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung Exynos7 SoC Display and Enhancement Controller (DECON)
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
description: |
DECON (Display and Enhancement Controller) is the Display Controller for the
Exynos7 series of SoCs which transfers the image data from a video memory
buffer to an external LCD interface.
properties:
compatible:
const: samsung,exynos7-decon
clocks:
minItems: 4
maxItems: 4
clock-names:
items:
- const: pclk_decon0
- const: aclk_decon0
- const: decon0_eclk
- const: decon0_vclk
display-timings:
$ref: ../panel/display-timings.yaml#
i80-if-timings:
type: object
description: timing configuration for lcd i80 interface support
properties:
cs-setup:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of address signal is enabled until
chip select is enabled.
default: 0
wr-active:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of CS is enabled.
default: 1
wr-hold:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of CS is disabled until write
signal is disabled.
default: 0
wr-setup:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of CS signal is enabled until
write signal is enabled.
default: 0
interrupts:
items:
- description: FIFO level
- description: VSYNC
- description: LCD system
interrupt-names:
items:
- const: fifo
- const: vsync
- const: lcd_sys
power-domains:
maxItems: 1
reg:
maxItems: 1
required:
- compatible
- clocks
- clock-names
- interrupts
- interrupt-names
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos7-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
display-controller@13930000 {
compatible = "samsung,exynos7-decon";
reg = <0x13930000 0x1000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_disp 100>, /* PCLK_DECON_INT */
<&clock_disp 101>, /* ACLK_DECON_INT */
<&clock_disp 102>, /* SCLK_DECON_INT_ECLK */
<&clock_disp 103>; /* SCLK_DECON_INT_EXTCLKPLL */
clock-names = "pclk_decon0",
"aclk_decon0",
"decon0_eclk",
"decon0_vclk";
pinctrl-0 = <&lcd_clk &pwm1_out>;
pinctrl-names = "default";
};
Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/samsung/samsung,fimd.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S3C/S5P/Exynos SoC Fully Interactive Mobile Display (FIMD)
maintainers:
- Inki Dae <inki.dae@samsung.com>
- Joonyoung Shim <jy0922.shim@samsung.com>
- Seung-Woo Kim <sw0312.kim@samsung.com>
- Kyungmin Park <kyungmin.park@samsung.com>
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
properties:
compatible:
enum:
- samsung,s3c2443-fimd
- samsung,s3c6400-fimd
- samsung,s5pv210-fimd
- samsung,exynos3250-fimd
- samsung,exynos4210-fimd
- samsung,exynos5250-fimd
- samsung,exynos5420-fimd
'#address-cells':
const: 1
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: sclk_fimd
- const: fimd
display-timings:
$ref: ../panel/display-timings.yaml#
i80-if-timings:
type: object
description: |
Timing configuration for lcd i80 interface support.
The parameters are defined as::
VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??
: : : : :
Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
| cs-setup+1 | : : :
|<---------->| : : :
Chip Select ???????????????|____________:____________:____________|??
| wr-setup+1 | | wr-hold+1 |
|<---------->| |<---------->|
Write Enable ????????????????????????????|____________|???????????????
| wr-active+1|
|<---------->|
Video Data ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--
properties:
cs-setup:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of address signal is enabled until
chip select is enabled.
default: 0
wr-active:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of CS is enabled.
default: 1
wr-hold:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of CS is disabled until write
signal is disabled.
default: 0
wr-setup:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Clock cycles for the active period of CS signal is enabled until
write signal is enabled.
default: 0
iommus:
minItems: 1
maxItems: 2
iommu-names:
items:
- const: m0
- const: m1
interrupts:
items:
- description: FIFO level
- description: VSYNC
- description: LCD system
interrupt-names:
items:
- const: fifo
- const: vsync
- const: lcd_sys
power-domains:
maxItems: 1
reg:
maxItems: 1
samsung,invert-vden:
type: boolean
description:
Video enable signal is inverted.
samsung,invert-vclk:
type: boolean
description:
Video clock signal is inverted.
samsung,sysreg:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to System Register syscon.
'#size-cells':
const: 0
patternProperties:
"^port@[0-4]+$":
$ref: /schemas/graph.yaml#/properties/port
description: |
Contains ports with port with index::
0 - for CAMIF0 input,
1 - for CAMIF1 input,
2 - for CAMIF2 input,
3 - for parallel output,
4 - for write-back interface
required:
- compatible
- clocks
- clock-names
- interrupts
- interrupt-names
- reg
allOf:
- if:
properties:
compatible:
contains:
const: samsung,exynos5420-fimd
then:
properties:
iommus:
minItems: 2
maxItems: 2
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/exynos4.h>
fimd@11c00000 {
compatible = "samsung,exynos4210-fimd";
interrupt-parent = <&combiner>;
reg = <0x11c00000 0x20000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <11 0>, <11 1>, <11 2>;
clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
clock-names = "sclk_fimd", "fimd";
power-domains = <&pd_lcd0>;
iommus = <&sysmmu_fimd0>;
samsung,sysreg = <&sys_reg>;
#address-cells = <1>;
#size-cells = <0>;
samsung,invert-vden;
samsung,invert-vclk;
pinctrl-0 = <&lcd_clk>, <&lcd_data24>;
pinctrl-names = "default";
port@3 {
reg = <3>;
fimd_dpi_ep: endpoint {
remote-endpoint = <&lcd_ep>;
};
};
};
Documentation/devicetree/bindings/display/sprd/sprd,display-subsystem.yaml
View file @ 9bf3fc50
......@@ -45,6 +45,8 @@ properties:
ports:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description:
Should contain a list of phandles pointing to display interface port
of DPU devices.
......
Documentation/devicetree/bindings/display/ste,mcde.yaml
View file @ 9bf3fc50
......@@ -58,8 +58,8 @@ patternProperties:
"^dsi@[0-9a-f]+$":
description: subnodes for the three DSI host adapters
type: object
allOf:
- $ref: dsi-controller.yaml#
$ref: dsi-controller.yaml#
properties:
compatible:
const: ste,mcde-dsi
......
Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
View file @ 9bf3fc50
......@@ -88,8 +88,7 @@ properties:
The DSS DPI output port node from video port 2
ti,am65x-oldi-io-ctrl:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
maxItems: 1
$ref: "/schemas/types.yaml#/definitions/phandle"
description:
phandle to syscon device node mapping OLDI IO_CTRL registers.
The mapped range should point to OLDI_DAT0_IO_CTRL, map it and
......
Documentation/devicetree/bindings/dma/dma-router.yaml
View file @ 9bf3fc50
......@@ -24,6 +24,8 @@ properties:
dma-masters:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description:
Array of phandles to the DMA controllers the router can direct
the signal to.
......
Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
View file @ 9bf3fc50
......@@ -22,6 +22,9 @@ description: |
https://static.dev.sifive.com/FU540-C000-v1.0.pdf
allOf:
- $ref: "dma-controller.yaml#"
properties:
compatible:
items:
......@@ -41,13 +44,12 @@ required:
- compatible
- reg
- interrupts
- '#dma-cells'
additionalProperties: false
unevaluatedProperties: false
examples:
- |
dma@3000000 {
dma-controller@3000000 {
compatible = "sifive,fu540-c000-pdma";
reg = <0x3000000 0x8000>;
interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, <30>;
......
Documentation/devicetree/bindings/dma/st,stm32-dmamux.yaml
View file @ 9bf3fc50
......@@ -46,7 +46,7 @@ examples:
#dma-cells = <3>;
dma-requests = <128>;
dma-channels = <16>;
dma-masters = <&dma1 &dma2>;
dma-masters = <&dma1>, <&dma2>;
clocks = <&timer_clk>;
};
......
Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx ZynqMP DMA Engine
description: |
The Xilinx ZynqMP DMA engine supports memory to memory transfers,
memory to device and device to memory transfers. It also has flow
control and rate control support for slave/peripheral dma access.
maintainers:
- Michael Tretter <m.tretter@pengutronix.de>
allOf:
- $ref: "../dma-controller.yaml#"
properties:
"#dma-cells":
const: 1
compatible:
const: xlnx,zynqmp-dma-1.0
reg:
description: memory map for gdma/adma module access
maxItems: 1
interrupts:
description: DMA channel interrupt
maxItems: 1
clocks:
description: input clocks
minItems: 2
maxItems: 2
clock-names:
items:
- const: clk_main
- const: clk_apb
xlnx,bus-width:
$ref: /schemas/types.yaml#/definitions/uint32
enum:
- 64
- 128
description: AXI bus width in bits
iommus:
maxItems: 1
power-domains:
maxItems: 1
dma-coherent:
description: present if dma operations are coherent
required:
- "#dma-cells"
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
fpd_dma_chan1: dma-controller@fd500000 {
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0xfd500000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 117 0x4>;
#dma-cells = <1>;
clock-names = "clk_main", "clk_apb";
clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
xlnx,bus-width = <128>;
dma-coherent;
};
Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt deleted 100644 → 0
View file @ bddac7c1
Xilinx ZynqMP DMA engine, it does support memory to memory transfers,
memory to device and device to memory transfers. It also has flow
control and rate control support for slave/peripheral dma access.
Required properties:
- compatible : Should be "xlnx,zynqmp-dma-1.0"
- reg : Memory map for gdma/adma module access.
- interrupts : Should contain DMA channel interrupt.
- xlnx,bus-width : Axi buswidth in bits. Should contain 128 or 64
- clock-names : List of input clocks "clk_main", "clk_apb"
(see clock bindings for details)
Optional properties:
- dma-coherent : Present if dma operations are coherent.
Example:
++++++++
fpd_dma_chan1: dma@fd500000 {
compatible = "xlnx,zynqmp-dma-1.0";
reg = <0x0 0xFD500000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 117 4>;
clock-names = "clk_main", "clk_apb";
xlnx,bus-width = <128>;
dma-coherent;
};
Documentation/devicetree/bindings/dvfs/performance-domain.yaml
View file @ 9bf3fc50
......@@ -43,7 +43,6 @@ properties:
performance-domains:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
maxItems: 1
description:
A phandle and performance domain specifier as defined by bindings of the
performance controller/provider specified by phandle.
......
Documentation/devicetree/bindings/example-schema.yaml
View file @ 9bf3fc50
......@@ -162,6 +162,16 @@ properties:
don't need a type.
enum: [ 100, 200, 300 ]
vendor,int-array-variable-length-and-constrained-values:
description: Array might define what type of elements might be used (e.g.
their range).
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 2
maxItems: 3
items:
minimum: 0
maximum: 8
child-node:
description: Child nodes are just another property from a json-schema
perspective.
......@@ -207,6 +217,10 @@ allOf:
then:
required:
- foo-supply
else:
# If otherwise the property is not allowed:
properties:
foo-supply: false
# Altering schema depending on presence of properties is usually done by
# dependencies (see above), however some adjustments might require if:
- if:
......
Documentation/devicetree/bindings/firmware/arm,scmi.yaml
View file @ 9bf3fc50
......@@ -364,7 +364,7 @@ examples:
firmware {
scmi {
compatible = "arm,scmi-smc";
shmem = <&cpu_scp_lpri0 &cpu_scp_lpri1>;
shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>;
arm,smc-id = <0xc3000001>;
#address-cells = <1>;
......
Documentation/devicetree/bindings/firmware/arm,scpi.yaml
View file @ 9bf3fc50
......@@ -43,6 +43,7 @@ properties:
by remote SCP firmware for use by SCPI message protocol should be
specified in any order.
minItems: 1
maxItems: 4
shmem:
description:
......@@ -51,6 +52,7 @@ properties:
be any memory reserved for the purpose of this communication between the
processors.
minItems: 1
maxItems: 4
power-controller:
type: object
......@@ -235,8 +237,8 @@ examples:
firmware {
scpi {
compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
mboxes = <&mailbox 1 &mailbox 2>;
shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
mboxes = <&mailbox 1>, <&mailbox 2>;
shmem = <&cpu_scp_lpri>, <&cpu_scp_hpri>;
scpi_sensors1: sensors {
compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
......
Documentation/devicetree/bindings/firmware/qemu,fw-cfg-mmio.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/firmware/qemu,fw-cfg-mmio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: QEMU Firmware Configuration bindings
maintainers:
- Rob Herring <robh@kernel.org>
description: |
Various QEMU emulation / virtualization targets provide the following
Firmware Configuration interface on the "virt" machine type:
- A write-only, 16-bit wide selector (or control) register,
- a read-write, 64-bit wide data register.
QEMU exposes the control and data register to guests as memory mapped
registers; their location is communicated to the guest's UEFI firmware in the
DTB that QEMU places at the bottom of the guest's DRAM.
The authoritative guest-side hardware interface documentation to the fw_cfg
device can be found in "docs/specs/fw_cfg.txt" in the QEMU source tree.
properties:
compatible:
const: qemu,fw-cfg-mmio
reg:
maxItems: 1
description: |
* Bytes 0x0 to 0x7 cover the data register.
* Bytes 0x8 to 0x9 cover the selector register.
* Further registers may be appended to the region in case of future interface
revisions / feature bits.
dma-coherent: true
required:
- compatible
- reg
additionalProperties: false
examples:
- |
fw-cfg@9020000 {
compatible = "qemu,fw-cfg-mmio";
reg = <0x9020000 0xa>;
};
...
Documentation/devicetree/bindings/gnss/gnss-common.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gnss/gnss-common.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common Properties for Global Navigation Satellite Systems (GNSS)
receiver devices
maintainers:
- Johan Hovold <johan@kernel.org>
description: |
This document defines device tree properties common to Global Navigation
Satellite System receivers.
properties:
$nodename:
pattern: "^gnss(@.*)?$"
lna-supply:
description: A separate regulator supplying power for the Low Noise
Amplifier (LNA). This is an amplifier connected between the GNSS
device and the receiver antenna.
enable-gpios:
description: A GPIO line that will enable the GNSS receiver when
asserted. If this line is active low, the GPIO phandle should
consequently be tagged with the GPIO_ACTIVE_LOW flag so the operating
system can rely on asserting the line to enable the GNSS device.
maxItems: 1
timepulse-gpios:
description: When a timepulse is provided to the GNSS device using a
GPIO line, this is used.
maxItems: 1
current-speed:
description: The baudrate in bits per second of the device as it comes
online, current active speed.
$ref: /schemas/types.yaml#/definitions/uint32
additionalProperties: true
examples:
- |
#include <dt-bindings/gpio/gpio.h>
serial {
gnss {
compatible = "u-blox,neo-8";
vcc-supply = <&gnss_reg>;
timepulse-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
current-speed = <4800>;
};
};
Documentation/devicetree/bindings/gnss/gnss.txt deleted 100644 → 0
View file @ bddac7c1
GNSS Receiver DT binding
This documents the binding structure and common properties for GNSS receiver
devices.
A GNSS receiver node is a node named "gnss" and typically resides on a serial
bus (e.g. UART, I2C or SPI).
Please refer to the following documents for generic properties:
Documentation/devicetree/bindings/serial/serial.yaml
Documentation/devicetree/bindings/spi/spi-bus.txt
Required properties:
- compatible : A string reflecting the vendor and specific device the node
represents
Optional properties:
- lna-supply : Separate supply for an LNA
- enable-gpios : GPIO used to enable the device
- timepulse-gpios : Time pulse GPIO
Example:
serial@1234 {
compatible = "ns16550a";
gnss {
compatible = "u-blox,neo-8";
vcc-supply = <&gnss_reg>;
timepulse-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
current-speed = <4800>;
};
};
Documentation/devicetree/bindings/gnss/sirfstar.txt deleted 100644 → 0
View file @ bddac7c1
SiRFstar-based GNSS Receiver DT binding
SiRFstar chipsets are used in GNSS-receiver modules produced by several
vendors and can use UART, SPI or I2C interfaces.
Please see Documentation/devicetree/bindings/gnss/gnss.txt for generic
properties.
Required properties:
- compatible : Must be one of
"fastrax,uc430"
"linx,r4"
"wi2wi,w2sg0004"
"wi2wi,w2sg0008i"
"wi2wi,w2sg0084i"
- vcc-supply : Main voltage regulator (pin name: 3V3_IN, VCC, VDD)
Required properties (I2C):
- reg : I2C slave address
Required properties (SPI):
- reg : SPI chip select address
Optional properties:
- sirf,onoff-gpios : GPIO used to power on and off device (pin name: ON_OFF)
- sirf,wakeup-gpios : GPIO used to determine device power state
(pin name: RFPWRUP, WAKEUP)
- timepulse-gpios : Time pulse GPIO (pin name: 1PPS, TM)
Example:
serial@1234 {
compatible = "ns16550a";
gnss {
compatible = "wi2wi,w2sg0084i";
vcc-supply = <&gnss_reg>;
sirf,onoff-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
sirf,wakeup-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
};
};
Documentation/devicetree/bindings/gnss/sirfstar.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/gnss/sirfstar.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiRFstar GNSS Receiver Device Tree Bindings
maintainers:
- Johan Hovold <johan@kernel.org>
description:
The SiRFstar GNSS receivers have incarnated over the years in different
chips, starting from the SiRFstarIII which was a chip that was introduced in
2004 and used in a lot of dedicated GPS devices. In 2009 SiRF was acquired
by CSR (Cambridge Silicon Radio) and in 2012 the CSR GPS business was
acquired by Samsung, while some products remained with CSR. In 2014 CSR
was acquired by Qualcomm who still sell some of the SiRF products.
SiRF chips can be used over UART, I2C or SPI buses.
allOf:
- $ref: gnss-common.yaml#
properties:
compatible:
enum:
- csr,gsd4t
- csr,csrg05ta03-icje-r
- fastrax,uc430
- linx,r4
- wi2wi,w2sg0004
- wi2wi,w2sg0008i
- wi2wi,w2sg0084i
reg:
description:
The I2C Address, SPI chip select address. Not required on UART buses.
vcc-supply:
description:
Main voltage regulator, pin names such as 3V3_IN, VCC, VDD.
reset-gpios:
maxItems: 1
description: An optional active low reset line, should be flagged with
GPIO_ACTIVE_LOW.
sirf,onoff-gpios:
maxItems: 1
description: GPIO used to power on and off device, pin name ON_OFF.
sirf,wakeup-gpios:
maxItems: 1
description: GPIO used to determine device power state, pin names such
as RFPWRUP, WAKEUP.
required:
- compatible
- vcc-supply
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
serial {
gnss {
compatible = "wi2wi,w2sg0084i";
vcc-supply = <&gnss_vcc_reg>;
reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
sirf,onoff-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>;
sirf,wakeup-gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
current-speed = <38400>;
};
};
Documentation/devicetree/bindings/gnss/u-blox,neo-6m.yaml
View file @ 9bf3fc50
......@@ -6,6 +6,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: U-blox GNSS Receiver Device Tree Bindings
allOf:
- $ref: gnss-common.yaml#
maintainers:
- Johan Hovold <johan@kernel.org>
......@@ -29,11 +32,6 @@ properties:
description: >
Main voltage regulator
timepulse-gpios:
maxItems: 1
description: >
Time pulse GPIO
u-blox,extint-gpios:
maxItems: 1
description: >
......@@ -43,13 +41,11 @@ properties:
description: >
Backup voltage regulator
current-speed: true
required:
- compatible
- vcc-supply
additionalProperties: false
unevaluatedProperties: false
examples:
- |
......
Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml
View file @ 9bf3fc50
......@@ -190,14 +190,6 @@ examples:
"chg-status+red", "green", "blue", "en-esata",
"fault1", "p26", "p27";
};
ts3a227@3b {
compatible = "ti,ts3a227e";
reg = <0x3b>;
interrupt-parent = <&gpio99>;
interrupts = <14 IRQ_TYPE_EDGE_RISING>;
ti,micbias = <0>; /* 2.1V */
};
};
- |
......
Documentation/devicetree/bindings/i2c/atmel,at91sam-i2c.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/atmel,at91sam-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: I2C for Atmel/Microchip platforms
maintainers:
- Alexandre Belloni <alexandre.belloni@bootlin.com>
properties:
compatible:
oneOf:
- items:
- enum:
- atmel,at91rm9200-i2c
- atmel,at91sam9261-i2c
- atmel,at91sam9260-i2c
- atmel,at91sam9g20-i2c
- atmel,at91sam9g10-i2c
- atmel,at91sam9x5-i2c
- atmel,sama5d4-i2c
- atmel,sama5d2-i2c
- microchip,sam9x60-i2c
- items:
- const: microchip,sama7g5-i2c
- const: microchip,sam9x60-i2c
reg:
maxItems: 1
interrupts:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
clocks:
maxItems: 1
clock-frequency:
default: 100000
dmas:
items:
- description: TX DMA Channel Specifier
- description: RX DMA Channel Specifier
dma-names:
items:
- const: tx
- const: rx
atmel,fifo-size:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
Maximum number of data the RX and TX FIFOs can store for
FIFO capable I2C controllers.
scl-gpios: true
sda-gpios: true
required:
- compatible
- reg
- interrupts
- "#address-cells"
- "#size-cells"
- clocks
allOf:
- $ref: "i2c-controller.yaml"
- if:
properties:
compatible:
contains:
enum:
- atmel,sama5d4-i2c
- atmel,sama5d2-i2c
- microchip,sam9x60-i2c
- microchip,sama7g5-i2c
then:
properties:
i2c-sda-hold-time-ns:
description:
TWD hold time
maxItems: 1
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/dma/at91.h>
#include <dt-bindings/gpio/gpio.h>
i2c0: i2c@fff84000 {
compatible = "atmel,at91sam9g20-i2c";
reg = <0xfff84000 0x100>;
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&twi0_clk>;
clock-frequency = <400000>;
eeprom@50 {
compatible = "atmel,24c512";
reg = <0x50>;
pagesize = <128>;
};
};
i2c1: i2c@f8034600 {
compatible = "atmel,sama5d2-i2c";
reg = <0xf8034600 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
AT91_XDMAC_DT_PERID(11)>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
AT91_XDMAC_DT_PERID(12)>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&flx0>;
atmel,fifo-size = <16>;
i2c-sda-hold-time-ns = <336>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
eeprom@54 {
compatible = "atmel,24c02";
reg = <0x54>;
pagesize = <16>;
};
};
Documentation/devicetree/bindings/i2c/i2c-at91.txt deleted 100644 → 0
View file @ bddac7c1
I2C for Atmel platforms
Required properties :
- compatible : Must be one of:
"atmel,at91rm9200-i2c",
"atmel,at91sam9261-i2c",
"atmel,at91sam9260-i2c",
"atmel,at91sam9g20-i2c",
"atmel,at91sam9g10-i2c",
"atmel,at91sam9x5-i2c",
"atmel,sama5d4-i2c",
"atmel,sama5d2-i2c",
"microchip,sam9x60-i2c".
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
- #address-cells = <1>;
- #size-cells = <0>;
- clocks: phandles to input clocks.
Optional properties:
- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000
- dmas: A list of two dma specifiers, one for each entry in dma-names.
- dma-names: should contain "tx" and "rx".
- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
capable I2C controllers.
- i2c-sda-hold-time-ns: TWD hold time, only available for:
"atmel,sama5d4-i2c",
"atmel,sama5d2-i2c",
"microchip,sam9x60-i2c".
- scl-gpios: specify the gpio related to SCL pin
- sda-gpios: specify the gpio related to SDA pin
- pinctrl: add extra pinctrl to configure i2c pins to gpio function for i2c
bus recovery, call it "gpio" state
- Child nodes conforming to i2c bus binding
Examples :
i2c0: i2c@fff84000 {
compatible = "atmel,at91sam9g20-i2c";
reg = <0xfff84000 0x100>;
interrupts = <12 4 6>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&twi0_clk>;
clock-frequency = <400000>;
24c512@50 {
compatible = "atmel,24c512";
reg = <0x50>;
pagesize = <128>;
}
}
i2c0: i2c@f8034600 {
compatible = "atmel,sama5d2-i2c";
reg = <0xf8034600 0x100>;
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
AT91_XDMAC_DT_PERID(11)>,
<&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
AT91_XDMAC_DT_PERID(12)>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&flx0>;
atmel,fifo-size = <16>;
i2c-sda-hold-time-ns = <336>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c0>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
wm8731: wm8731@1a {
compatible = "wm8731";
reg = <0x1a>;
};
};
Documentation/devicetree/bindings/i2c/i2c-imx.yaml
View file @ 9bf3fc50
......@@ -88,9 +88,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/imx5-clock.h>
#include <dt-bindings/clock/vf610-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
i2c@83fc4000 {
compatible = "fsl,imx51-i2c", "fsl,imx21-i2c";
......@@ -99,6 +97,9 @@ examples:
clocks = <&clks IMX5_CLK_I2C2_GATE>;
};
- |
#include <dt-bindings/clock/vf610-clock.h>
i2c@40066000 {
compatible = "fsl,vf610-i2c";
reg = <0x40066000 0x1000>;
......
Documentation/devicetree/bindings/i2c/i2c-mpc.yaml
View file @ 9bf3fc50
......@@ -73,6 +73,7 @@ examples:
clock-frequency = <100000>;
};
- |
/* MPC5200B based board */
i2c@3d00 {
#address-cells = <1>;
......@@ -84,6 +85,7 @@ examples:
fsl,preserve-clocking;
};
- |
/* MPC8544 base board */
i2c@3100 {
#address-cells = <1>;
......
Documentation/devicetree/bindings/i2c/i2c-s3c2410.txt deleted 100644 → 0
View file @ bddac7c1
* Samsung's I2C controller
The Samsung's I2C controller is used to interface with I2C devices.
Required properties:
- compatible: value should be either of the following.
(a) "samsung, s3c2410-i2c", for i2c compatible with s3c2410 i2c.
(b) "samsung, s3c2440-i2c", for i2c compatible with s3c2440 i2c.
(c) "samsung, s3c2440-hdmiphy-i2c", for s3c2440-like i2c used
inside HDMIPHY block found on several samsung SoCs
(d) "samsung, exynos5-sata-phy-i2c", for s3c2440-like i2c used as
a host to SATA PHY controller on an internal bus.
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt number to the cpu.
- samsung,i2c-sda-delay: Delay (in ns) applied to data line (SDA) edges.
Required for all cases except "samsung,s3c2440-hdmiphy-i2c":
- Samsung GPIO variant (deprecated):
- gpios: The order of the gpios should be the following: <SDA, SCL>.
The gpio specifier depends on the gpio controller. Required in all
cases except for "samsung,s3c2440-hdmiphy-i2c" whose input/output
lines are permanently wired to the respective clienta
- Pinctrl variant (preferred, if available):
- pinctrl-0: Pin control group to be used for this controller.
- pinctrl-names: Should contain only one value - "default".
Optional properties:
- samsung,i2c-slave-addr: Slave address in multi-master environment. If not
specified, default value is 0.
- samsung,i2c-max-bus-freq: Desired frequency in Hz of the bus. If not
specified, the default value in Hz is 100000.
- samsung,sysreg-phandle - handle to syscon used to control the system registers
Example:
i2c@13870000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
interrupts = <345>;
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <100000>;
/* Samsung GPIO variant begins here */
gpios = <&gpd1 2 0 /* SDA */
&gpd1 3 0 /* SCL */>;
/* Samsung GPIO variant ends here */
/* Pinctrl variant begins here */
pinctrl-0 = <&i2c3_bus>;
pinctrl-names = "default";
/* Pinctrl variant ends here */
#address-cells = <1>;
#size-cells = <0>;
wm8994@1a {
compatible = "wlf,wm8994";
reg = <0x1a>;
};
};
Documentation/devicetree/bindings/i2c/ingenic,i2c.yaml
View file @ 9bf3fc50
......@@ -69,8 +69,7 @@ examples:
#size-cells = <0>;
reg = <0x10054000 0x1000>;
interrupt-parent = <&intc>;
interrupts = <56>;
interrupts = <56 IRQ_TYPE_LEVEL_LOW>;
clocks = <&cgu JZ4780_CLK_SMB4>;
pinctrl-names = "default";
......@@ -86,7 +85,6 @@ examples:
compatible = "nxp,pcf8563";
reg = <0x51>;
interrupt-parent = <&gpf>;
interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
};
};
Documentation/devicetree/bindings/i2c/renesas,riic.yaml
View file @ 9bf3fc50
......@@ -20,6 +20,7 @@ properties:
- renesas,riic-r7s72100 # RZ/A1H
- renesas,riic-r7s9210 # RZ/A2M
- renesas,riic-r9a07g044 # RZ/G2{L,LC}
- renesas,riic-r9a07g054 # RZ/V2L
- const: renesas,riic-rz # RZ/A or RZ/G2L
reg:
......@@ -75,6 +76,7 @@ if:
contains:
enum:
- renesas,riic-r9a07g044
- renesas,riic-r9a07g054
then:
required:
- resets
......
Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml 0 → 100644
View file @ 9bf3fc50
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/i2c/samsung,s3c2410-i2c.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S3C/S5P/Exynos SoC I2C Controller
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
properties:
compatible:
enum:
- samsung,s3c2410-i2c
- samsung,s3c2440-i2c
# For s3c2440-like I2C used inside HDMIPHY block found on several SoCs:
- samsung,s3c2440-hdmiphy-i2c
# For s3c2440-like I2C used as a host to SATA PHY controller on an
# internal bus:
- samsung,exynos5-sata-phy-i2c
'#address-cells':
const: 1
clocks:
maxItems: 1
clock-names:
items:
- const: i2c
gpios:
description: |
The order of the GPIOs should be the following:: <SDA, SCL>. The GPIO
specifier depends on the gpio controller. Required in all cases except
for "samsung,s3c2440-hdmiphy-i2c" whose input/output lines are
permanently wired to the respective client.
This property is deprecated. Use "pinctrl-0" and "pinctrl-names" instead.
deprecated: yes
interrupts:
maxItems: 1
reg:
maxItems: 1
samsung,i2c-max-bus-freq:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Desired frequency in Hz of the bus.
default: 100000
samsung,i2c-sda-delay:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Delay (in ns) applied to data line (SDA) edges.
default: 0
samsung,i2c-slave-addr:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Slave address in multi-master environment.
default: 0
samsung,sysreg-phandle:
$ref: /schemas/types.yaml#/definitions/phandle
description: Pandle to syscon used to control the system registers.
'#size-cells':
const: 0
required:
- compatible
- reg
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
- if:
properties:
compatible:
contains:
enum:
- samsung,s3c2440-hdmiphy-i2c
- samsung,exynos5-sata-phy-i2c
then:
properties:
gpios: false
- if:
properties:
compatible:
contains:
enum:
- samsung,s3c2410-i2c
- samsung,s3c2440-i2c
- samsung,s3c2440-hdmiphy-i2c
then:
required:
- interrupts
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/exynos5250.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
i2c@12c60000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C60000 0x100>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C0>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_bus>;
samsung,sysreg-phandle = <&sysreg_system_controller>;
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <20000>;
samsung,i2c-slave-addr = <0x66>;
eeprom@50 {
compatible = "samsung,s524ad0xd1";
reg = <0x50>;
};
};
i2c@12ce0000 {
compatible = "samsung,s3c2440-hdmiphy-i2c";
reg = <0x12CE0000 0x1000>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_I2C_HDMI>;
clock-names = "i2c";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <66000>;
phy-i2c@38 {
compatible = "samsung,exynos4212-hdmiphy";
reg = <0x38>;
};
};
i2c@121d0000 {
compatible = "samsung,exynos5-sata-phy-i2c";
reg = <0x121D0000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_SATA_PHYI2C>;
clock-names = "i2c";
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <40000>;
phy-i2c@38 {
compatible = "samsung,exynos-sataphy-i2c";
reg = <0x38>;
};
};
Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml
View file @ 9bf3fc50
......@@ -25,16 +25,9 @@ allOf:
i2c-scl-falling-time-ns:
default: 10
st,syscfg-fmp:
description: Use to set Fast Mode Plus bit within SYSCFG when
Fast Mode Plus speed is selected by slave.
Format is phandle to syscfg / register offset within
syscfg / register bitmask for FMP bit.
$ref: "/schemas/types.yaml#/definitions/phandle-array"
items:
minItems: 3
maxItems: 3
else:
properties:
st,syscfg-fmp: false
- if:
properties:
......@@ -87,6 +80,16 @@ properties:
minimum: 1
maximum: 1000000
st,syscfg-fmp:
description: Use to set Fast Mode Plus bit within SYSCFG when Fast Mode
Plus speed is selected by slave.
$ref: "/schemas/types.yaml#/definitions/phandle-array"
items:
- items:
- description: phandle to syscfg
- description: register offset within syscfg
- description: register bitmask for FMP bit
required:
- compatible
- reg
......@@ -147,4 +150,3 @@ examples:
i2c-scl-falling-time-ns = <20>;
st,syscfg-fmp = <&syscfg 0x4 0x2>;
};
...
Documentation/devicetree/bindings/input/adc-joystick.yaml
View file @ 9bf3fc50
......@@ -61,9 +61,8 @@ patternProperties:
description: EV_ABS specific event code generated by the axis.
abs-range:
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32-array
- items:
$ref: /schemas/types.yaml#/definitions/uint32-array
items:
- description: minimum value
- description: maximum value
description: >
......
Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
View file @ 9bf3fc50
......@@ -121,6 +121,8 @@ properties:
qcom,bcm-voters:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description: |
List of phandles to qcom,bcm-voter nodes that are required by
this interconnect to send RPMh commands.
......
Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
View file @ 9bf3fc50
......@@ -138,6 +138,8 @@ properties:
properties:
affinity:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description:
Should be a list of phandles to CPU nodes (as described in
Documentation/devicetree/bindings/arm/cpus.yaml).
......@@ -273,11 +275,11 @@ examples:
ppi-partitions {
part0: interrupt-partition-0 {
affinity = <&cpu0 &cpu2>;
affinity = <&cpu0>, <&cpu2>;
};
part1: interrupt-partition-1 {
affinity = <&cpu1 &cpu3>;
affinity = <&cpu1>, <&cpu3>;
};
};
};
......
Documentation/devicetree/bindings/interrupt-controller/ti,sci-inta.yaml
View file @ 9bf3fc50
......@@ -77,6 +77,8 @@ properties:
ti,unmapped-event-sources:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description:
Array of phandles to DMA controllers where the unmapped events originate.
......
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
View file @ 9bf3fc50
......@@ -101,6 +101,8 @@ properties:
$ref: /schemas/types.yaml#/definitions/phandle-array
minItems: 1
maxItems: 32
items:
maxItems: 1
description: |
List of phandle to the local arbiters in the current Socs.
Refer to bindings/memory-controllers/mediatek,smi-larb.yaml. It must sort
......@@ -167,8 +169,8 @@ examples:
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_INFRA_M4U>;
clock-names = "bclk";
mediatek,larbs = <&larb0 &larb1 &larb2
&larb3 &larb4 &larb5>;
mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
<&larb3>, <&larb4>, <&larb5>;
#iommu-cells = <1>;
};
......
Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
View file @ 9bf3fc50
......@@ -70,6 +70,12 @@ properties:
renesas,ipmmu-main:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to main IPMMU
- description: the interrupt bit number associated with the particular
cache IPMMU device. The interrupt bit number needs to match the main
IPMMU IMSSTR register. Only used by cache IPMMU instances.
description:
Reference to the main IPMMU phandle plus 1 cell. The cell is
the interrupt bit number associated with the particular cache IPMMU
......
Documentation/devicetree/bindings/leds/backlight/led-backlight.yaml
View file @ 9bf3fc50
......@@ -23,6 +23,8 @@ properties:
leds:
description: A list of LED nodes
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
brightness-levels:
description:
......
Documentation/devicetree/bindings/leds/cznic,turris-omnia-leds.yaml
View file @ 9bf3fc50
......@@ -32,8 +32,7 @@ properties:
patternProperties:
"^multi-led@[0-9a-b]$":
type: object
allOf:
- $ref: leds-class-multicolor.yaml#
$ref: leds-class-multicolor.yaml#
description:
This node represents one of the RGB LED devices on Turris Omnia.
No subnodes need to be added for subchannels since this controller only
......
Documentation/devicetree/bindings/leds/leds-lp50xx.yaml
View file @ 9bf3fc50
......@@ -55,8 +55,7 @@ properties:
patternProperties:
'^multi-led@[0-9a-f]$':
type: object
allOf:
- $ref: leds-class-multicolor.yaml#
$ref: leds-class-multicolor.yaml#
properties:
reg:
minItems: 1
......
Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml
View file @ 9bf3fc50
......@@ -48,6 +48,10 @@ properties:
allwinner,sram:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to SRAM
- description: register value for device
description: Phandle to the device SRAM
iommus:
......
Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
View file @ 9bf3fc50
......@@ -58,7 +58,7 @@ properties:
req_gpr is the gpr register offset of RX_ENABLE for the mipi phy.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- items:
- description: The 'gpr' is the phandle to general purpose register node.
- description: The 'req_gpr' is the gpr register offset containing
CSI2_1_RX_ENABLE or CSI2_2_RX_ENABLE respectively.
......
Documentation/devicetree/bindings/media/ti,cal.yaml
View file @ 9bf3fc50
......@@ -48,6 +48,10 @@ properties:
ti,camerrx-control:
$ref: "/schemas/types.yaml#/definitions/phandle-array"
items:
- items:
- description: phandle to device control module
- description: offset to the control_camerarx_core register
description:
phandle to the device control module and offset to the
control_camerarx_core register
......
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
View file @ 9bf3fc50
......@@ -53,7 +53,7 @@ properties:
maxItems: 1
mediatek,smi:
$ref: /schemas/types.yaml#/definitions/phandle-array
$ref: /schemas/types.yaml#/definitions/phandle
description: a phandle to the smi_common node.
mediatek,larb-id:
......
Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml
View file @ 9bf3fc50
......@@ -45,6 +45,8 @@ properties:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
minItems: 1
maxItems: 16
items:
maxItems: 1
description: phandles of the PPMU events used by the controller.
device-handle:
......
Documentation/devicetree/bindings/mfd/google,cros-ec.yaml
View file @ 9bf3fc50
......@@ -38,18 +38,14 @@ properties:
description:
This property specifies the delay in usecs between the
assertion of the CS and the first clock pulse.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- default: 0
- minimum: 0
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
google,cros-ec-spi-msg-delay:
description:
This property specifies the delay in usecs between messages.
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
- default: 0
- minimum: 0
$ref: /schemas/types.yaml#/definitions/uint32
default: 0
google,has-vbc-nvram:
description:
......
Documentation/devicetree/bindings/mtd/rockchip,nand-controller.yaml
View file @ 9bf3fc50
......@@ -96,8 +96,7 @@ patternProperties:
rockchip,boot-ecc-strength:
enum: [16, 24, 40, 60, 70]
allOf:
- $ref: /schemas/types.yaml#/definitions/uint32
$ref: /schemas/types.yaml#/definitions/uint32
description: |
If specified it indicates that a different BCH/ECC setting is
supported by the boot ROM.
......
Documentation/devicetree/bindings/net/allwinner,sun4i-a10-emac.yaml
View file @ 9bf3fc50
......@@ -29,6 +29,10 @@ properties:
allwinner,sram:
description: Phandle to the device SRAM
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to SRAM
- description: register value for device
required:
- compatible
......
Documentation/devicetree/bindings/net/can/bosch,c_can.yaml
View file @ 9bf3fc50
......@@ -56,7 +56,7 @@ properties:
offset).
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- items:
- description: The phandle to the system control region.
- description: The register offset.
- description: The CAN instance number.
......
Documentation/devicetree/bindings/net/can/bosch,m_can.yaml
View file @ 9bf3fc50
......@@ -104,6 +104,7 @@ properties:
- description: Tx Buffers 0-32 elements / 0-576 words
minimum: 0
maximum: 32
minItems: 1
power-domains:
description:
......
Documentation/devicetree/bindings/net/can/fsl,flexcan.yaml
View file @ 9bf3fc50
......@@ -84,7 +84,7 @@ properties:
req_bit is the bit offset of CAN stop request.
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- items:
- description: The 'gpr' is the phandle to general purpose register node.
- description: The 'req_gpr' is the gpr register offset of CAN stop request.
maximum: 0xff
......
Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml
View file @ 9bf3fc50
......@@ -33,6 +33,7 @@ properties:
- items:
- enum:
- renesas,r9a07g044-canfd # RZ/G2{L,LC}
- renesas,r9a07g054-canfd # RZ/V2L
- const: renesas,rzg2l-canfd # RZ/G2L family
- const: renesas,r8a779a0-canfd # R-Car V3U
......
Documentation/devicetree/bindings/net/cortina,gemini-ethernet.txt deleted 100644 → 0
View file @ bddac7c1
Cortina Systems Gemini Ethernet Controller
==========================================
This ethernet controller is found in the Gemini SoC family:
StorLink SL3512 and SL3516, also known as Cortina Systems
CS3512 and CS3516.
Required properties:
- compatible: must be "cortina,gemini-ethernet"
- reg: must contain the global registers and the V-bit and A-bit
memory areas, in total three register sets.
- syscon: a phandle to the system controller
- #address-cells: must be specified, must be <1>
- #size-cells: must be specified, must be <1>
- ranges: should be state like this giving a 1:1 address translation
for the subnodes
The subnodes represents the two ethernet ports in this device.
They are not independent of each other since they share resources
in the parent node, and are thus children.
Required subnodes:
- port0: contains the resources for ethernet port 0
- port1: contains the resources for ethernet port 1
Required subnode properties:
- compatible: must be "cortina,gemini-ethernet-port"
- reg: must contain two register areas: the DMA/TOE memory and
the GMAC memory area of the port
- interrupts: should contain the interrupt line of the port.
this is nominally a level interrupt active high.
- resets: this must provide an SoC-integrated reset line for
the port.
- clocks: this should contain a handle to the PCLK clock for
clocking the silicon in this port
- clock-names: must be "PCLK"
Optional subnode properties:
- phy-mode: see ethernet.txt
- phy-handle: see ethernet.txt
Example:
mdio-bus {
(...)
phy0: ethernet-phy@1 {
reg = <1>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@3 {
reg = <3>;
device_type = "ethernet-phy";
};
};
ethernet@60000000 {
compatible = "cortina,gemini-ethernet";
reg = <0x60000000 0x4000>, /* Global registers, queue */
<0x60004000 0x2000>, /* V-bit */
<0x60006000 0x2000>; /* A-bit */
syscon = <&syscon>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gmac0: ethernet-port@0 {
compatible = "cortina,gemini-ethernet-port";
reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
<0x6000a000 0x2000>; /* Port 0 GMAC */
interrupt-parent = <&intcon>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon GEMINI_RESET_GMAC0>;
clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
clock-names = "PCLK";
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
gmac1: ethernet-port@1 {
compatible = "cortina,gemini-ethernet-port";
reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
<0x6000e000 0x2000>; /* Port 1 GMAC */
interrupt-parent = <&intcon>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon GEMINI_RESET_GMAC1>;
clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
clock-names = "PCLK";
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
};
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/cortina,gemini-ethernet.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cortina Systems Gemini Ethernet Controller
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
description: |
This ethernet controller is found in the Gemini SoC family:
StorLink SL3512 and SL3516, also known as Cortina Systems
CS3512 and CS3516.
properties:
compatible:
const: cortina,gemini-ethernet
reg:
minItems: 3
description: must contain the global registers and the V-bit and A-bit
memory areas, in total three register sets.
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
#The subnodes represents the two ethernet ports in this device.
#They are not independent of each other since they share resources
#in the parent node, and are thus children.
patternProperties:
"^ethernet-port@[0-9]+$":
type: object
description: contains the resources for ethernet port
allOf:
- $ref: ethernet-controller.yaml#
properties:
compatible:
const: cortina,gemini-ethernet-port
reg:
items:
- description: DMA/TOE memory
- description: GMAC memory area of the port
interrupts:
maxItems: 1
description: should contain the interrupt line of the port.
this is nominally a level interrupt active high.
resets:
maxItems: 1
description: this must provide an SoC-integrated reset line for the port.
clocks:
maxItems: 1
description: this should contain a handle to the PCLK clock for
clocking the silicon in this port
clock-names:
const: PCLK
required:
- reg
- compatible
- interrupts
- resets
- clocks
- clock-names
required:
- compatible
- reg
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/cortina,gemini-clock.h>
#include <dt-bindings/reset/cortina,gemini-reset.h>
mdio0: mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@1 {
reg = <1>;
device_type = "ethernet-phy";
};
phy1: ethernet-phy@3 {
reg = <3>;
device_type = "ethernet-phy";
};
};
ethernet@60000000 {
compatible = "cortina,gemini-ethernet";
reg = <0x60000000 0x4000>, /* Global registers, queue */
<0x60004000 0x2000>, /* V-bit */
<0x60006000 0x2000>; /* A-bit */
#address-cells = <1>;
#size-cells = <1>;
ranges;
gmac0: ethernet-port@0 {
compatible = "cortina,gemini-ethernet-port";
reg = <0x60008000 0x2000>, /* Port 0 DMA/TOE */
<0x6000a000 0x2000>; /* Port 0 GMAC */
interrupt-parent = <&intcon>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon GEMINI_RESET_GMAC0>;
clocks = <&syscon GEMINI_CLK_GATE_GMAC0>;
clock-names = "PCLK";
phy-mode = "rgmii";
phy-handle = <&phy0>;
};
gmac1: ethernet-port@1 {
compatible = "cortina,gemini-ethernet-port";
reg = <0x6000c000 0x2000>, /* Port 1 DMA/TOE */
<0x6000e000 0x2000>; /* Port 1 GMAC */
interrupt-parent = <&intcon>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
resets = <&syscon GEMINI_RESET_GMAC1>;
clocks = <&syscon GEMINI_CLK_GATE_GMAC1>;
clock-names = "PCLK";
phy-mode = "rgmii";
phy-handle = <&phy1>;
};
};
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