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Commit a61fb707 authored by Weili Qian's avatar Weili Qian Committed by Herbert Xu
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crypto: hisilicon/qm - remove incorrect type cast 

The 'offset' type is unsigned long in 'struct debugfs_reg32',
so type of values casts to unsigned long long is incorrect, and the
values do not require type cast, remove them.
Signed-off-by: default avatarWeili Qian <qianweili@huawei.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 66e6fb1e
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Showing with 52 additions and 52 deletions
drivers/crypto/hisilicon/debugfs.c
View file @ a61fb707
...@@ -53,34 +53,34 @@ static struct qm_dfx_item qm_dfx_files[] = { ...@@ -53,34 +53,34 @@ static struct qm_dfx_item qm_dfx_files[] = {
#define CNT_CYC_REGS_NUM 10 #define CNT_CYC_REGS_NUM 10
static const struct debugfs_reg32 qm_dfx_regs[] = { static const struct debugfs_reg32 qm_dfx_regs[] = {
/* XXX_CNT are reading clear register */ /* XXX_CNT are reading clear register */
{"QM_ECC_1BIT_CNT ", 0x104000ull}, {"QM_ECC_1BIT_CNT ", 0x104000},
{"QM_ECC_MBIT_CNT ", 0x104008ull}, {"QM_ECC_MBIT_CNT ", 0x104008},
{"QM_DFX_MB_CNT ", 0x104018ull}, {"QM_DFX_MB_CNT ", 0x104018},
{"QM_DFX_DB_CNT ", 0x104028ull}, {"QM_DFX_DB_CNT ", 0x104028},
{"QM_DFX_SQE_CNT ", 0x104038ull}, {"QM_DFX_SQE_CNT ", 0x104038},
{"QM_DFX_CQE_CNT ", 0x104048ull}, {"QM_DFX_CQE_CNT ", 0x104048},
{"QM_DFX_SEND_SQE_TO_ACC_CNT ", 0x104050ull}, {"QM_DFX_SEND_SQE_TO_ACC_CNT ", 0x104050},
{"QM_DFX_WB_SQE_FROM_ACC_CNT ", 0x104058ull}, {"QM_DFX_WB_SQE_FROM_ACC_CNT ", 0x104058},
{"QM_DFX_ACC_FINISH_CNT ", 0x104060ull}, {"QM_DFX_ACC_FINISH_CNT ", 0x104060},
{"QM_DFX_CQE_ERR_CNT ", 0x1040b4ull}, {"QM_DFX_CQE_ERR_CNT ", 0x1040b4},
{"QM_DFX_FUNS_ACTIVE_ST ", 0x200ull}, {"QM_DFX_FUNS_ACTIVE_ST ", 0x200},
{"QM_ECC_1BIT_INF ", 0x104004ull}, {"QM_ECC_1BIT_INF ", 0x104004},
{"QM_ECC_MBIT_INF ", 0x10400cull}, {"QM_ECC_MBIT_INF ", 0x10400c},
{"QM_DFX_ACC_RDY_VLD0 ", 0x1040a0ull}, {"QM_DFX_ACC_RDY_VLD0 ", 0x1040a0},
{"QM_DFX_ACC_RDY_VLD1 ", 0x1040a4ull}, {"QM_DFX_ACC_RDY_VLD1 ", 0x1040a4},
{"QM_DFX_AXI_RDY_VLD ", 0x1040a8ull}, {"QM_DFX_AXI_RDY_VLD ", 0x1040a8},
{"QM_DFX_FF_ST0 ", 0x1040c8ull}, {"QM_DFX_FF_ST0 ", 0x1040c8},
{"QM_DFX_FF_ST1 ", 0x1040ccull}, {"QM_DFX_FF_ST1 ", 0x1040cc},
{"QM_DFX_FF_ST2 ", 0x1040d0ull}, {"QM_DFX_FF_ST2 ", 0x1040d0},
{"QM_DFX_FF_ST3 ", 0x1040d4ull}, {"QM_DFX_FF_ST3 ", 0x1040d4},
{"QM_DFX_FF_ST4 ", 0x1040d8ull}, {"QM_DFX_FF_ST4 ", 0x1040d8},
{"QM_DFX_FF_ST5 ", 0x1040dcull}, {"QM_DFX_FF_ST5 ", 0x1040dc},
{"QM_DFX_FF_ST6 ", 0x1040e0ull}, {"QM_DFX_FF_ST6 ", 0x1040e0},
{"QM_IN_IDLE_ST ", 0x1040e4ull}, {"QM_IN_IDLE_ST ", 0x1040e4},
}; };
static const struct debugfs_reg32 qm_vf_dfx_regs[] = { static const struct debugfs_reg32 qm_vf_dfx_regs[] = {
{"QM_DFX_FUNS_ACTIVE_ST ", 0x200ull}, {"QM_DFX_FUNS_ACTIVE_ST ", 0x200},
}; };
/* define the QM's dfx regs region and region length */ /* define the QM's dfx regs region and region length */
......
drivers/crypto/hisilicon/zip/zip_main.c
View file @ a61fb707
...@@ -270,28 +270,28 @@ static const u64 core_offsets[] = { ...@@ -270,28 +270,28 @@ static const u64 core_offsets[] = {
}; };
static const struct debugfs_reg32 hzip_dfx_regs[] = { static const struct debugfs_reg32 hzip_dfx_regs[] = {
{"HZIP_GET_BD_NUM ", 0x00ull}, {"HZIP_GET_BD_NUM ", 0x00},
{"HZIP_GET_RIGHT_BD ", 0x04ull}, {"HZIP_GET_RIGHT_BD ", 0x04},
{"HZIP_GET_ERROR_BD ", 0x08ull}, {"HZIP_GET_ERROR_BD ", 0x08},
{"HZIP_DONE_BD_NUM ", 0x0cull}, {"HZIP_DONE_BD_NUM ", 0x0c},
{"HZIP_WORK_CYCLE ", 0x10ull}, {"HZIP_WORK_CYCLE ", 0x10},
{"HZIP_IDLE_CYCLE ", 0x18ull}, {"HZIP_IDLE_CYCLE ", 0x18},
{"HZIP_MAX_DELAY ", 0x20ull}, {"HZIP_MAX_DELAY ", 0x20},
{"HZIP_MIN_DELAY ", 0x24ull}, {"HZIP_MIN_DELAY ", 0x24},
{"HZIP_AVG_DELAY ", 0x28ull}, {"HZIP_AVG_DELAY ", 0x28},
{"HZIP_MEM_VISIBLE_DATA ", 0x30ull}, {"HZIP_MEM_VISIBLE_DATA ", 0x30},
{"HZIP_MEM_VISIBLE_ADDR ", 0x34ull}, {"HZIP_MEM_VISIBLE_ADDR ", 0x34},
{"HZIP_CONSUMED_BYTE ", 0x38ull}, {"HZIP_CONSUMED_BYTE ", 0x38},
{"HZIP_PRODUCED_BYTE ", 0x40ull}, {"HZIP_PRODUCED_BYTE ", 0x40},
{"HZIP_COMP_INF ", 0x70ull}, {"HZIP_COMP_INF ", 0x70},
{"HZIP_PRE_OUT ", 0x78ull}, {"HZIP_PRE_OUT ", 0x78},
{"HZIP_BD_RD ", 0x7cull}, {"HZIP_BD_RD ", 0x7c},
{"HZIP_BD_WR ", 0x80ull}, {"HZIP_BD_WR ", 0x80},
{"HZIP_GET_BD_AXI_ERR_NUM ", 0x84ull}, {"HZIP_GET_BD_AXI_ERR_NUM ", 0x84},
{"HZIP_GET_BD_PARSE_ERR_NUM ", 0x88ull}, {"HZIP_GET_BD_PARSE_ERR_NUM ", 0x88},
{"HZIP_ADD_BD_AXI_ERR_NUM ", 0x8cull}, {"HZIP_ADD_BD_AXI_ERR_NUM ", 0x8c},
{"HZIP_DECOMP_STF_RELOAD_CURR_ST ", 0x94ull}, {"HZIP_DECOMP_STF_RELOAD_CURR_ST ", 0x94},
{"HZIP_DECOMP_LZ77_CURR_ST ", 0x9cull}, {"HZIP_DECOMP_LZ77_CURR_ST ", 0x9c},
}; };
static const struct debugfs_reg32 hzip_com_dfx_regs[] = { static const struct debugfs_reg32 hzip_com_dfx_regs[] = {
...@@ -303,11 +303,11 @@ static const struct debugfs_reg32 hzip_com_dfx_regs[] = { ...@@ -303,11 +303,11 @@ static const struct debugfs_reg32 hzip_com_dfx_regs[] = {
}; };
static const struct debugfs_reg32 hzip_dump_dfx_regs[] = { static const struct debugfs_reg32 hzip_dump_dfx_regs[] = {
{"HZIP_GET_BD_NUM ", 0x00ull}, {"HZIP_GET_BD_NUM ", 0x00},
{"HZIP_GET_RIGHT_BD ", 0x04ull}, {"HZIP_GET_RIGHT_BD ", 0x04},
{"HZIP_GET_ERROR_BD ", 0x08ull}, {"HZIP_GET_ERROR_BD ", 0x08},
{"HZIP_DONE_BD_NUM ", 0x0cull}, {"HZIP_DONE_BD_NUM ", 0x0c},
{"HZIP_MAX_DELAY ", 0x20ull}, {"HZIP_MAX_DELAY ", 0x20},
}; };
/* define the ZIP's dfx regs region and region length */ /* define the ZIP's dfx regs region and region length */
......
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