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Commit b0969341 authored by Larry Finger's avatar Larry Finger
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staging: rtl8192e: Cleanup checkpatch -f warnings and errors - Part IV 

Signed-off-by: default avatarLarry Finger <Larry.Finger@lwfinger.net>
parent 99a1f99f
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Showing with 799 additions and 750 deletions
drivers/staging/rtl8192e/r8192E_phy.c
View file @ b0969341
...@@ -47,26 +47,29 @@ static u32 RF_CHANNEL_TABLE_ZEBRA[] = { ...@@ -47,26 +47,29 @@ static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
/*************************Define local function prototype**********************/ /*************************Define local function prototype**********************/
static u32 phy_FwRFSerialRead(struct net_device* dev,enum rf90_radio_path eRFPath,u32 Offset); static u32 phy_FwRFSerialRead(struct net_device *dev,
static void phy_FwRFSerialWrite(struct net_device* dev,enum rf90_radio_path eRFPath,u32 Offset,u32 Data); enum rf90_radio_path eRFPath,
u32 Offset);
static void phy_FwRFSerialWrite(struct net_device *dev,
enum rf90_radio_path eRFPath,
u32 Offset, u32 Data);
u32 rtl8192_CalculateBitShift(u32 dwBitMask) u32 rtl8192_CalculateBitShift(u32 dwBitMask)
{ {
u32 i; u32 i;
for (i=0; i<=31; i++) for (i = 0; i <= 31; i++) {
{ if (((dwBitMask >> i) & 0x1) == 1)
if (((dwBitMask>>i)&0x1) == 1)
break; break;
} }
return i; return i;
} }
u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
{ {
u8 ret = 1; u8 ret = 1;
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
if (priv->rf_type == RF_2T4R) if (priv->rf_type == RF_2T4R)
ret = 0; ret = 0;
else if (priv->rf_type == RF_1T2R) else if (priv->rf_type == RF_1T2R) {
{
if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B) if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
ret = 1; ret = 1;
else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D) else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
...@@ -74,22 +77,25 @@ u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath) ...@@ -74,22 +77,25 @@ u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
} }
return ret; return ret;
} }
void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask,
u32 dwData)
{ {
u32 OriginalValue, BitShift, NewValue; u32 OriginalValue, BitShift, NewValue;
if (dwBitMask!= bMaskDWord) if (dwBitMask != bMaskDWord) {
{
OriginalValue = read_nic_dword(dev, dwRegAddr); OriginalValue = read_nic_dword(dev, dwRegAddr);
BitShift = rtl8192_CalculateBitShift(dwBitMask); BitShift = rtl8192_CalculateBitShift(dwBitMask);
NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift)); NewValue = (((OriginalValue) & (~dwBitMask)) |
(dwData << BitShift));
write_nic_dword(dev, dwRegAddr, NewValue); write_nic_dword(dev, dwRegAddr, NewValue);
}else } else
write_nic_dword(dev, dwRegAddr, dwData); write_nic_dword(dev, dwRegAddr, dwData);
return; return;
} }
u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask)
u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr, u32 dwBitMask)
{ {
u32 Ret = 0, OriginalValue, BitShift; u32 Ret = 0, OriginalValue, BitShift;
...@@ -97,60 +103,55 @@ u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask) ...@@ -97,60 +103,55 @@ u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask)
BitShift = rtl8192_CalculateBitShift(dwBitMask); BitShift = rtl8192_CalculateBitShift(dwBitMask);
Ret = (OriginalValue & dwBitMask) >> BitShift; Ret = (OriginalValue & dwBitMask) >> BitShift;
return (Ret); return Ret;
} }
u32 rtl8192_phy_RFSerialRead(struct net_device* dev, enum rf90_radio_path eRFPath, u32 Offset) u32 rtl8192_phy_RFSerialRead(struct net_device *dev,
enum rf90_radio_path eRFPath, u32 Offset)
{ {
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
u32 ret = 0; u32 ret = 0;
u32 NewOffset = 0; u32 NewOffset = 0;
struct bb_reg_definition* pPhyReg = &priv->PHYRegDef[eRFPath]; struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
Offset &= 0x3f; Offset &= 0x3f;
if (priv->rf_chip == RF_8256) if (priv->rf_chip == RF_8256) {
{
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
if (Offset >= 31) if (Offset >= 31) {
{
priv->RfReg0Value[eRFPath] |= 0x140; priv->RfReg0Value[eRFPath] |= 0x140;
rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
NewOffset = Offset -30; bMaskDWord,
} (priv->RfReg0Value[eRFPath]<<16));
else if (Offset >= 16) NewOffset = Offset - 30;
{ } else if (Offset >= 16) {
priv->RfReg0Value[eRFPath] |= 0x100; priv->RfReg0Value[eRFPath] |= 0x100;
priv->RfReg0Value[eRFPath] &= (~0x40); priv->RfReg0Value[eRFPath] &= (~0x40);
rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) ); rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
bMaskDWord,
(priv->RfReg0Value[eRFPath]<<16));
NewOffset = Offset - 15; NewOffset = Offset - 15;
} } else
else
NewOffset = Offset; NewOffset = Offset;
} } else {
else RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need"
{ " to be 8256\n");
RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
NewOffset = Offset; NewOffset = Offset;
} }
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset); rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress,
NewOffset);
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0); rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1); rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
mdelay(1);
msleep(1); ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack,
bLSSIReadBackData);
ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
if (priv->rf_chip == RF_8256) {
if (priv->rf_chip == RF_8256)
{
priv->RfReg0Value[eRFPath] &= 0xebf; priv->RfReg0Value[eRFPath] &= 0xebf;
rtl8192_setBBreg( rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord,
dev, (priv->RfReg0Value[eRFPath] << 16));
pPhyReg->rf3wireOffset,
bMaskDWord,
(priv->RfReg0Value[eRFPath] << 16));
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
} }
...@@ -160,36 +161,36 @@ u32 rtl8192_phy_RFSerialRead(struct net_device* dev, enum rf90_radio_path eRFPat ...@@ -160,36 +161,36 @@ u32 rtl8192_phy_RFSerialRead(struct net_device* dev, enum rf90_radio_path eRFPat
} }
void rtl8192_phy_RFSerialWrite(struct net_device* dev, enum rf90_radio_path eRFPath, u32 Offset, u32 Data) void rtl8192_phy_RFSerialWrite(struct net_device *dev,
enum rf90_radio_path eRFPath, u32 Offset,
u32 Data)
{ {
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
u32 DataAndAddr = 0, NewOffset = 0; u32 DataAndAddr = 0, NewOffset = 0;
struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath]; struct bb_reg_definition *pPhyReg = &priv->PHYRegDef[eRFPath];
Offset &= 0x3f; Offset &= 0x3f;
if (priv->rf_chip == RF_8256) if (priv->rf_chip == RF_8256) {
{
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);
if (Offset >= 31) if (Offset >= 31) {
{
priv->RfReg0Value[eRFPath] |= 0x140; priv->RfReg0Value[eRFPath] |= 0x140;
rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16)); rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
bMaskDWord,
(priv->RfReg0Value[eRFPath] << 16));
NewOffset = Offset - 30; NewOffset = Offset - 30;
} } else if (Offset >= 16) {
else if (Offset >= 16)
{
priv->RfReg0Value[eRFPath] |= 0x100; priv->RfReg0Value[eRFPath] |= 0x100;
priv->RfReg0Value[eRFPath] &= (~0x40); priv->RfReg0Value[eRFPath] &= (~0x40);
rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16)); rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset,
bMaskDWord,
(priv->RfReg0Value[eRFPath] << 16));
NewOffset = Offset - 15; NewOffset = Offset - 15;
} } else
else
NewOffset = Offset; NewOffset = Offset;
} } else {
else RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be"
{ " 8256\n");
RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
NewOffset = Offset; NewOffset = Offset;
} }
...@@ -197,14 +198,11 @@ void rtl8192_phy_RFSerialWrite(struct net_device* dev, enum rf90_radio_path eRFP ...@@ -197,14 +198,11 @@ void rtl8192_phy_RFSerialWrite(struct net_device* dev, enum rf90_radio_path eRFP
rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr); rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
if (Offset == 0x0)
if (Offset==0x0)
priv->RfReg0Value[eRFPath] = Data; priv->RfReg0Value[eRFPath] = Data;
if (priv->rf_chip == RF_8256) if (priv->rf_chip == RF_8256) {
{ if (Offset != 0) {
if (Offset != 0)
{
priv->RfReg0Value[eRFPath] &= 0xebf; priv->RfReg0Value[eRFPath] &= 0xebf;
rtl8192_setBBreg( rtl8192_setBBreg(
dev, dev,
...@@ -214,11 +212,11 @@ void rtl8192_phy_RFSerialWrite(struct net_device* dev, enum rf90_radio_path eRFP ...@@ -214,11 +212,11 @@ void rtl8192_phy_RFSerialWrite(struct net_device* dev, enum rf90_radio_path eRFP
} }
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);
} }
return; return;
} }
void rtl8192_phy_SetRFReg(struct net_device* dev, enum rf90_radio_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data) void rtl8192_phy_SetRFReg(struct net_device *dev, enum rf90_radio_path eRFPath,
u32 RegAddr, u32 BitMask, u32 Data)
{ {
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
u32 Original_Value, BitShift, New_Value; u32 Original_Value, BitShift, New_Value;
...@@ -229,36 +227,37 @@ void rtl8192_phy_SetRFReg(struct net_device* dev, enum rf90_radio_path eRFPath, ...@@ -229,36 +227,37 @@ void rtl8192_phy_SetRFReg(struct net_device* dev, enum rf90_radio_path eRFPath,
return; return;
RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n"); RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
if (priv->Rf_Mode == RF_OP_By_FW) if (priv->Rf_Mode == RF_OP_By_FW) {
{ if (BitMask != bMask12Bits) {
if (BitMask != bMask12Bits) Original_Value = phy_FwRFSerialRead(dev, eRFPath,
{ RegAddr);
Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
BitShift = rtl8192_CalculateBitShift(BitMask); BitShift = rtl8192_CalculateBitShift(BitMask);
New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); New_Value = (((Original_Value) & (~BitMask)) |
(Data << BitShift));
phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value); phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
}else } else
phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data); phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
udelay(200); udelay(200);
} } else {
else if (BitMask != bMask12Bits) {
{ Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath,
if (BitMask != bMask12Bits) RegAddr);
{
Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
BitShift = rtl8192_CalculateBitShift(BitMask); BitShift = rtl8192_CalculateBitShift(BitMask);
New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift)); New_Value = (((Original_Value) & (~BitMask)) |
(Data << BitShift));
rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value); rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr,
}else New_Value);
} else
rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data); rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
} }
return; return;
} }
u32 rtl8192_phy_QueryRFReg(struct net_device* dev, enum rf90_radio_path eRFPath, u32 RegAddr, u32 BitMask) u32 rtl8192_phy_QueryRFReg(struct net_device *dev, enum rf90_radio_path eRFPath,
u32 RegAddr, u32 BitMask)
{ {
u32 Original_Value, Readback_Value, BitShift; u32 Original_Value, Readback_Value, BitShift;
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
...@@ -267,79 +266,61 @@ u32 rtl8192_phy_QueryRFReg(struct net_device* dev, enum rf90_radio_path eRFPath, ...@@ -267,79 +266,61 @@ u32 rtl8192_phy_QueryRFReg(struct net_device* dev, enum rf90_radio_path eRFPath,
if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter) if (priv->rtllib->eRFPowerState != eRfOn && !priv->being_init_adapter)
return 0; return 0;
down(&priv->rf_sem); down(&priv->rf_sem);
if (priv->Rf_Mode == RF_OP_By_FW) if (priv->Rf_Mode == RF_OP_By_FW) {
{
Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr); Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
udelay(200); udelay(200);
} } else {
else Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath,
{ RegAddr);
Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
} }
BitShift = rtl8192_CalculateBitShift(BitMask); BitShift = rtl8192_CalculateBitShift(BitMask);
Readback_Value = (Original_Value & BitMask) >> BitShift; Readback_Value = (Original_Value & BitMask) >> BitShift;
up(&priv->rf_sem); up(&priv->rf_sem);
return (Readback_Value); return Readback_Value;
} }
static u32 phy_FwRFSerialRead( static u32 phy_FwRFSerialRead(struct net_device *dev,
struct net_device* dev, enum rf90_radio_path eRFPath, u32 Offset)
enum rf90_radio_path eRFPath,
u32 Offset )
{ {
u32 retValue = 0; u32 retValue = 0;
u32 Data = 0; u32 Data = 0;
u8 time = 0; u8 time = 0;
Data |= ((Offset&0xFF)<<12); Data |= ((Offset & 0xFF) << 12);
Data |= ((eRFPath&0x3)<<20); Data |= ((eRFPath & 0x3) << 20);
Data |= 0x80000000; Data |= 0x80000000;
while (read_nic_dword(dev, QPNR)&0x80000000) while (read_nic_dword(dev, QPNR)&0x80000000) {
{
if (time++ < 100) if (time++ < 100)
{
udelay(10); udelay(10);
}
else else
break; break;
} }
write_nic_dword(dev, QPNR, Data); write_nic_dword(dev, QPNR, Data);
while (read_nic_dword(dev, QPNR)&0x80000000) while (read_nic_dword(dev, QPNR) & 0x80000000) {
{
if (time++ < 100) if (time++ < 100)
{
udelay(10); udelay(10);
}
else else
return (0); return 0;
} }
retValue = read_nic_dword(dev, RF_DATA); retValue = read_nic_dword(dev, RF_DATA);
return (retValue); return retValue;
} /* phy_FwRFSerialRead */ } /* phy_FwRFSerialRead */
static void static void phy_FwRFSerialWrite(struct net_device *dev,
phy_FwRFSerialWrite( enum rf90_radio_path eRFPath,
struct net_device* dev, u32 Offset, u32 Data)
enum rf90_radio_path eRFPath,
u32 Offset,
u32 Data )
{ {
u8 time = 0; u8 time = 0;
Data |= ((Offset & 0xFF) << 12);
Data |= ((Offset&0xFF)<<12); Data |= ((eRFPath & 0x3) << 20);
Data |= ((eRFPath&0x3)<<20);
Data |= 0x400000; Data |= 0x400000;
Data |= 0x80000000; Data |= 0x80000000;
while (read_nic_dword(dev, QPNR)&0x80000000) while (read_nic_dword(dev, QPNR) & 0x80000000) {
{
if (time++ < 100) if (time++ < 100)
{
udelay(10); udelay(10);
}
else else
break; break;
} }
...@@ -348,82 +329,81 @@ phy_FwRFSerialWrite( ...@@ -348,82 +329,81 @@ phy_FwRFSerialWrite(
} /* phy_FwRFSerialWrite */ } /* phy_FwRFSerialWrite */
void rtl8192_phy_configmac(struct net_device* dev) void rtl8192_phy_configmac(struct net_device *dev)
{ {
u32 dwArrayLen = 0, i = 0; u32 dwArrayLen = 0, i = 0;
u32* pdwArray = NULL; u32 *pdwArray = NULL;
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
if (priv->bTXPowerDataReadFromEEPORM)
{ if (priv->bTXPowerDataReadFromEEPORM) {
RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n"); RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
dwArrayLen = MACPHY_Array_PGLength; dwArrayLen = MACPHY_Array_PGLength;
pdwArray = Rtl819XMACPHY_Array_PG; pdwArray = Rtl819XMACPHY_Array_PG;
} } else {
else RT_TRACE(COMP_PHY, "Read rtl819XMACPHY_Array\n");
{
RT_TRACE(COMP_PHY,"Read rtl819XMACPHY_Array\n");
dwArrayLen = MACPHY_ArrayLength; dwArrayLen = MACPHY_ArrayLength;
pdwArray = Rtl819XMACPHY_Array; pdwArray = Rtl819XMACPHY_Array;
} }
for (i = 0; i<dwArrayLen; i=i+3){ for (i = 0; i < dwArrayLen; i += 3) {
RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n", RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MAC"
pdwArray[i], pdwArray[i+1], pdwArray[i+2]); "PHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
if (pdwArray[i] == 0x318) if (pdwArray[i] == 0x318)
{
pdwArray[i+2] = 0x00000800; pdwArray[i+2] = 0x00000800;
} rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1],
rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]); pdwArray[i+2]);
} }
return; return;
} }
void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType) void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
{ {
int i; int i;
u32* Rtl819XPHY_REGArray_Table = NULL; u32 *Rtl819XPHY_REGArray_Table = NULL;
u32* Rtl819XAGCTAB_Array_Table = NULL; u32 *Rtl819XAGCTAB_Array_Table = NULL;
u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0; u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
{
AGCTAB_ArrayLen = AGCTAB_ArrayLength; AGCTAB_ArrayLen = AGCTAB_ArrayLength;
Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array; Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
if (priv->rf_type == RF_2T4R) if (priv->rf_type == RF_2T4R) {
{ PHY_REGArrayLen = PHY_REGArrayLength;
PHY_REGArrayLen = PHY_REGArrayLength; Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray; } else if (priv->rf_type == RF_1T2R) {
} PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
else if (priv->rf_type == RF_1T2R) Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
{
PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
}
} }
if (ConfigType == BaseBand_Config_PHY_REG) if (ConfigType == BaseBand_Config_PHY_REG) {
{ for (i = 0; i < PHY_REGArrayLen; i += 2) {
for (i=0; i<PHY_REGArrayLen; i+=2) rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i],
{ bMaskDWord,
rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]); Rtl819XPHY_REGArray_Table[i+1]);
RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]); RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray"
"[0] is %x Rtl819xUsbPHY_REGArray[1] is %x\n",
i, Rtl819XPHY_REGArray_Table[i],
Rtl819XPHY_REGArray_Table[i+1]);
} }
} } else if (ConfigType == BaseBand_Config_AGC_TAB) {
else if (ConfigType == BaseBand_Config_AGC_TAB) for (i = 0; i < AGCTAB_ArrayLen; i += 2) {
{ rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i],
for (i=0; i<AGCTAB_ArrayLen; i+=2) bMaskDWord,
{ Rtl819XAGCTAB_Array_Table[i+1]);
rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]); RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] "
RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]); "is %x rtl819XAGCTAB_Array[1] is %x\n", i,
Rtl819XAGCTAB_Array_Table[i],
Rtl819XAGCTAB_Array_Table[i+1]);
} }
} }
return; return;
} }
void rtl8192_InitBBRFRegDef(struct net_device* dev)
void rtl8192_InitBBRFRegDef(struct net_device *dev)
{ {
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW; priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
...@@ -510,37 +490,45 @@ void rtl8192_InitBBRFRegDef(struct net_device* dev) ...@@ -510,37 +490,45 @@ void rtl8192_InitBBRFRegDef(struct net_device* dev)
priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack; priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
} }
bool rtl8192_phy_checkBBAndRF(struct net_device* dev, enum hw90_block CheckBlock, enum rf90_radio_path eRFPath)
bool rtl8192_phy_checkBBAndRF(struct net_device *dev,
enum hw90_block CheckBlock,
enum rf90_radio_path eRFPath)
{ {
bool ret = true; bool ret = true;
u32 i, CheckTimes = 4, dwRegRead = 0; u32 i, CheckTimes = 4, dwRegRead = 0;
u32 WriteAddr[4]; u32 WriteAddr[4];
u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f}; u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
WriteAddr[HW90_BLOCK_MAC] = 0x100; WriteAddr[HW90_BLOCK_MAC] = 0x100;
WriteAddr[HW90_BLOCK_PHY0] = 0x900; WriteAddr[HW90_BLOCK_PHY0] = 0x900;
WriteAddr[HW90_BLOCK_PHY1] = 0x800; WriteAddr[HW90_BLOCK_PHY1] = 0x800;
WriteAddr[HW90_BLOCK_RF] = 0x3; WriteAddr[HW90_BLOCK_RF] = 0x3;
RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__, CheckBlock); RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __func__,
for (i=0 ; i < CheckTimes ; i++) CheckBlock);
{ for (i = 0; i < CheckTimes; i++) {
switch (CheckBlock) {
switch (CheckBlock)
{
case HW90_BLOCK_MAC: case HW90_BLOCK_MAC:
RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!"); RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write "
"0x100 here!");
break; break;
case HW90_BLOCK_PHY0: case HW90_BLOCK_PHY0:
case HW90_BLOCK_PHY1: case HW90_BLOCK_PHY1:
write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]); write_nic_dword(dev, WriteAddr[CheckBlock],
WriteData[i]);
dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]); dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
break; break;
case HW90_BLOCK_RF: case HW90_BLOCK_RF:
WriteData[i] &= 0xfff; WriteData[i] &= 0xfff;
rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]); rtl8192_phy_SetRFReg(dev, eRFPath,
WriteAddr[HW90_BLOCK_RF],
bMask12Bits, WriteData[i]);
mdelay(10); mdelay(10);
dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord); dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath,
WriteAddr[HW90_BLOCK_RF],
bMaskDWord);
mdelay(10); mdelay(10);
break; break;
...@@ -550,9 +538,9 @@ bool rtl8192_phy_checkBBAndRF(struct net_device* dev, enum hw90_block CheckBlock ...@@ -550,9 +538,9 @@ bool rtl8192_phy_checkBBAndRF(struct net_device* dev, enum hw90_block CheckBlock
} }
if (dwRegRead != WriteData[i]) if (dwRegRead != WriteData[i]) {
{ RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, "
RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]); "WriteData: %x\n", dwRegRead, WriteData[i]);
ret = false; ret = false;
break; break;
} }
...@@ -561,27 +549,27 @@ bool rtl8192_phy_checkBBAndRF(struct net_device* dev, enum hw90_block CheckBlock ...@@ -561,27 +549,27 @@ bool rtl8192_phy_checkBBAndRF(struct net_device* dev, enum hw90_block CheckBlock
return ret; return ret;
} }
bool rtl8192_BB_Config_ParaFile(struct net_device* dev) bool rtl8192_BB_Config_ParaFile(struct net_device *dev)
{ {
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
bool rtStatus = true; bool rtStatus = true;
u8 bRegValue = 0, eCheckItem = 0; u8 bRegValue = 0, eCheckItem = 0;
u32 dwRegValue = 0; u32 dwRegValue = 0;
/**************************************
**************************************/
bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET); bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET);
write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT)); write_nic_byte(dev, BB_GLOBAL_RESET, (bRegValue|BB_GLOBAL_RESET_BIT));
dwRegValue = read_nic_dword(dev, CPU_GEN); dwRegValue = read_nic_dword(dev, CPU_GEN);
write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST))); write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
for (eCheckItem=(enum hw90_block)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++) for (eCheckItem = (enum hw90_block)HW90_BLOCK_PHY0;
{ eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
rtStatus = rtl8192_phy_checkBBAndRF(dev, (enum hw90_block)eCheckItem, (enum rf90_radio_path)0); rtStatus = rtl8192_phy_checkBBAndRF(dev,
if (rtStatus != true) (enum hw90_block)eCheckItem,
{ (enum rf90_radio_path)0);
RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1); if (rtStatus != true) {
RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():"
"Check PHY%d Fail!!\n", eCheckItem-1);
return rtStatus; return rtStatus;
} }
} }
...@@ -593,14 +581,11 @@ bool rtl8192_BB_Config_ParaFile(struct net_device* dev) ...@@ -593,14 +581,11 @@ bool rtl8192_BB_Config_ParaFile(struct net_device* dev)
rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB); rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
if (priv->IC_Cut > VERSION_8190_BD) if (priv->IC_Cut > VERSION_8190_BD) {
{
if (priv->rf_type == RF_2T4R) if (priv->rf_type == RF_2T4R)
{ dwRegValue = (priv->AntennaTxPwDiff[2]<<8 |
dwRegValue = ( priv->AntennaTxPwDiff[2]<<8 | priv->AntennaTxPwDiff[1]<<4 |
priv->AntennaTxPwDiff[1]<<4 | priv->AntennaTxPwDiff[0]);
priv->AntennaTxPwDiff[0]);
}
else else
dwRegValue = 0x0; dwRegValue = 0x0;
rtl8192_setBBreg(dev, rFPGA0_TxGainStage, rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
...@@ -608,22 +593,25 @@ bool rtl8192_BB_Config_ParaFile(struct net_device* dev) ...@@ -608,22 +593,25 @@ bool rtl8192_BB_Config_ParaFile(struct net_device* dev)
dwRegValue = priv->CrystalCap; dwRegValue = priv->CrystalCap;
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue); rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x,
dwRegValue);
} }
return rtStatus; return rtStatus;
} }
bool rtl8192_BBConfig(struct net_device* dev) bool rtl8192_BBConfig(struct net_device *dev)
{ {
bool rtStatus = true; bool rtStatus = true;
rtl8192_InitBBRFRegDef(dev); rtl8192_InitBBRFRegDef(dev);
rtStatus = rtl8192_BB_Config_ParaFile(dev); rtStatus = rtl8192_BB_Config_ParaFile(dev);
return rtStatus; return rtStatus;
} }
void rtl8192_phy_getTxPower(struct net_device* dev) void rtl8192_phy_getTxPower(struct net_device *dev)
{ {
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
priv->MCSTxPowerLevelOriginalOffset[0] = priv->MCSTxPowerLevelOriginalOffset[0] =
read_nic_dword(dev, rTxAGC_Rate18_06); read_nic_dword(dev, rTxAGC_Rate18_06);
priv->MCSTxPowerLevelOriginalOffset[1] = priv->MCSTxPowerLevelOriginalOffset[1] =
...@@ -641,44 +629,39 @@ void rtl8192_phy_getTxPower(struct net_device* dev) ...@@ -641,44 +629,39 @@ void rtl8192_phy_getTxPower(struct net_device* dev)
priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1); priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1); priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1);
priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1); priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n", RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, "
"c60=0x%x, c68=0x%x)\n",
priv->DefaultInitialGain[0], priv->DefaultInitialGain[1], priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]); priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3); priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3);
priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2); priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2);
RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n", RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x\n",
rOFDM0_RxDetector3, priv->framesync); rOFDM0_RxDetector3, priv->framesync);
priv->SifsTime = read_nic_word(dev, SIFS); priv->SifsTime = read_nic_word(dev, SIFS);
return; return;
} }
void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel) void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
{ {
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
u8 powerlevel = 0,powerlevelOFDM24G = 0; u8 powerlevel = 0, powerlevelOFDM24G = 0;
char ant_pwr_diff; char ant_pwr_diff;
u32 u4RegValue; u32 u4RegValue;
if (priv->epromtype == EEPROM_93C46) if (priv->epromtype == EEPROM_93C46) {
{
powerlevel = priv->TxPowerLevelCCK[channel-1]; powerlevel = priv->TxPowerLevelCCK[channel-1];
powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
} } else if (priv->epromtype == EEPROM_93C56) {
else if (priv->epromtype == EEPROM_93C56) if (priv->rf_type == RF_1T2R) {
{
if (priv->rf_type == RF_1T2R)
{
powerlevel = priv->TxPowerLevelCCK_C[channel-1]; powerlevel = priv->TxPowerLevelCCK_C[channel-1];
powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1]; powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
} } else if (priv->rf_type == RF_2T4R) {
else if (priv->rf_type == RF_2T4R)
{
powerlevel = priv->TxPowerLevelCCK_A[channel-1]; powerlevel = priv->TxPowerLevelCCK_A[channel-1];
powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1]; powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1] ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
-priv->TxPowerLevelOFDM24G_A[channel-1]; - priv->TxPowerLevelOFDM24G_A[channel-1];
priv->RF_C_TxPwDiff = ant_pwr_diff; priv->RF_C_TxPwDiff = ant_pwr_diff;
...@@ -688,9 +671,9 @@ void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel) ...@@ -688,9 +671,9 @@ void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff); priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);
priv->AntennaTxPwDiff[0] = 0; priv->AntennaTxPwDiff[0] = 0;
u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 | u4RegValue = (priv->AntennaTxPwDiff[2]<<8 |
priv->AntennaTxPwDiff[1]<<4 | priv->AntennaTxPwDiff[1]<<4 |
priv->AntennaTxPwDiff[0]); priv->AntennaTxPwDiff[0]);
rtl8192_setBBreg(dev, rFPGA0_TxGainStage, rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
(bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue); (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
...@@ -706,97 +689,105 @@ void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel) ...@@ -706,97 +689,105 @@ void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
case RF_8258: case RF_8258:
break; break;
default: default:
RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n", __func__); RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n",
__func__);
break; break;
} }
return; return;
} }
bool rtl8192_phy_RFConfig(struct net_device* dev) bool rtl8192_phy_RFConfig(struct net_device *dev)
{ {
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
bool rtStatus = true; bool rtStatus = true;
switch (priv->rf_chip) switch (priv->rf_chip) {
{ case RF_8225:
case RF_8225: break;
break; case RF_8256:
case RF_8256: rtStatus = PHY_RF8256_Config(dev);
rtStatus = PHY_RF8256_Config(dev); break;
break;
case RF_8258: case RF_8258:
break; break;
case RF_PSEUDO_11N: case RF_PSEUDO_11N:
break; break;
default: default:
RT_TRACE(COMP_ERR, "error chip id\n"); RT_TRACE(COMP_ERR, "error chip id\n");
break; break;
} }
return rtStatus; return rtStatus;
} }
void rtl8192_phy_updateInitGain(struct net_device* dev) void rtl8192_phy_updateInitGain(struct net_device *dev)
{ {
return; return;
} }
u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, enum rf90_radio_path eRFPath) u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
enum rf90_radio_path eRFPath)
{ {
int i; int i;
u8 ret = 0; u8 ret = 0;
switch (eRFPath){ switch (eRFPath) {
case RF90_PATH_A: case RF90_PATH_A:
for (i = 0;i<RadioA_ArrayLength; i=i+2){ for (i = 0; i < RadioA_ArrayLength; i += 2) {
if (Rtl819XRadioA_Array[i] == 0xfe) {
if (Rtl819XRadioA_Array[i] == 0xfe){ msleep(100);
msleep(100); continue;
continue;
}
rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array[i], bMask12Bits, Rtl819XRadioA_Array[i+1]);
} }
break; rtl8192_phy_SetRFReg(dev, eRFPath,
case RF90_PATH_B: Rtl819XRadioA_Array[i],
for (i = 0;i<RadioB_ArrayLength; i=i+2){ bMask12Bits,
Rtl819XRadioA_Array[i+1]);
if (Rtl819XRadioB_Array[i] == 0xfe){
msleep(100);
continue;
}
rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array[i], bMask12Bits, Rtl819XRadioB_Array[i+1]);
}
break;
case RF90_PATH_B:
for (i = 0; i < RadioB_ArrayLength; i += 2) {
if (Rtl819XRadioB_Array[i] == 0xfe) {
msleep(100);
continue;
} }
break; rtl8192_phy_SetRFReg(dev, eRFPath,
case RF90_PATH_C: Rtl819XRadioB_Array[i],
for (i = 0;i<RadioC_ArrayLength; i=i+2){ bMask12Bits,
Rtl819XRadioB_Array[i+1]);
if (Rtl819XRadioC_Array[i] == 0xfe){
msleep(100);
continue;
}
rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioC_Array[i], bMask12Bits, Rtl819XRadioC_Array[i+1]);
}
break;
case RF90_PATH_C:
for (i = 0; i < RadioC_ArrayLength; i += 2) {
if (Rtl819XRadioC_Array[i] == 0xfe) {
msleep(100);
continue;
} }
break; rtl8192_phy_SetRFReg(dev, eRFPath,
case RF90_PATH_D: Rtl819XRadioC_Array[i],
for (i = 0;i<RadioD_ArrayLength; i=i+2){ bMask12Bits,
Rtl819XRadioC_Array[i+1]);
if (Rtl819XRadioD_Array[i] == 0xfe){
msleep(100);
continue;
}
rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioD_Array[i], bMask12Bits, Rtl819XRadioD_Array[i+1]);
}
break;
case RF90_PATH_D:
for (i = 0; i < RadioD_ArrayLength; i += 2) {
if (Rtl819XRadioD_Array[i] == 0xfe) {
msleep(100);
continue;
} }
break; rtl8192_phy_SetRFReg(dev, eRFPath,
default: Rtl819XRadioD_Array[i], bMask12Bits,
break; Rtl819XRadioD_Array[i+1]);
}
break;
default:
break;
} }
return ret;; return ret;
} }
void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
...@@ -805,8 +796,7 @@ void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) ...@@ -805,8 +796,7 @@ void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
u8 powerlevel = priv->TxPowerLevelCCK[channel-1]; u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1]; u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
switch (priv->rf_chip) switch (priv->rf_chip) {
{
case RF_8225: case RF_8225:
break; break;
...@@ -818,31 +808,28 @@ void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel) ...@@ -818,31 +808,28 @@ void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
case RF_8258: case RF_8258:
break; break;
default: default:
RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n"); RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPower"
"Level()\n");
break; break;
} }
return; return;
} }
u8 rtl8192_phy_SetSwChnlCmdArray(
struct sw_chnl_cmd* CmdTable, u8 rtl8192_phy_SetSwChnlCmdArray(struct sw_chnl_cmd *CmdTable, u32 CmdTableIdx,
u32 CmdTableIdx, u32 CmdTableSz, enum sw_chnl_cmd_id CmdID,
u32 CmdTableSz, u32 Para1, u32 Para2, u32 msDelay)
enum sw_chnl_cmd_id CmdID,
u32 Para1,
u32 Para2,
u32 msDelay
)
{ {
struct sw_chnl_cmd* pCmd; struct sw_chnl_cmd *pCmd;
if (CmdTable == NULL) if (CmdTable == NULL) {
{ RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot "
RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"); "be NULL.\n");
return false; return false;
} }
if (CmdTableIdx >= CmdTableSz) if (CmdTableIdx >= CmdTableSz) {
{ RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid"
RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n", " index, please check size of the table, CmdTableIdx:"
"%d, CmdTableSz:%d\n",
CmdTableIdx, CmdTableSz); CmdTableIdx, CmdTableSz);
return false; return false;
} }
...@@ -855,7 +842,9 @@ u8 rtl8192_phy_SetSwChnlCmdArray( ...@@ -855,7 +842,9 @@ u8 rtl8192_phy_SetSwChnlCmdArray(
return true; return true;
} }
u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay)
u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage,
u8 *step, u32 *delay)
{ {
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
struct sw_chnl_cmd PreCommonCmd[MAX_PRECMD_CNT]; struct sw_chnl_cmd PreCommonCmd[MAX_PRECMD_CNT];
...@@ -867,50 +856,58 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u ...@@ -867,50 +856,58 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u
struct sw_chnl_cmd *CurrentCmd = NULL; struct sw_chnl_cmd *CurrentCmd = NULL;
u8 eRFPath; u8 eRFPath;
RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", __func__, *stage, *step, channel); RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n",
__func__, *stage, *step, channel);
if (!IsLegalChannel(priv->rtllib, channel)) if (!IsLegalChannel(priv->rtllib, channel)) {
{ RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n",
RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel); channel);
return true; return true;
} }
{ {
PreCommonCmdCnt = 0; PreCommonCmdCnt = 0;
rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
CmdID_SetTxPowerLevel, 0, 0, 0); MAX_PRECMD_CNT, CmdID_SetTxPowerLevel,
rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT, 0, 0, 0);
CmdID_End, 0, 0, 0); rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++,
MAX_PRECMD_CNT, CmdID_End, 0, 0, 0);
PostCommonCmdCnt = 0; PostCommonCmdCnt = 0;
rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT, rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++,
CmdID_End, 0, 0, 0); MAX_POSTCMD_CNT, CmdID_End, 0, 0, 0);
RfDependCmdCnt = 0; RfDependCmdCnt = 0;
switch ( priv->rf_chip ) switch (priv->rf_chip) {
{
case RF_8225: case RF_8225:
if (!(channel >= 1 && channel <= 14)) if (!(channel >= 1 && channel <= 14)) {
{ RT_TRACE(COMP_ERR, "illegal channel for Zebra "
RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel); "8225: %d\n", channel);
return false; return false;
} }
rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, rtl8192_phy_SetSwChnlCmdArray(RfDependCmd,
CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10); RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, CmdID_RF_WriteReg, rZebra1_Channel,
RF_CHANNEL_TABLE_ZEBRA[channel], 10);
rtl8192_phy_SetSwChnlCmdArray(RfDependCmd,
RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
CmdID_End, 0, 0, 0); CmdID_End, 0, 0, 0);
break; break;
case RF_8256: case RF_8256:
if (!(channel >= 1 && channel <= 14)) if (!(channel >= 1 && channel <= 14)) {
{ RT_TRACE(COMP_ERR, "illegal channel for Zebra"
RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel); " 8256: %d\n", channel);
return false; return false;
} }
rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, rtl8192_phy_SetSwChnlCmdArray(RfDependCmd,
CmdID_RF_WriteReg, rZebra1_Channel, channel, 10); RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT, CmdID_RF_WriteReg, rZebra1_Channel, channel,
10);
rtl8192_phy_SetSwChnlCmdArray(RfDependCmd,
RfDependCmdCnt++,
MAX_RFDEPENDCMD_CNT,
CmdID_End, 0, 0, 0); CmdID_End, 0, 0, 0);
break; break;
...@@ -918,68 +915,70 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u ...@@ -918,68 +915,70 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u
break; break;
default: default:
RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n",
priv->rf_chip);
return false; return false;
break; break;
} }
do{ do {
switch (*stage) switch (*stage) {
{
case 0: case 0:
CurrentCmd=&PreCommonCmd[*step]; CurrentCmd = &PreCommonCmd[*step];
break; break;
case 1: case 1:
CurrentCmd=&RfDependCmd[*step]; CurrentCmd = &RfDependCmd[*step];
break; break;
case 2: case 2:
CurrentCmd=&PostCommonCmd[*step]; CurrentCmd = &PostCommonCmd[*step];
break; break;
} }
if (CurrentCmd->CmdID==CmdID_End) if (CurrentCmd->CmdID == CmdID_End) {
{ if ((*stage) == 2) {
if ((*stage)==2)
{
return true; return true;
} } else {
else
{
(*stage)++; (*stage)++;
(*step)=0; (*step) = 0;
continue; continue;
} }
} }
switch (CurrentCmd->CmdID) switch (CurrentCmd->CmdID) {
{
case CmdID_SetTxPowerLevel: case CmdID_SetTxPowerLevel:
if (priv->IC_Cut > (u8)VERSION_8190_BD) if (priv->IC_Cut > (u8)VERSION_8190_BD)
rtl8192_SetTxPowerLevel(dev,channel); rtl8192_SetTxPowerLevel(dev, channel);
break; break;
case CmdID_WritePortUlong: case CmdID_WritePortUlong:
write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2); write_nic_dword(dev, CurrentCmd->Para1,
CurrentCmd->Para2);
break; break;
case CmdID_WritePortUshort: case CmdID_WritePortUshort:
write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2); write_nic_word(dev, CurrentCmd->Para1,
(u16)CurrentCmd->Para2);
break; break;
case CmdID_WritePortUchar: case CmdID_WritePortUchar:
write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2); write_nic_byte(dev, CurrentCmd->Para1,
(u8)CurrentCmd->Para2);
break; break;
case CmdID_RF_WriteReg: case CmdID_RF_WriteReg:
for (eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++) for (eRFPath = 0; eRFPath <
rtl8192_phy_SetRFReg(dev, (enum rf90_radio_path)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7); priv->NumTotalRFPath; eRFPath++)
rtl8192_phy_SetRFReg(dev,
(enum rf90_radio_path)eRFPath,
CurrentCmd->Para1, bMask12Bits,
CurrentCmd->Para2<<7);
break; break;
default: default:
break; break;
} }
break; break;
}while(true); } while (true);
}/*for (Number of RF paths)*/ } /*for (Number of RF paths)*/
(*delay)=CurrentCmd->msDelay; (*delay) = CurrentCmd->msDelay;
(*step)++; (*step)++;
return false; return false;
} }
...@@ -987,14 +986,14 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u ...@@ -987,14 +986,14 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u
void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel) void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
{ {
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
u32 delay = 0; u32 delay = 0;
while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay)) while (!rtl8192_phy_SwChnlStepByStep(dev, channel, &priv->SwChnlStage,
{ &priv->SwChnlStep, &delay)) {
if (delay>0) if (delay > 0)
msleep(delay); msleep(delay);
if (IS_NIC_DOWN(priv)) if (IS_NIC_DOWN(priv))
break; break;
} }
} }
void rtl8192_SwChnl_WorkItem(struct net_device *dev) void rtl8192_SwChnl_WorkItem(struct net_device *dev)
...@@ -1004,44 +1003,43 @@ void rtl8192_SwChnl_WorkItem(struct net_device *dev) ...@@ -1004,44 +1003,43 @@ void rtl8192_SwChnl_WorkItem(struct net_device *dev)
RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n"); RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__, priv->chan, priv); RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __func__,
priv->chan, priv);
rtl8192_phy_FinishSwChnlNow(dev , priv->chan); rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n"); RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
} }
u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel) u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
{ {
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
RT_TRACE(COMP_PHY, "=====>%s()\n", __func__); RT_TRACE(COMP_PHY, "=====>%s()\n", __func__);
if (IS_NIC_DOWN(priv)) if (IS_NIC_DOWN(priv)) {
{ RT_TRACE(COMP_ERR, "%s(): ERR !! driver is not up\n", __func__);
RT_TRACE(COMP_ERR, "%s(): ERR !! driver is not up\n",__func__);
return false; return false;
} }
if (priv->SwChnlInProgress) if (priv->SwChnlInProgress)
return false; return false;
switch (priv->rtllib->mode) switch (priv->rtllib->mode) {
{
case WIRELESS_MODE_A: case WIRELESS_MODE_A:
case WIRELESS_MODE_N_5G: case WIRELESS_MODE_N_5G:
if (channel<=14){ if (channel <= 14) {
RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14"); RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
return false; return false;
} }
break; break;
case WIRELESS_MODE_B: case WIRELESS_MODE_B:
if (channel>14){ if (channel > 14) {
RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14"); RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
return false; return false;
} }
break; break;
case WIRELESS_MODE_G: case WIRELESS_MODE_G:
case WIRELESS_MODE_N_24G: case WIRELESS_MODE_N_24G:
if (channel>14){ if (channel > 14) {
RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14"); RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
return false; return false;
} }
...@@ -1052,71 +1050,77 @@ u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel) ...@@ -1052,71 +1050,77 @@ u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
if (channel == 0) if (channel == 0)
channel = 1; channel = 1;
priv->chan=channel; priv->chan = channel;
priv->SwChnlStage=0; priv->SwChnlStage = 0;
priv->SwChnlStep=0; priv->SwChnlStep = 0;
if (!IS_NIC_DOWN(priv)){ if (!IS_NIC_DOWN(priv))
rtl8192_SwChnl_WorkItem(dev); rtl8192_SwChnl_WorkItem(dev);
}
priv->SwChnlInProgress = false; priv->SwChnlInProgress = false;
return true; return true;
} }
static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev ) static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev)
{ {
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
switch (priv->CurrentChannelBW) switch (priv->CurrentChannelBW) {
{ case HT_CHANNEL_WIDTH_20:
case HT_CHANNEL_WIDTH_20: priv->CCKPresentAttentuation =
priv->CCKPresentAttentuation = priv->CCKPresentAttentuation_20Mdefault +
priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference; priv->CCKPresentAttentuation_difference;
if (priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
if (priv->CCKPresentAttentuation < 0)
priv->CCKPresentAttentuation = 0;
RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
if (priv->rtllib->current_network.channel== 14 && !priv->bcck_in_ch14) if (priv->CCKPresentAttentuation >
{ (CCKTxBBGainTableLength-1))
priv->bcck_in_ch14 = true; priv->CCKPresentAttentuation =
dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); CCKTxBBGainTableLength-1;
} if (priv->CCKPresentAttentuation < 0)
else if (priv->rtllib->current_network.channel != 14 && priv->bcck_in_ch14) priv->CCKPresentAttentuation = 0;
{
priv->bcck_in_ch14 = false; RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresent"
dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); "Attentuation = %d\n",
} priv->CCKPresentAttentuation);
else
dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); if (priv->rtllib->current_network.channel == 14 &&
!priv->bcck_in_ch14) {
priv->bcck_in_ch14 = true;
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
} else if (priv->rtllib->current_network.channel !=
14 && priv->bcck_in_ch14) {
priv->bcck_in_ch14 = false;
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
} else {
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
}
break; break;
case HT_CHANNEL_WIDTH_20_40: case HT_CHANNEL_WIDTH_20_40:
priv->CCKPresentAttentuation =
priv->CCKPresentAttentuation_40Mdefault +
priv->CCKPresentAttentuation_difference;
RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresent"
"Attentuation = %d\n",
priv->CCKPresentAttentuation);
if (priv->CCKPresentAttentuation >
(CCKTxBBGainTableLength - 1))
priv->CCKPresentAttentuation = priv->CCKPresentAttentuation =
priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference; CCKTxBBGainTableLength-1;
if (priv->CCKPresentAttentuation < 0)
RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation); priv->CCKPresentAttentuation = 0;
if (priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1; if (priv->rtllib->current_network.channel == 14 &&
if (priv->CCKPresentAttentuation < 0) !priv->bcck_in_ch14) {
priv->CCKPresentAttentuation = 0; priv->bcck_in_ch14 = true;
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
if (priv->rtllib->current_network.channel == 14 && !priv->bcck_in_ch14) } else if (priv->rtllib->current_network.channel != 14
{ && priv->bcck_in_ch14) {
priv->bcck_in_ch14 = true; priv->bcck_in_ch14 = false;
dm_cck_txpower_adjust(dev,priv->bcck_in_ch14); dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
} } else {
else if (priv->rtllib->current_network.channel != 14 && priv->bcck_in_ch14) dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
{ }
priv->bcck_in_ch14 = false;
dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
}
else
dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
break; break;
} }
} }
...@@ -1125,24 +1129,29 @@ static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev) ...@@ -1125,24 +1129,29 @@ static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
{ {
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
if (priv->rtllib->current_network.channel == 14 && !priv->bcck_in_ch14) if (priv->rtllib->current_network.channel == 14 &&
!priv->bcck_in_ch14)
priv->bcck_in_ch14 = true; priv->bcck_in_ch14 = true;
else if (priv->rtllib->current_network.channel != 14 && priv->bcck_in_ch14) else if (priv->rtllib->current_network.channel != 14 &&
priv->bcck_in_ch14)
priv->bcck_in_ch14 = false; priv->bcck_in_ch14 = false;
switch (priv->CurrentChannelBW) switch (priv->CurrentChannelBW) {
{ case HT_CHANNEL_WIDTH_20:
case HT_CHANNEL_WIDTH_20: if (priv->Record_CCK_20Mindex == 0)
if (priv->Record_CCK_20Mindex == 0) priv->Record_CCK_20Mindex = 6;
priv->Record_CCK_20Mindex = 6; priv->CCK_index = priv->Record_CCK_20Mindex;
priv->CCK_index = priv->Record_CCK_20Mindex; RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_"
RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n", priv->CCK_index); "Switch_ThermalMeter(),CCK_index = %d\n",
break; priv->CCK_index);
break;
case HT_CHANNEL_WIDTH_20_40:
priv->CCK_index = priv->Record_CCK_40Mindex; case HT_CHANNEL_WIDTH_20_40:
RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n", priv->CCK_index); priv->CCK_index = priv->Record_CCK_40Mindex;
break; RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_"
"Switch_ThermalMeter(), CCK_index = %d\n",
priv->CCK_index);
break;
} }
dm_cck_txpower_adjust(dev, priv->bcck_in_ch14); dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
} }
...@@ -1163,108 +1172,107 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev) ...@@ -1163,108 +1172,107 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
u8 regBwOpMode; u8 regBwOpMode;
RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n", \ RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s "
priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz") "bandwidth\n", priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20 ?
"20MHz" : "40MHz")
if (priv->rf_chip== RF_PSEUDO_11N) if (priv->rf_chip == RF_PSEUDO_11N) {
{ priv->SetBWModeInProgress = false;
priv->SetBWModeInProgress= false;
return; return;
} }
if (IS_NIC_DOWN(priv)){ if (IS_NIC_DOWN(priv)) {
RT_TRACE(COMP_ERR,"%s(): ERR!! driver is not up\n",__func__); RT_TRACE(COMP_ERR, "%s(): ERR!! driver is not up\n", __func__);
return; return;
} }
regBwOpMode = read_nic_byte(dev, BW_OPMODE); regBwOpMode = read_nic_byte(dev, BW_OPMODE);
switch (priv->CurrentChannelBW) switch (priv->CurrentChannelBW) {
{ case HT_CHANNEL_WIDTH_20:
case HT_CHANNEL_WIDTH_20: regBwOpMode |= BW_OPMODE_20MHZ;
regBwOpMode |= BW_OPMODE_20MHZ; write_nic_byte(dev, BW_OPMODE, regBwOpMode);
write_nic_byte(dev, BW_OPMODE, regBwOpMode); break;
break;
case HT_CHANNEL_WIDTH_20_40: case HT_CHANNEL_WIDTH_20_40:
regBwOpMode &= ~BW_OPMODE_20MHZ; regBwOpMode &= ~BW_OPMODE_20MHZ;
write_nic_byte(dev, BW_OPMODE, regBwOpMode); write_nic_byte(dev, BW_OPMODE, regBwOpMode);
break; break;
default: default:
RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW); RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown "
break; "Bandwidth: %#X\n", priv->CurrentChannelBW);
break;
} }
switch (priv->CurrentChannelBW) switch (priv->CurrentChannelBW) {
{ case HT_CHANNEL_WIDTH_20:
case HT_CHANNEL_WIDTH_20: rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
if (!priv->btxpower_tracking) {
if (!priv->btxpower_tracking) write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
{ write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000); write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317); } else {
write_nic_dword(dev, rCCK0_DebugPort, 0x00000204); CCK_Tx_Power_Track_BW_Switch(dev);
} }
else
CCK_Tx_Power_Track_BW_Switch(dev);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
break; rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
case HT_CHANNEL_WIDTH_20_40:
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
if (!priv->btxpower_tracking)
{
write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
}
else
CCK_Tx_Power_Track_BW_Switch(dev);
rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1)); break;
rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC); case HT_CHANNEL_WIDTH_20_40:
rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
if (!priv->btxpower_tracking) {
write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
} else {
CCK_Tx_Power_Track_BW_Switch(dev);
}
rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand,
(priv->nCur40MhzPrimeSC>>1));
rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00,
priv->nCur40MhzPrimeSC);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0); rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
break; break;
default: default:
RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW); RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown "
break; "Bandwidth: %#X\n", priv->CurrentChannelBW);
break;
} }
switch ( priv->rf_chip ) switch (priv->rf_chip) {
{ case RF_8225:
case RF_8225: break;
break;
case RF_8256: case RF_8256:
PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW); PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
break; break;
case RF_8258: case RF_8258:
break; break;
case RF_PSEUDO_11N: case RF_PSEUDO_11N:
break; break;
default: default:
RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip); RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
break; break;
} }
atomic_dec(&(priv->rtllib->atm_swbw)); atomic_dec(&(priv->rtllib->atm_swbw));
priv->SetBWModeInProgress= false; priv->SetBWModeInProgress = false;
RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()"); RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
} }
void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth, enum ht_extchnl_offset Offset) void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth,
enum ht_extchnl_offset Offset)
{ {
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
...@@ -1272,14 +1280,14 @@ void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth, ...@@ -1272,14 +1280,14 @@ void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth,
if (priv->SetBWModeInProgress) if (priv->SetBWModeInProgress)
return; return;
atomic_inc(&(priv->rtllib->atm_swbw)); atomic_inc(&(priv->rtllib->atm_swbw));
priv->SetBWModeInProgress= true; priv->SetBWModeInProgress = true;
priv->CurrentChannelBW = Bandwidth; priv->CurrentChannelBW = Bandwidth;
if (Offset==HT_EXTCHNL_OFFSET_LOWER) if (Offset == HT_EXTCHNL_OFFSET_LOWER)
priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER; priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
else if (Offset==HT_EXTCHNL_OFFSET_UPPER) else if (Offset == HT_EXTCHNL_OFFSET_UPPER)
priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER; priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
else else
priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE; priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
...@@ -1288,79 +1296,107 @@ void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth, ...@@ -1288,79 +1296,107 @@ void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth,
} }
void InitialGain819xPci(struct net_device *dev, u8 Operation) void InitialGain819xPci(struct net_device *dev, u8 Operation)
{ {
#define SCAN_RX_INITIAL_GAIN 0x17 #define SCAN_RX_INITIAL_GAIN 0x17
#define POWER_DETECTION_TH 0x08 #define POWER_DETECTION_TH 0x08
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
u32 BitMask; u32 BitMask;
u8 initial_gain; u8 initial_gain;
if (!IS_NIC_DOWN(priv)){ if (!IS_NIC_DOWN(priv)) {
switch (Operation) switch (Operation) {
{ case IG_Backup:
case IG_Backup: RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial"
RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n"); " gain.\n");
initial_gain = SCAN_RX_INITIAL_GAIN; initial_gain = SCAN_RX_INITIAL_GAIN;
BitMask = bMaskByte0; BitMask = bMaskByte0;
if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) if (dm_digtable.dig_algorithm ==
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); DIG_ALGO_BY_FALSE_ALARM)
priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask); rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask); priv->initgain_backup.xaagccore1 =
priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask); (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1,
priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask); BitMask);
BitMask = bMaskByte2; priv->initgain_backup.xbagccore1 =
priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask); (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1,
BitMask);
RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1); priv->initgain_backup.xcagccore1 =
RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1); (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1,
RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1); BitMask);
RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1); priv->initgain_backup.xdagccore1 =
RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca); (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1,
BitMask);
RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain); BitMask = bMaskByte2;
write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain); priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev,
write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain); rCCK0_CCA, BitMask);
write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain); RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is"
RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH); " %x\n", priv->initgain_backup.xaagccore1);
write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH); RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is"
break; " %x\n", priv->initgain_backup.xbagccore1);
case IG_Restore: RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is"
RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n"); " %x\n", priv->initgain_backup.xcagccore1);
BitMask = 0x7f; RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is"
if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) " %x\n", priv->initgain_backup.xdagccore1);
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is"
" %x\n", priv->initgain_backup.cca);
rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1); RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x\n",
rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1); initial_gain);
rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1); write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
BitMask = bMaskByte2; write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca); write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1); RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x\n",
RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1); POWER_DETECTION_TH);
RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1); write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1); break;
RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca); case IG_Restore:
RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial "
rtl8192_phy_setTxPower(dev,priv->rtllib->current_network.channel); "gain.\n");
BitMask = 0x7f;
if (dm_digtable.dig_algorithm ==
if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM) DIG_ALGO_BY_FALSE_ALARM)
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
break;
default: rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask,
RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n"); (u32)priv->initgain_backup.xaagccore1);
break; rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask,
(u32)priv->initgain_backup.xbagccore1);
rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask,
(u32)priv->initgain_backup.xcagccore1);
rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask,
(u32)priv->initgain_backup.xdagccore1);
BitMask = bMaskByte2;
rtl8192_setBBreg(dev, rCCK0_CCA, BitMask,
(u32)priv->initgain_backup.cca);
RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50"
" is %x\n", priv->initgain_backup.xaagccore1);
RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58"
" is %x\n", priv->initgain_backup.xbagccore1);
RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60"
" is %x\n", priv->initgain_backup.xcagccore1);
RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68"
" is %x\n", priv->initgain_backup.xdagccore1);
RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a"
" is %x\n", priv->initgain_backup.cca);
rtl8192_phy_setTxPower(dev,
priv->rtllib->current_network.channel);
if (dm_digtable.dig_algorithm ==
DIG_ALGO_BY_FALSE_ALARM)
rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
break;
default:
RT_TRACE(COMP_SCAN, "Unknown IG Operation.\n");
break;
} }
} }
} }
extern void void PHY_SetRtl8192eRfOff(struct net_device *dev)
PHY_SetRtl8192eRfOff(struct net_device* dev )
{ {
rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);
...@@ -1374,14 +1410,12 @@ PHY_SetRtl8192eRfOff(struct net_device* dev ) ...@@ -1374,14 +1410,12 @@ PHY_SetRtl8192eRfOff(struct net_device* dev )
} }
bool bool SetRFPowerState8190(struct net_device *dev,
SetRFPowerState8190( enum rt_rf_power_state eRFPowerState)
struct net_device* dev,
enum rt_rf_power_state eRFPowerState
)
{ {
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *)(&(priv->rtllib->PowerSaveControl)); struct rt_pwr_save_ctrl *pPSC = (struct rt_pwr_save_ctrl *)
(&(priv->rtllib->PowerSaveControl));
bool bResult = true; bool bResult = true;
u8 i = 0, QueueID = 0; u8 i = 0, QueueID = 0;
struct rtl8192_tx_ring *ring = NULL; struct rtl8192_tx_ring *ring = NULL;
...@@ -1391,137 +1425,142 @@ SetRFPowerState8190( ...@@ -1391,137 +1425,142 @@ SetRFPowerState8190(
RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n"); RT_TRACE(COMP_PS, "===========> SetRFPowerState8190()!\n");
priv->SetRFPowerStateInProgress = true; priv->SetRFPowerStateInProgress = true;
switch (priv->rf_chip) switch (priv->rf_chip) {
{ case RF_8256:
case RF_8256: switch (eRFPowerState) {
switch ( eRFPowerState ) case eRfOn:
{ RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn!\n");
case eRfOn: if ((priv->rtllib->eRFPowerState == eRfOff) &&
RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOn !\n"); RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
if ((priv->rtllib->eRFPowerState == eRfOff) && RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) bool rtstatus = true;
{ u32 InitilizeCount = 3;
bool rtstatus = true; do {
u32 InitilizeCount = 3; InitilizeCount--;
do priv->RegRfOff = false;
{ rtstatus = NicIFEnableNIC(dev);
InitilizeCount--; } while ((rtstatus != true) &&
priv->RegRfOff = false; (InitilizeCount > 0));
rtstatus = NicIFEnableNIC(dev);
}while( (rtstatus != true) &&(InitilizeCount >0) ); if (rtstatus != true) {
RT_TRACE(COMP_ERR, "%s():Initialize Ada"
if (rtstatus != true) "pter fail,return\n",
{ __func__);
RT_TRACE(COMP_ERR,"%s():Initialize Adapter fail,return\n",__func__); priv->SetRFPowerStateInProgress = false;
priv->SetRFPowerStateInProgress = false; return false;
return false; }
}
RT_CLEAR_PS_LEVEL(pPSC,
RT_CLEAR_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC); RT_RF_OFF_LEVL_HALT_NIC);
} else { } else {
write_nic_byte(dev, ANAPAR, 0x37); write_nic_byte(dev, ANAPAR, 0x37);
mdelay(1); mdelay(1);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x4, 0x1); rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
0x4, 0x1);
priv->bHwRfOffAction = 0; priv->bHwRfOffAction = 0;
rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE,
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); BIT4, 0x1);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4,
rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3); 0x300, 0x3);
rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3); rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); 0x18, 0x3);
rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3,
0x3);
rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3,
0x3);
rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1,
0x60, 0x3);
} }
break; break;
case eRfSleep:
if (priv->rtllib->eRFPowerState == eRfOff)
break;
case eRfSleep:
{
if (priv->rtllib->eRFPowerState == eRfOff)
break;
for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
ring = &priv->tx_ring[QueueID];
{ if (skb_queue_len(&ring->queue) == 0) {
for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) QueueID++;
{ continue;
ring = &priv->tx_ring[QueueID]; } else {
RT_TRACE((COMP_POWER|COMP_RF), "eRf Off"
if (skb_queue_len(&ring->queue) == 0) { "/Sleep: %d times TcbBusyQueue"
QueueID++; "[%d] !=0 before doze!\n",
continue; (i+1), QueueID);
} udelay(10);
else i++;
{
RT_TRACE((COMP_POWER|COMP_RF), "eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID);
udelay(10);
i++;
}
if (i >= MAX_DOZE_WAITING_TIMES_9x)
{
RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! SetRFPowerState8190(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
break;
}
}
} }
{ if (i >= MAX_DOZE_WAITING_TIMES_9x) {
PHY_SetRtl8192eRfOff(dev); RT_TRACE(COMP_POWER, "\n\n\n TimeOut!! "
"SetRFPowerState8190(): eRfOff"
": %d times TcbBusyQueue[%d] "
"!= 0 !!!\n",
MAX_DOZE_WAITING_TIMES_9x,
QueueID);
break;
} }
} }
break; PHY_SetRtl8192eRfOff(dev);
break;
case eRfOff:
RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOff/Sleep !\n"); case eRfOff:
RT_TRACE(COMP_PS, "SetRFPowerState8190() eRfOff/"
"Sleep !\n");
for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
ring = &priv->tx_ring[QueueID]; for (QueueID = 0, i = 0; QueueID < MAX_TX_QUEUE; ) {
ring = &priv->tx_ring[QueueID];
if (skb_queue_len(&ring->queue) == 0) {
QueueID++; if (skb_queue_len(&ring->queue) == 0) {
continue; QueueID++;
} continue;
else } else {
{ RT_TRACE(COMP_POWER, "eRf Off/Sleep: %d"
RT_TRACE(COMP_POWER, " times TcbBusyQueue[%d] !=0 b"
"eRf Off/Sleep: %d times TcbBusyQueue[%d] !=0 before doze!\n", (i+1), QueueID); "efore doze!\n", (i+1),
udelay(10); QueueID);
i++; udelay(10);
} i++;
if (i >= MAX_DOZE_WAITING_TIMES_9x)
{
RT_TRACE(COMP_POWER, "\n\n\n SetZebraRFPowerState8185B(): eRfOff: %d times TcbBusyQueue[%d] != 0 !!!\n\n\n", MAX_DOZE_WAITING_TIMES_9x, QueueID);
break;
}
}
{
if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC && !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC))
{
NicIFDisableNIC(dev);
RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
}
else if (!(pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC))
{
PHY_SetRtl8192eRfOff(dev);
}
} }
if (i >= MAX_DOZE_WAITING_TIMES_9x) {
RT_TRACE(COMP_POWER, "\n\n\n SetZebra: "
"RFPowerState8185B(): eRfOff:"
" %d times TcbBusyQueue[%d] "
"!= 0 !!!\n",
MAX_DOZE_WAITING_TIMES_9x,
QueueID);
break; break;
}
}
default: if (pPSC->RegRfPsLevel & RT_RF_OFF_LEVL_HALT_NIC &&
bResult = false; !RT_IN_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC)) {
RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state to set: 0x%X!!!\n", eRFPowerState); NicIFDisableNIC(dev);
break; RT_SET_PS_LEVEL(pPSC, RT_RF_OFF_LEVL_HALT_NIC);
} } else if (!(pPSC->RegRfPsLevel &
RT_RF_OFF_LEVL_HALT_NIC)) {
PHY_SetRtl8192eRfOff(dev);
}
break; break;
default: default:
RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n"); bResult = false;
RT_TRACE(COMP_ERR, "SetRFPowerState8190(): unknow state"
" to set: 0x%X!!!\n", eRFPowerState);
break; break;
}
break;
default:
RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n");
break;
} }
if (bResult) { if (bResult) {
...@@ -1532,62 +1571,60 @@ SetRFPowerState8190( ...@@ -1532,62 +1571,60 @@ SetRFPowerState8190(
break; break;
default: default:
RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown RF type\n"); RT_TRACE(COMP_ERR, "SetRFPowerState8190(): Unknown "
"RF type\n");
break; break;
} }
} }
priv->SetRFPowerStateInProgress = false; priv->SetRFPowerStateInProgress = false;
RT_TRACE(COMP_PS, "<=========== SetRFPowerState8190() bResult = %d!\n", bResult); RT_TRACE(COMP_PS, "<=========== SetRFPowerState8190() bResult = %d!\n",
bResult);
return bResult; return bResult;
} }
bool SetRFPowerState(struct net_device *dev,
enum rt_rf_power_state eRFPowerState)
bool
SetRFPowerState(
struct net_device* dev,
enum rt_rf_power_state eRFPowerState
)
{ {
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
bool bResult = false; bool bResult = false;
RT_TRACE(COMP_PS,"---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState); RT_TRACE(COMP_PS, "---------> SetRFPowerState(): eRFPowerState(%d)\n",
if (eRFPowerState == priv->rtllib->eRFPowerState && priv->bHwRfOffAction == 0) { eRFPowerState);
RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState); if (eRFPowerState == priv->rtllib->eRFPowerState &&
priv->bHwRfOffAction == 0) {
RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): discard the "
"request for eRFPowerState(%d) is the same.\n",
eRFPowerState);
return bResult; return bResult;
} }
bResult = SetRFPowerState8190(dev, eRFPowerState); bResult = SetRFPowerState8190(dev, eRFPowerState);
RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): bResult(%d)\n", bResult); RT_TRACE(COMP_PS, "<--------- SetRFPowerState(): bResult(%d)\n",
bResult);
return bResult; return bResult;
} }
extern void extern void PHY_ScanOperationBackup8192(struct net_device *dev, u8 Operation)
PHY_ScanOperationBackup8192(
struct net_device* dev,
u8 Operation
)
{ {
struct r8192_priv *priv = rtllib_priv(dev); struct r8192_priv *priv = rtllib_priv(dev);
if (priv->up) { if (priv->up) {
switch (Operation) { switch (Operation) {
case SCAN_OPT_BACKUP: case SCAN_OPT_BACKUP:
priv->rtllib->InitialGainHandler(dev,IG_Backup); priv->rtllib->InitialGainHandler(dev, IG_Backup);
break; break;
case SCAN_OPT_RESTORE: case SCAN_OPT_RESTORE:
priv->rtllib->InitialGainHandler(dev,IG_Restore); priv->rtllib->InitialGainHandler(dev, IG_Restore);
break; break;
default: default:
RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation. \n"); RT_TRACE(COMP_SCAN, "Unknown Scan Backup Operation.\n");
break; break;
} }
} }
......
drivers/staging/rtl8192e/r8192E_phy.h
View file @ b0969341
...@@ -25,25 +25,25 @@ ...@@ -25,25 +25,25 @@
#define MAX_RFDEPENDCMD_CNT 16 #define MAX_RFDEPENDCMD_CNT 16
#define MAX_POSTCMD_CNT 16 #define MAX_POSTCMD_CNT 16
#define AGCTAB_ArrayLength AGCTAB_ArrayLengthPciE #define AGCTAB_ArrayLength AGCTAB_ArrayLengthPciE
#define MACPHY_ArrayLength MACPHY_ArrayLengthPciE #define MACPHY_ArrayLength MACPHY_ArrayLengthPciE
#define RadioA_ArrayLength RadioA_ArrayLengthPciE #define RadioA_ArrayLength RadioA_ArrayLengthPciE
#define RadioB_ArrayLength RadioB_ArrayLengthPciE #define RadioB_ArrayLength RadioB_ArrayLengthPciE
#define MACPHY_Array_PGLength MACPHY_Array_PGLengthPciE #define MACPHY_Array_PGLength MACPHY_Array_PGLengthPciE
#define RadioC_ArrayLength RadioC_ArrayLengthPciE #define RadioC_ArrayLength RadioC_ArrayLengthPciE
#define RadioD_ArrayLength RadioD_ArrayLengthPciE #define RadioD_ArrayLength RadioD_ArrayLengthPciE
#define PHY_REGArrayLength PHY_REGArrayLengthPciE #define PHY_REGArrayLength PHY_REGArrayLengthPciE
#define PHY_REG_1T2RArrayLength PHY_REG_1T2RArrayLengthPciE #define PHY_REG_1T2RArrayLength PHY_REG_1T2RArrayLengthPciE
#define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG #define Rtl819XMACPHY_Array_PG Rtl8192PciEMACPHY_Array_PG
#define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array #define Rtl819XMACPHY_Array Rtl8192PciEMACPHY_Array
#define Rtl819XRadioA_Array Rtl8192PciERadioA_Array #define Rtl819XRadioA_Array Rtl8192PciERadioA_Array
#define Rtl819XRadioB_Array Rtl8192PciERadioB_Array #define Rtl819XRadioB_Array Rtl8192PciERadioB_Array
#define Rtl819XRadioC_Array Rtl8192PciERadioC_Array #define Rtl819XRadioC_Array Rtl8192PciERadioC_Array
#define Rtl819XRadioD_Array Rtl8192PciERadioD_Array #define Rtl819XRadioD_Array Rtl8192PciERadioD_Array
#define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array #define Rtl819XAGCTAB_Array Rtl8192PciEAGCTAB_Array
#define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray #define Rtl819XPHY_REGArray Rtl8192PciEPHY_REGArray
#define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray #define Rtl819XPHY_REG_1T2RArray Rtl8192PciEPHY_REG_1T2RArray
...@@ -57,7 +57,7 @@ enum sw_chnl_cmd_id { ...@@ -57,7 +57,7 @@ enum sw_chnl_cmd_id {
CmdID_RF_WriteReg, CmdID_RF_WriteReg,
}; };
/*--------------------------------Define structure--------------------------------*/ /*--------------------------------Define structure----------------------------*/
struct sw_chnl_cmd { struct sw_chnl_cmd {
enum sw_chnl_cmd_id CmdID; enum sw_chnl_cmd_id CmdID;
u32 Para1; u32 Para1;
...@@ -97,23 +97,35 @@ enum rf90_radio_path { ...@@ -97,23 +97,35 @@ enum rf90_radio_path {
#define bMaskLWord 0x0000ffff #define bMaskLWord 0x0000ffff
#define bMaskDWord 0xffffffff #define bMaskDWord 0xffffffff
extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath); extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev,
extern void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData); u32 eRFPath);
extern u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask); extern void rtl8192_setBBreg(struct net_device *dev, u32 dwRegAddr,
extern void rtl8192_phy_SetRFReg(struct net_device* dev, enum rf90_radio_path eRFPath, u32 RegAddr, u32 BitMask, u32 Data); u32 dwBitMask, u32 dwData);
extern u32 rtl8192_phy_QueryRFReg(struct net_device* dev, enum rf90_radio_path eRFPath, u32 RegAddr, u32 BitMask); extern u32 rtl8192_QueryBBReg(struct net_device *dev, u32 dwRegAddr,
extern void rtl8192_phy_configmac(struct net_device* dev); u32 dwBitMask);
extern void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType); extern void rtl8192_phy_SetRFReg(struct net_device *dev,
extern bool rtl8192_phy_checkBBAndRF(struct net_device* dev, enum hw90_block CheckBlock, enum rf90_radio_path eRFPath); enum rf90_radio_path eRFPath,
extern bool rtl8192_BBConfig(struct net_device* dev); u32 RegAddr, u32 BitMask, u32 Data);
extern void rtl8192_phy_getTxPower(struct net_device* dev); extern u32 rtl8192_phy_QueryRFReg(struct net_device *dev,
extern void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel); enum rf90_radio_path eRFPath,
extern bool rtl8192_phy_RFConfig(struct net_device* dev); u32 RegAddr, u32 BitMask);
extern void rtl8192_phy_updateInitGain(struct net_device* dev); extern void rtl8192_phy_configmac(struct net_device *dev);
extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, enum rf90_radio_path eRFPath); extern void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType);
extern bool rtl8192_phy_checkBBAndRF(struct net_device *dev,
extern u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel); enum hw90_block CheckBlock,
extern void rtl8192_SetBWMode(struct net_device *dev, enum ht_channel_width Bandwidth, enum ht_extchnl_offset Offset); enum rf90_radio_path eRFPath);
extern bool rtl8192_BBConfig(struct net_device *dev);
extern void rtl8192_phy_getTxPower(struct net_device *dev);
extern void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel);
extern bool rtl8192_phy_RFConfig(struct net_device *dev);
extern void rtl8192_phy_updateInitGain(struct net_device *dev);
extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
enum rf90_radio_path eRFPath);
extern u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel);
extern void rtl8192_SetBWMode(struct net_device *dev,
enum ht_channel_width Bandwidth,
enum ht_extchnl_offset Offset);
extern void rtl8192_SwChnl_WorkItem(struct net_device *dev); extern void rtl8192_SwChnl_WorkItem(struct net_device *dev);
extern void rtl8192_SetBWModeWorkItem(struct net_device *dev); extern void rtl8192_SetBWModeWorkItem(struct net_device *dev);
extern void InitialGain819xPci(struct net_device *dev, u8 Operation); extern void InitialGain819xPci(struct net_device *dev, u8 Operation);
...@@ -122,11 +134,11 @@ extern void PHY_SetRtl8192eRfOff(struct net_device *dev); ...@@ -122,11 +134,11 @@ extern void PHY_SetRtl8192eRfOff(struct net_device *dev);
bool bool
SetRFPowerState( SetRFPowerState(
struct net_device* dev, struct net_device *dev,
enum rt_rf_power_state eRFPowerState enum rt_rf_power_state eRFPowerState
); );
#define PHY_SetRFPowerState SetRFPowerState #define PHY_SetRFPowerState SetRFPowerState
extern void PHY_ScanOperationBackup8192(struct net_device* dev,u8 Operation); extern void PHY_ScanOperationBackup8192(struct net_device *dev, u8 Operation);
#endif #endif
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