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Commit b42e6dc6 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'microblaze-3.15-rc1' of git://git.monstr.eu/linux-2.6-microblaze 

Pull Microblaze updates from Michal Simek:
 - use asm-generic/io.h and fix intc/timer code
 - clean platform handling
 - enable some syscalls

* tag 'microblaze-3.15-rc1' of git://git.monstr.eu/linux-2.6-microblaze:
  microblaze: Use asm-generic/io.h
  microblaze: Remove platform folder
  microblaze: Remove generic platform
  microblaze: Sort Kconfig options
  microblaze: Move DTS file to common location at boot/dts folder
  microblaze: Fix compilation failure because of release_thread
  microblaze: Fix sparse warning because of missing cpu.h header
  microblaze: Make timer driver endian aware
  microblaze: Make intc driver endian aware
  microblaze: Wire-up new system calls sched_setattr/getattr
  microblaze: Wire-up preadv/pwritev in syscall table
  microblaze: Enable pselect6 syscall
  microblaze: Drop architecture-specific declaration of early_printk
  microblaze: Rename global function heartbeat()
parents 9e897e13 a66a6265
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arch/microblaze/Kconfig
View file @ b42e6dc6
config MICROBLAZE config MICROBLAZE
def_bool y def_bool y
select ARCH_MIGHT_HAVE_PC_PARPORT select ARCH_MIGHT_HAVE_PC_PARPORT
select HAVE_MEMBLOCK
select HAVE_MEMBLOCK_NODE_MAP
select HAVE_FUNCTION_TRACER
select HAVE_FUNCTION_TRACE_MCOUNT_TEST
select HAVE_FUNCTION_GRAPH_TRACER
select HAVE_DYNAMIC_FTRACE
select HAVE_FTRACE_MCOUNT_RECORD
select ARCH_WANT_OPTIONAL_GPIOLIB
select HAVE_OPROFILE
select HAVE_ARCH_KGDB
select HAVE_DMA_ATTRS
select HAVE_DMA_API_DEBUG
select TRACING_SUPPORT
select OF
select OF_EARLY_FLATTREE
select ARCH_WANT_IPC_PARSE_VERSION select ARCH_WANT_IPC_PARSE_VERSION
select HAVE_DEBUG_KMEMLEAK select ARCH_WANT_OPTIONAL_GPIOLIB
select IRQ_DOMAIN select BUILDTIME_EXTABLE_SORT
select VIRT_TO_BUS select CLKSRC_OF
select CLONE_BACKWARDS3
select COMMON_CLK
select GENERIC_ATOMIC64
select GENERIC_CLOCKEVENTS
select GENERIC_CPU_DEVICES
select GENERIC_IDLE_POLL_SETUP
select GENERIC_IRQ_PROBE select GENERIC_IRQ_PROBE
select GENERIC_IRQ_SHOW select GENERIC_IRQ_SHOW
select GENERIC_PCI_IOMAP select GENERIC_PCI_IOMAP
select GENERIC_CPU_DEVICES
select GENERIC_ATOMIC64
select GENERIC_CLOCKEVENTS
select COMMON_CLK
select GENERIC_SCHED_CLOCK select GENERIC_SCHED_CLOCK
select GENERIC_IDLE_POLL_SETUP select HAVE_ARCH_KGDB
select HAVE_DEBUG_KMEMLEAK
select HAVE_DMA_API_DEBUG
select HAVE_DMA_ATTRS
select HAVE_DYNAMIC_FTRACE
select HAVE_FTRACE_MCOUNT_RECORD
select HAVE_FUNCTION_GRAPH_TRACER
select HAVE_FUNCTION_TRACE_MCOUNT_TEST
select HAVE_FUNCTION_TRACER
select HAVE_MEMBLOCK
select HAVE_MEMBLOCK_NODE_MAP
select HAVE_OPROFILE
select IRQ_DOMAIN
select MODULES_USE_ELF_RELA select MODULES_USE_ELF_RELA
select CLONE_BACKWARDS3 select OF
select CLKSRC_OF select OF_EARLY_FLATTREE
select BUILDTIME_EXTABLE_SORT select TRACING_SUPPORT
select VIRT_TO_BUS
config SWAP config SWAP
def_bool n def_bool n
...@@ -74,7 +74,7 @@ source "init/Kconfig" ...@@ -74,7 +74,7 @@ source "init/Kconfig"
source "kernel/Kconfig.freezer" source "kernel/Kconfig.freezer"
source "arch/microblaze/platform/Kconfig.platform" source "arch/microblaze/Kconfig.platform"
menu "Processor type and features" menu "Processor type and features"
......
arch/microblaze/platform/Kconfig.platform → arch/microblaze/Kconfig.platform
View file @ b42e6dc6
...@@ -5,18 +5,6 @@ ...@@ -5,18 +5,6 @@
# #
menu "Platform options" menu "Platform options"
choice
prompt "Platform"
default PLATFORM_MICROBLAZE_AUTO
help
Choose which hardware board/platform you are targeting.
config PLATFORM_GENERIC
bool "Generic"
help
Choose this option for the Generic platform.
endchoice
config OPT_LIB_FUNCTION config OPT_LIB_FUNCTION
bool "Optimalized lib function" bool "Optimalized lib function"
...@@ -37,8 +25,45 @@ config OPT_LIB_ASM ...@@ -37,8 +25,45 @@ config OPT_LIB_ASM
Allows turn on optimalized library function (memcpy and memmove). Allows turn on optimalized library function (memcpy and memmove).
Function are written in asm code. Function are written in asm code.
if PLATFORM_GENERIC=y # Definitions for MICROBLAZE0
source "arch/microblaze/platform/generic/Kconfig.auto" comment "Definitions for MICROBLAZE0"
endif
config KERNEL_BASE_ADDR
hex "Physical address where Linux Kernel is"
default "0x90000000"
help
BASE Address for kernel
config XILINX_MICROBLAZE0_FAMILY
string "Targeted FPGA family"
default "virtex5"
config XILINX_MICROBLAZE0_USE_MSR_INSTR
int "USE_MSR_INSTR range (0:1)"
default 0
config XILINX_MICROBLAZE0_USE_PCMP_INSTR
int "USE_PCMP_INSTR range (0:1)"
default 0
config XILINX_MICROBLAZE0_USE_BARREL
int "USE_BARREL range (0:1)"
default 0
config XILINX_MICROBLAZE0_USE_DIV
int "USE_DIV range (0:1)"
default 0
config XILINX_MICROBLAZE0_USE_HW_MUL
int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
default 0
config XILINX_MICROBLAZE0_USE_FPU
int "USE_FPU values (0=NONE, 1=BASIC, 2=EXTENDED)"
default 0
config XILINX_MICROBLAZE0_HW_VER
string "Core version number"
default 7.10.d
endmenu endmenu
arch/microblaze/Makefile
View file @ b42e6dc6
...@@ -48,7 +48,6 @@ head-y := arch/microblaze/kernel/head.o ...@@ -48,7 +48,6 @@ head-y := arch/microblaze/kernel/head.o
libs-y += arch/microblaze/lib/ libs-y += arch/microblaze/lib/
core-y += arch/microblaze/kernel/ core-y += arch/microblaze/kernel/
core-y += arch/microblaze/mm/ core-y += arch/microblaze/mm/
core-y += arch/microblaze/platform/
core-$(CONFIG_PCI) += arch/microblaze/pci/ core-$(CONFIG_PCI) += arch/microblaze/pci/
drivers-$(CONFIG_OPROFILE) += arch/microblaze/oprofile/ drivers-$(CONFIG_OPROFILE) += arch/microblaze/oprofile/
......
arch/microblaze/boot/dts/system.dts deleted 120000 → 0
View file @ 9e897e13
../../platform/generic/system.dts
\ No newline at end of file
arch/microblaze/boot/dts/system.dts 0 → 100644
View file @ b42e6dc6
This diff is collapsed.
arch/microblaze/include/asm/io.h
View file @ b42e6dc6
...@@ -15,7 +15,6 @@ ...@@ -15,7 +15,6 @@
#include <asm/page.h> #include <asm/page.h>
#include <linux/types.h> #include <linux/types.h>
#include <linux/mm.h> /* Get struct page {...} */ #include <linux/mm.h> /* Get struct page {...} */
#include <asm-generic/iomap.h>
#ifndef CONFIG_PCI #ifndef CONFIG_PCI
#define _IO_BASE 0 #define _IO_BASE 0
...@@ -25,211 +24,32 @@ ...@@ -25,211 +24,32 @@
#define _IO_BASE isa_io_base #define _IO_BASE isa_io_base
#define _ISA_MEM_BASE isa_mem_base #define _ISA_MEM_BASE isa_mem_base
#define PCI_DRAM_OFFSET pci_dram_offset #define PCI_DRAM_OFFSET pci_dram_offset
#endif struct pci_dev;
extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
#define pci_iounmap pci_iounmap
extern unsigned long isa_io_base; extern unsigned long isa_io_base;
extern unsigned long pci_io_base;
extern unsigned long pci_dram_offset; extern unsigned long pci_dram_offset;
extern resource_size_t isa_mem_base; extern resource_size_t isa_mem_base;
#endif
#define PCI_IOBASE ((void __iomem *)_IO_BASE)
#define IO_SPACE_LIMIT (0xFFFFFFFF) #define IO_SPACE_LIMIT (0xFFFFFFFF)
/* the following is needed to support PCI with some drivers */
#define mmiowb()
static inline unsigned char __raw_readb(const volatile void __iomem *addr)
{
return *(volatile unsigned char __force *)addr;
}
static inline unsigned short __raw_readw(const volatile void __iomem *addr)
{
return *(volatile unsigned short __force *)addr;
}
static inline unsigned int __raw_readl(const volatile void __iomem *addr)
{
return *(volatile unsigned int __force *)addr;
}
static inline unsigned long __raw_readq(const volatile void __iomem *addr)
{
return *(volatile unsigned long __force *)addr;
}
static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
{
*(volatile unsigned char __force *)addr = v;
}
static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
{
*(volatile unsigned short __force *)addr = v;
}
static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
{
*(volatile unsigned int __force *)addr = v;
}
static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
{
*(volatile unsigned long __force *)addr = v;
}
/*
* read (readb, readw, readl, readq) and write (writeb, writew,
* writel, writeq) accessors are for PCI and thus little endian.
* Linux 2.4 for Microblaze had this wrong.
*/
static inline unsigned char readb(const volatile void __iomem *addr)
{
return *(volatile unsigned char __force *)addr;
}
static inline unsigned short readw(const volatile void __iomem *addr)
{
return le16_to_cpu(*(volatile unsigned short __force *)addr);
}
static inline unsigned int readl(const volatile void __iomem *addr)
{
return le32_to_cpu(*(volatile unsigned int __force *)addr);
}
#define readq readq
static inline u64 readq(const volatile void __iomem *addr)
{
return le64_to_cpu(__raw_readq(addr));
}
static inline void writeb(unsigned char v, volatile void __iomem *addr)
{
*(volatile unsigned char __force *)addr = v;
}
static inline void writew(unsigned short v, volatile void __iomem *addr)
{
*(volatile unsigned short __force *)addr = cpu_to_le16(v);
}
static inline void writel(unsigned int v, volatile void __iomem *addr)
{
*(volatile unsigned int __force *)addr = cpu_to_le32(v);
}
#define writeq(b, addr) __raw_writeq(cpu_to_le64(b), addr)
/* ioread and iowrite variants. thease are for now same as __raw_
* variants of accessors. we might check for endianess in the feature
*/
#define ioread8(addr) __raw_readb((u8 *)(addr))
#define ioread16(addr) __raw_readw((u16 *)(addr))
#define ioread32(addr) __raw_readl((u32 *)(addr))
#define iowrite8(v, addr) __raw_writeb((u8)(v), (u8 *)(addr))
#define iowrite16(v, addr) __raw_writew((u16)(v), (u16 *)(addr))
#define iowrite32(v, addr) __raw_writel((u32)(v), (u32 *)(addr))
#define ioread16be(addr) __raw_readw((u16 *)(addr))
#define ioread32be(addr) __raw_readl((u32 *)(addr))
#define iowrite16be(v, addr) __raw_writew((u16)(v), (u16 *)(addr))
#define iowrite32be(v, addr) __raw_writel((u32)(v), (u32 *)(addr))
/* These are the definitions for the x86 IO instructions
* inb/inw/inl/outb/outw/outl, the "string" versions
* insb/insw/insl/outsb/outsw/outsl, and the "pausing" versions
* inb_p/inw_p/...
* The macros don't do byte-swapping.
*/
#define inb(port) readb((u8 *)((unsigned long)(port)))
#define outb(val, port) writeb((val), (u8 *)((unsigned long)(port)))
#define inw(port) readw((u16 *)((unsigned long)(port)))
#define outw(val, port) writew((val), (u16 *)((unsigned long)(port)))
#define inl(port) readl((u32 *)((unsigned long)(port)))
#define outl(val, port) writel((val), (u32 *)((unsigned long)(port)))
#define inb_p(port) inb((port))
#define outb_p(val, port) outb((val), (port))
#define inw_p(port) inw((port))
#define outw_p(val, port) outw((val), (port))
#define inl_p(port) inl((port))
#define outl_p(val, port) outl((val), (port))
#define memset_io(a, b, c) memset((void *)(a), (b), (c))
#define memcpy_fromio(a, b, c) memcpy((a), (void *)(b), (c))
#define memcpy_toio(a, b, c) memcpy((void *)(a), (b), (c))
#ifdef CONFIG_MMU #ifdef CONFIG_MMU
#define phys_to_virt(addr) ((void *)__phys_to_virt(addr))
#define virt_to_phys(addr) ((unsigned long)__virt_to_phys(addr))
#define virt_to_bus(addr) ((unsigned long)__virt_to_phys(addr))
#define page_to_bus(page) (page_to_phys(page)) #define page_to_bus(page) (page_to_phys(page))
#define bus_to_virt(addr) (phys_to_virt(addr))
extern void iounmap(void __iomem *addr); extern void iounmap(void __iomem *addr);
/*extern void *__ioremap(phys_addr_t address, unsigned long size,
unsigned long flags);*/
extern void __iomem *ioremap(phys_addr_t address, unsigned long size); extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
#define ioremap_writethrough(addr, size) ioremap((addr), (size)) #define ioremap_writethrough(addr, size) ioremap((addr), (size))
#define ioremap_nocache(addr, size) ioremap((addr), (size)) #define ioremap_nocache(addr, size) ioremap((addr), (size))
#define ioremap_fullcache(addr, size) ioremap((addr), (size)) #define ioremap_fullcache(addr, size) ioremap((addr), (size))
#define ioremap_wc(addr, size) ioremap((addr), (size))
#else /* CONFIG_MMU */
/**
* virt_to_phys - map virtual addresses to physical
* @address: address to remap
*
* The returned physical address is the physical (CPU) mapping for
* the memory address given. It is only valid to use this function on
* addresses directly mapped or allocated via kmalloc.
*
* This function does not give bus mappings for DMA transfers. In
* almost all conceivable cases a device driver should not be using
* this function
*/
static inline unsigned long __iomem virt_to_phys(volatile void *address)
{
return __pa((unsigned long)address);
}
#define virt_to_bus virt_to_phys
/**
* phys_to_virt - map physical address to virtual
* @address: address to remap
*
* The returned virtual address is a current CPU mapping for
* the memory address given. It is only valid to use this function on
* addresses that have a kernel mapping
*
* This function does not handle bus mappings for DMA transfers. In
* almost all conceivable cases a device driver should not be using
* this function
*/
static inline void *phys_to_virt(unsigned long address)
{
return (void *)__va(address);
}
#define bus_to_virt(a) phys_to_virt(a)
static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size,
unsigned long flags)
{
return (void *)address;
}
#define ioremap(physaddr, size) ((void __iomem *)(unsigned long)(physaddr))
#define iounmap(addr) ((void)0)
#define ioremap_nocache(physaddr, size) ioremap(physaddr, size)
#endif /* CONFIG_MMU */ #endif /* CONFIG_MMU */
/* /* Big Endian */
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
* access
*/
#define xlate_dev_mem_ptr(p) __va(p)
/*
* Convert a virtual cached pointer to an uncached pointer
*/
#define xlate_dev_kmem_ptr(p) p
/*
* Big Endian
*/
#define out_be32(a, v) __raw_writel((v), (void __iomem __force *)(a)) #define out_be32(a, v) __raw_writel((v), (void __iomem __force *)(a))
#define out_be16(a, v) __raw_writew((v), (a)) #define out_be16(a, v) __raw_writew((v), (a))
...@@ -239,10 +59,7 @@ static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size, ...@@ -239,10 +59,7 @@ static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size,
#define writel_be(v, a) out_be32((__force unsigned *)a, v) #define writel_be(v, a) out_be32((__force unsigned *)a, v)
#define readl_be(a) in_be32((__force unsigned *)a) #define readl_be(a) in_be32((__force unsigned *)a)
/* /* Little endian */
* Little endian
*/
#define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (a)) #define out_le32(a, v) __raw_writel(__cpu_to_le32(v), (a))
#define out_le16(a, v) __raw_writew(__cpu_to_le16(v), (a)) #define out_le16(a, v) __raw_writew(__cpu_to_le16(v), (a))
...@@ -253,100 +70,7 @@ static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size, ...@@ -253,100 +70,7 @@ static inline void __iomem *__ioremap(phys_addr_t address, unsigned long size,
#define out_8(a, v) __raw_writeb((v), (a)) #define out_8(a, v) __raw_writeb((v), (a))
#define in_8(a) __raw_readb(a) #define in_8(a) __raw_readb(a)
#define mmiowb() #include <asm-generic/io.h>
#define ioport_map(port, nr) ((void __iomem *)(port))
#define ioport_unmap(addr)
/* from asm-generic/io.h */
#ifndef insb
static inline void insb(unsigned long addr, void *buffer, int count)
{
if (count) {
u8 *buf = buffer;
do {
u8 x = inb(addr);
*buf++ = x;
} while (--count);
}
}
#endif
#ifndef insw
static inline void insw(unsigned long addr, void *buffer, int count)
{
if (count) {
u16 *buf = buffer;
do {
u16 x = inw(addr);
*buf++ = x;
} while (--count);
}
}
#endif
#ifndef insl
static inline void insl(unsigned long addr, void *buffer, int count)
{
if (count) {
u32 *buf = buffer;
do {
u32 x = inl(addr);
*buf++ = x;
} while (--count);
}
}
#endif
#ifndef outsb
static inline void outsb(unsigned long addr, const void *buffer, int count)
{
if (count) {
const u8 *buf = buffer;
do {
outb(*buf++, addr);
} while (--count);
}
}
#endif
#ifndef outsw
static inline void outsw(unsigned long addr, const void *buffer, int count)
{
if (count) {
const u16 *buf = buffer;
do {
outw(*buf++, addr);
} while (--count);
}
}
#endif
#ifndef outsl
static inline void outsl(unsigned long addr, const void *buffer, int count)
{
if (count) {
const u32 *buf = buffer;
do {
outl(*buf++, addr);
} while (--count);
}
}
#endif
#define ioread8_rep(p, dst, count) \
insb((unsigned long) (p), (dst), (count))
#define ioread16_rep(p, dst, count) \
insw((unsigned long) (p), (dst), (count))
#define ioread32_rep(p, dst, count) \
insl((unsigned long) (p), (dst), (count))
#define iowrite8_rep(p, src, count) \
outsb((unsigned long) (p), (src), (count))
#define iowrite16_rep(p, src, count) \
outsw((unsigned long) (p), (src), (count))
#define iowrite32_rep(p, src, count) \
outsl((unsigned long) (p), (src), (count))
#define readb_relaxed readb #define readb_relaxed readb
#define readw_relaxed readw #define readw_relaxed readw
......
arch/microblaze/include/asm/processor.h
View file @ b42e6dc6
...@@ -122,7 +122,7 @@ struct thread_struct { ...@@ -122,7 +122,7 @@ struct thread_struct {
} }
/* Free all resources held by a thread. */ /* Free all resources held by a thread. */
extern inline void release_thread(struct task_struct *dead_task) static inline void release_thread(struct task_struct *dead_task)
{ {
} }
......
arch/microblaze/include/asm/setup.h
View file @ b42e6dc6
...@@ -19,14 +19,12 @@ extern char cmd_line[COMMAND_LINE_SIZE]; ...@@ -19,14 +19,12 @@ extern char cmd_line[COMMAND_LINE_SIZE];
extern char *klimit; extern char *klimit;
void early_printk(const char *fmt, ...);
int setup_early_printk(char *opt); int setup_early_printk(char *opt);
void remap_early_printk(void); void remap_early_printk(void);
void disable_early_printk(void); void disable_early_printk(void);
void heartbeat(void); void microblaze_heartbeat(void);
void setup_heartbeat(void); void microblaze_setup_heartbeat(void);
# ifdef CONFIG_MMU # ifdef CONFIG_MMU
extern void mmu_reset(void); extern void mmu_reset(void);
......
arch/microblaze/include/uapi/asm/unistd.h
View file @ b42e6dc6
...@@ -93,7 +93,7 @@ ...@@ -93,7 +93,7 @@
#define __NR_settimeofday 79 /* ok */ #define __NR_settimeofday 79 /* ok */
#define __NR_getgroups 80 /* ok */ #define __NR_getgroups 80 /* ok */
#define __NR_setgroups 81 /* ok */ #define __NR_setgroups 81 /* ok */
#define __NR_select 82 /* obsolete -> sys_pselect7 */ #define __NR_select 82 /* obsolete -> sys_pselect6 */
#define __NR_symlink 83 /* symlinkat */ #define __NR_symlink 83 /* symlinkat */
#define __NR_oldlstat 84 /* remove */ #define __NR_oldlstat 84 /* remove */
#define __NR_readlink 85 /* obsolete -> sys_readlinkat */ #define __NR_readlink 85 /* obsolete -> sys_readlinkat */
...@@ -320,7 +320,7 @@ ...@@ -320,7 +320,7 @@
#define __NR_readlinkat 305 /* ok */ #define __NR_readlinkat 305 /* ok */
#define __NR_fchmodat 306 /* ok */ #define __NR_fchmodat 306 /* ok */
#define __NR_faccessat 307 /* ok */ #define __NR_faccessat 307 /* ok */
#define __NR_pselect6 308 /* obsolete -> sys_pselect7 */ #define __NR_pselect6 308 /* ok */
#define __NR_ppoll 309 /* ok */ #define __NR_ppoll 309 /* ok */
#define __NR_unshare 310 /* ok */ #define __NR_unshare 310 /* ok */
#define __NR_set_robust_list 311 /* ok */ #define __NR_set_robust_list 311 /* ok */
...@@ -396,5 +396,7 @@ ...@@ -396,5 +396,7 @@
#define __NR_process_vm_writev 378 #define __NR_process_vm_writev 378
#define __NR_kcmp 379 #define __NR_kcmp 379
#define __NR_finit_module 380 #define __NR_finit_module 380
#define __NR_sched_setattr 381
#define __NR_sched_getattr 382
#endif /* _UAPI_ASM_MICROBLAZE_UNISTD_H */ #endif /* _UAPI_ASM_MICROBLAZE_UNISTD_H */
arch/microblaze/kernel/Makefile
View file @ b42e6dc6
...@@ -16,7 +16,7 @@ extra-y := head.o vmlinux.lds ...@@ -16,7 +16,7 @@ extra-y := head.o vmlinux.lds
obj-y += dma.o exceptions.o \ obj-y += dma.o exceptions.o \
hw_exception_handler.o intc.o irq.o \ hw_exception_handler.o intc.o irq.o \
process.o prom.o prom_parse.o ptrace.o \ platform.o process.o prom.o prom_parse.o ptrace.o \
reset.o setup.o signal.o sys_microblaze.o timer.o traps.o unwind.o reset.o setup.o signal.o sys_microblaze.o timer.o traps.o unwind.o
obj-y += cpu/ obj-y += cpu/
......
arch/microblaze/kernel/heartbeat.c
View file @ b42e6dc6
...@@ -17,7 +17,7 @@ ...@@ -17,7 +17,7 @@
static unsigned int base_addr; static unsigned int base_addr;
void heartbeat(void) void microblaze_heartbeat(void)
{ {
static unsigned int cnt, period, dist; static unsigned int cnt, period, dist;
...@@ -42,7 +42,7 @@ void heartbeat(void) ...@@ -42,7 +42,7 @@ void heartbeat(void)
} }
} }
void setup_heartbeat(void) void microblaze_setup_heartbeat(void)
{ {
struct device_node *gpio = NULL; struct device_node *gpio = NULL;
int *prop; int *prop;
......
arch/microblaze/kernel/intc.c
View file @ b42e6dc6
...@@ -32,6 +32,29 @@ static void __iomem *intc_baseaddr; ...@@ -32,6 +32,29 @@ static void __iomem *intc_baseaddr;
#define MER_ME (1<<0) #define MER_ME (1<<0)
#define MER_HIE (1<<1) #define MER_HIE (1<<1)
static unsigned int (*read_fn)(void __iomem *);
static void (*write_fn)(u32, void __iomem *);
static void intc_write32(u32 val, void __iomem *addr)
{
iowrite32(val, addr);
}
static unsigned int intc_read32(void __iomem *addr)
{
return ioread32(addr);
}
static void intc_write32_be(u32 val, void __iomem *addr)
{
iowrite32be(val, addr);
}
static unsigned int intc_read32_be(void __iomem *addr)
{
return ioread32be(addr);
}
static void intc_enable_or_unmask(struct irq_data *d) static void intc_enable_or_unmask(struct irq_data *d)
{ {
unsigned long mask = 1 << d->hwirq; unsigned long mask = 1 << d->hwirq;
...@@ -43,21 +66,21 @@ static void intc_enable_or_unmask(struct irq_data *d) ...@@ -43,21 +66,21 @@ static void intc_enable_or_unmask(struct irq_data *d)
* acks the irq before calling the interrupt handler * acks the irq before calling the interrupt handler
*/ */
if (irqd_is_level_type(d)) if (irqd_is_level_type(d))
out_be32(intc_baseaddr + IAR, mask); write_fn(mask, intc_baseaddr + IAR);
out_be32(intc_baseaddr + SIE, mask); write_fn(mask, intc_baseaddr + SIE);
} }
static void intc_disable_or_mask(struct irq_data *d) static void intc_disable_or_mask(struct irq_data *d)
{ {
pr_debug("disable: %ld\n", d->hwirq); pr_debug("disable: %ld\n", d->hwirq);
out_be32(intc_baseaddr + CIE, 1 << d->hwirq); write_fn(1 << d->hwirq, intc_baseaddr + CIE);
} }
static void intc_ack(struct irq_data *d) static void intc_ack(struct irq_data *d)
{ {
pr_debug("ack: %ld\n", d->hwirq); pr_debug("ack: %ld\n", d->hwirq);
out_be32(intc_baseaddr + IAR, 1 << d->hwirq); write_fn(1 << d->hwirq, intc_baseaddr + IAR);
} }
static void intc_mask_ack(struct irq_data *d) static void intc_mask_ack(struct irq_data *d)
...@@ -65,8 +88,8 @@ static void intc_mask_ack(struct irq_data *d) ...@@ -65,8 +88,8 @@ static void intc_mask_ack(struct irq_data *d)
unsigned long mask = 1 << d->hwirq; unsigned long mask = 1 << d->hwirq;
pr_debug("disable_and_ack: %ld\n", d->hwirq); pr_debug("disable_and_ack: %ld\n", d->hwirq);
out_be32(intc_baseaddr + CIE, mask); write_fn(mask, intc_baseaddr + CIE);
out_be32(intc_baseaddr + IAR, mask); write_fn(mask, intc_baseaddr + IAR);
} }
static struct irq_chip intc_dev = { static struct irq_chip intc_dev = {
...@@ -83,7 +106,7 @@ unsigned int get_irq(void) ...@@ -83,7 +106,7 @@ unsigned int get_irq(void)
{ {
unsigned int hwirq, irq = -1; unsigned int hwirq, irq = -1;
hwirq = in_be32(intc_baseaddr + IVR); hwirq = read_fn(intc_baseaddr + IVR);
if (hwirq != -1U) if (hwirq != -1U)
irq = irq_find_mapping(root_domain, hwirq); irq = irq_find_mapping(root_domain, hwirq);
...@@ -140,17 +163,25 @@ static int __init xilinx_intc_of_init(struct device_node *intc, ...@@ -140,17 +163,25 @@ static int __init xilinx_intc_of_init(struct device_node *intc,
pr_info("%s: num_irq=%d, edge=0x%x\n", pr_info("%s: num_irq=%d, edge=0x%x\n",
intc->full_name, nr_irq, intr_mask); intc->full_name, nr_irq, intr_mask);
write_fn = intc_write32;
read_fn = intc_read32;
/* /*
* Disable all external interrupts until they are * Disable all external interrupts until they are
* explicity requested. * explicity requested.
*/ */
out_be32(intc_baseaddr + IER, 0); write_fn(0, intc_baseaddr + IER);
/* Acknowledge any pending interrupts just in case. */ /* Acknowledge any pending interrupts just in case. */
out_be32(intc_baseaddr + IAR, 0xffffffff); write_fn(0xffffffff, intc_baseaddr + IAR);
/* Turn on the Master Enable. */ /* Turn on the Master Enable. */
out_be32(intc_baseaddr + MER, MER_HIE | MER_ME); write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
if (!(read_fn(intc_baseaddr + MER) & (MER_HIE | MER_ME))) {
write_fn = intc_write32_be;
read_fn = intc_read32_be;
write_fn(MER_HIE | MER_ME, intc_baseaddr + MER);
}
/* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm /* Yeah, okay, casting the intr_mask to a void* is butt-ugly, but I'm
* lazy and Michal can clean it up to something nicer when he tests * lazy and Michal can clean it up to something nicer when he tests
......
arch/microblaze/kernel/process.c
View file @ b42e6dc6
...@@ -8,6 +8,7 @@ ...@@ -8,6 +8,7 @@
* for more details. * for more details.
*/ */
#include <linux/cpu.h>
#include <linux/export.h> #include <linux/export.h>
#include <linux/sched.h> #include <linux/sched.h>
#include <linux/pm.h> #include <linux/pm.h>
......
arch/microblaze/kernel/signal.c
View file @ b42e6dc6
...@@ -216,7 +216,7 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info, ...@@ -216,7 +216,7 @@ static int setup_rt_frame(int sig, struct k_sigaction *ka, siginfo_t *info,
/* MS: I need add offset in page */ /* MS: I need add offset in page */
address += ((unsigned long)frame->tramp) & ~PAGE_MASK; address += ((unsigned long)frame->tramp) & ~PAGE_MASK;
/* MS address is virtual */ /* MS address is virtual */
address = virt_to_phys(address); address = __virt_to_phys(address);
invalidate_icache_range(address, address + 8); invalidate_icache_range(address, address + 8);
flush_dcache_range(address, address + 8); flush_dcache_range(address, address + 8);
} }
......
arch/microblaze/kernel/syscall_table.S
View file @ b42e6dc6
...@@ -308,7 +308,7 @@ ENTRY(sys_call_table) ...@@ -308,7 +308,7 @@ ENTRY(sys_call_table)
.long sys_readlinkat /* 305 */ .long sys_readlinkat /* 305 */
.long sys_fchmodat .long sys_fchmodat
.long sys_faccessat .long sys_faccessat
.long sys_ni_syscall /* pselect6 */ .long sys_pselect6
.long sys_ppoll .long sys_ppoll
.long sys_unshare /* 310 */ .long sys_unshare /* 310 */
.long sys_set_robust_list .long sys_set_robust_list
...@@ -363,8 +363,8 @@ ENTRY(sys_call_table) ...@@ -363,8 +363,8 @@ ENTRY(sys_call_table)
.long sys_sendmsg /* 360 */ .long sys_sendmsg /* 360 */
.long sys_recvmsg .long sys_recvmsg
.long sys_accept4 .long sys_accept4
.long sys_ni_syscall .long sys_preadv
.long sys_ni_syscall .long sys_pwritev
.long sys_rt_tgsigqueueinfo /* 365 */ .long sys_rt_tgsigqueueinfo /* 365 */
.long sys_perf_event_open .long sys_perf_event_open
.long sys_recvmmsg .long sys_recvmmsg
...@@ -381,3 +381,5 @@ ENTRY(sys_call_table) ...@@ -381,3 +381,5 @@ ENTRY(sys_call_table)
.long sys_process_vm_writev .long sys_process_vm_writev
.long sys_kcmp .long sys_kcmp
.long sys_finit_module .long sys_finit_module
.long sys_sched_setattr
.long sys_sched_getattr
arch/microblaze/kernel/timer.c
View file @ b42e6dc6
...@@ -43,10 +43,33 @@ static unsigned int timer_clock_freq; ...@@ -43,10 +43,33 @@ static unsigned int timer_clock_freq;
#define TCSR_PWMA (1<<9) #define TCSR_PWMA (1<<9)
#define TCSR_ENALL (1<<10) #define TCSR_ENALL (1<<10)
static unsigned int (*read_fn)(void __iomem *);
static void (*write_fn)(u32, void __iomem *);
static void timer_write32(u32 val, void __iomem *addr)
{
iowrite32(val, addr);
}
static unsigned int timer_read32(void __iomem *addr)
{
return ioread32(addr);
}
static void timer_write32_be(u32 val, void __iomem *addr)
{
iowrite32be(val, addr);
}
static unsigned int timer_read32_be(void __iomem *addr)
{
return ioread32be(addr);
}
static inline void xilinx_timer0_stop(void) static inline void xilinx_timer0_stop(void)
{ {
out_be32(timer_baseaddr + TCSR0, write_fn(read_fn(timer_baseaddr + TCSR0) & ~TCSR_ENT,
in_be32(timer_baseaddr + TCSR0) & ~TCSR_ENT); timer_baseaddr + TCSR0);
} }
static inline void xilinx_timer0_start_periodic(unsigned long load_val) static inline void xilinx_timer0_start_periodic(unsigned long load_val)
...@@ -54,10 +77,10 @@ static inline void xilinx_timer0_start_periodic(unsigned long load_val) ...@@ -54,10 +77,10 @@ static inline void xilinx_timer0_start_periodic(unsigned long load_val)
if (!load_val) if (!load_val)
load_val = 1; load_val = 1;
/* loading value to timer reg */ /* loading value to timer reg */
out_be32(timer_baseaddr + TLR0, load_val); write_fn(load_val, timer_baseaddr + TLR0);
/* load the initial value */ /* load the initial value */
out_be32(timer_baseaddr + TCSR0, TCSR_LOAD); write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
/* see timer data sheet for detail /* see timer data sheet for detail
* !ENALL - don't enable 'em all * !ENALL - don't enable 'em all
...@@ -72,8 +95,8 @@ static inline void xilinx_timer0_start_periodic(unsigned long load_val) ...@@ -72,8 +95,8 @@ static inline void xilinx_timer0_start_periodic(unsigned long load_val)
* UDT - set the timer as down counter * UDT - set the timer as down counter
* !MDT0 - generate mode * !MDT0 - generate mode
*/ */
out_be32(timer_baseaddr + TCSR0, write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); timer_baseaddr + TCSR0);
} }
static inline void xilinx_timer0_start_oneshot(unsigned long load_val) static inline void xilinx_timer0_start_oneshot(unsigned long load_val)
...@@ -81,13 +104,13 @@ static inline void xilinx_timer0_start_oneshot(unsigned long load_val) ...@@ -81,13 +104,13 @@ static inline void xilinx_timer0_start_oneshot(unsigned long load_val)
if (!load_val) if (!load_val)
load_val = 1; load_val = 1;
/* loading value to timer reg */ /* loading value to timer reg */
out_be32(timer_baseaddr + TLR0, load_val); write_fn(load_val, timer_baseaddr + TLR0);
/* load the initial value */ /* load the initial value */
out_be32(timer_baseaddr + TCSR0, TCSR_LOAD); write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
out_be32(timer_baseaddr + TCSR0, write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT); timer_baseaddr + TCSR0);
} }
static int xilinx_timer_set_next_event(unsigned long delta, static int xilinx_timer_set_next_event(unsigned long delta,
...@@ -133,14 +156,14 @@ static struct clock_event_device clockevent_xilinx_timer = { ...@@ -133,14 +156,14 @@ static struct clock_event_device clockevent_xilinx_timer = {
static inline void timer_ack(void) static inline void timer_ack(void)
{ {
out_be32(timer_baseaddr + TCSR0, in_be32(timer_baseaddr + TCSR0)); write_fn(read_fn(timer_baseaddr + TCSR0), timer_baseaddr + TCSR0);
} }
static irqreturn_t timer_interrupt(int irq, void *dev_id) static irqreturn_t timer_interrupt(int irq, void *dev_id)
{ {
struct clock_event_device *evt = &clockevent_xilinx_timer; struct clock_event_device *evt = &clockevent_xilinx_timer;
#ifdef CONFIG_HEART_BEAT #ifdef CONFIG_HEART_BEAT
heartbeat(); microblaze_heartbeat();
#endif #endif
timer_ack(); timer_ack();
evt->event_handler(evt); evt->event_handler(evt);
...@@ -169,7 +192,7 @@ static __init void xilinx_clockevent_init(void) ...@@ -169,7 +192,7 @@ static __init void xilinx_clockevent_init(void)
static u64 xilinx_clock_read(void) static u64 xilinx_clock_read(void)
{ {
return in_be32(timer_baseaddr + TCR1); return read_fn(timer_baseaddr + TCR1);
} }
static cycle_t xilinx_read(struct clocksource *cs) static cycle_t xilinx_read(struct clocksource *cs)
...@@ -217,10 +240,10 @@ static int __init xilinx_clocksource_init(void) ...@@ -217,10 +240,10 @@ static int __init xilinx_clocksource_init(void)
panic("failed to register clocksource"); panic("failed to register clocksource");
/* stop timer1 */ /* stop timer1 */
out_be32(timer_baseaddr + TCSR1, write_fn(read_fn(timer_baseaddr + TCSR1) & ~TCSR_ENT,
in_be32(timer_baseaddr + TCSR1) & ~TCSR_ENT); timer_baseaddr + TCSR1);
/* start timer1 - up counting without interrupt */ /* start timer1 - up counting without interrupt */
out_be32(timer_baseaddr + TCSR1, TCSR_TINT|TCSR_ENT|TCSR_ARHT); write_fn(TCSR_TINT|TCSR_ENT|TCSR_ARHT, timer_baseaddr + TCSR1);
/* register timecounter - for ftrace support */ /* register timecounter - for ftrace support */
init_xilinx_timecounter(); init_xilinx_timecounter();
...@@ -245,6 +268,15 @@ static void __init xilinx_timer_init(struct device_node *timer) ...@@ -245,6 +268,15 @@ static void __init xilinx_timer_init(struct device_node *timer)
BUG(); BUG();
} }
write_fn = timer_write32;
read_fn = timer_read32;
write_fn(TCSR_MDT, timer_baseaddr + TCSR0);
if (!(read_fn(timer_baseaddr + TCSR0) & TCSR_MDT)) {
write_fn = timer_write32_be;
read_fn = timer_read32_be;
}
irq = irq_of_parse_and_map(timer, 0); irq = irq_of_parse_and_map(timer, 0);
of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num); of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num);
...@@ -274,7 +306,7 @@ static void __init xilinx_timer_init(struct device_node *timer) ...@@ -274,7 +306,7 @@ static void __init xilinx_timer_init(struct device_node *timer)
setup_irq(irq, &timer_irqaction); setup_irq(irq, &timer_irqaction);
#ifdef CONFIG_HEART_BEAT #ifdef CONFIG_HEART_BEAT
setup_heartbeat(); microblaze_setup_heartbeat();
#endif #endif
xilinx_clocksource_init(); xilinx_clocksource_init();
xilinx_clockevent_init(); xilinx_clockevent_init();
......
arch/microblaze/mm/consistent.c
View file @ b42e6dc6
...@@ -117,7 +117,7 @@ void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle) ...@@ -117,7 +117,7 @@ void *consistent_alloc(gfp_t gfp, size_t size, dma_addr_t *dma_handle)
ret = (void *)va; ret = (void *)va;
/* This gives us the real physical address of the first page. */ /* This gives us the real physical address of the first page. */
*dma_handle = pa = virt_to_bus((void *)vaddr); *dma_handle = pa = __virt_to_phys(vaddr);
#endif #endif
/* /*
......
arch/microblaze/mm/init.c
View file @ b42e6dc6
...@@ -369,7 +369,7 @@ asmlinkage void __init mmu_init(void) ...@@ -369,7 +369,7 @@ asmlinkage void __init mmu_init(void)
if (initrd_start) { if (initrd_start) {
unsigned long size; unsigned long size;
size = initrd_end - initrd_start; size = initrd_end - initrd_start;
memblock_reserve(virt_to_phys(initrd_start), size); memblock_reserve(__virt_to_phys(initrd_start), size);
} }
#endif /* CONFIG_BLK_DEV_INITRD */ #endif /* CONFIG_BLK_DEV_INITRD */
......
arch/microblaze/mm/pgtable.c
View file @ b42e6dc6
...@@ -69,10 +69,11 @@ static void __iomem *__ioremap(phys_addr_t addr, unsigned long size, ...@@ -69,10 +69,11 @@ static void __iomem *__ioremap(phys_addr_t addr, unsigned long size,
* *
* However, allow remap of rootfs: TBD * However, allow remap of rootfs: TBD
*/ */
if (mem_init_done && if (mem_init_done &&
p >= memory_start && p < virt_to_phys(high_memory) && p >= memory_start && p < virt_to_phys(high_memory) &&
!(p >= virt_to_phys((unsigned long)&__bss_stop) && !(p >= __virt_to_phys((phys_addr_t)__bss_stop) &&
p < virt_to_phys((unsigned long)__bss_stop))) { p < __virt_to_phys((phys_addr_t)__bss_stop))) {
pr_warn("__ioremap(): phys addr "PTE_FMT" is RAM lr %pf\n", pr_warn("__ioremap(): phys addr "PTE_FMT" is RAM lr %pf\n",
(unsigned long)p, __builtin_return_address(0)); (unsigned long)p, __builtin_return_address(0));
return NULL; return NULL;
......
arch/microblaze/platform/Makefile deleted 100644 → 0
View file @ 9e897e13
#
# Makefile for arch/microblaze/platform directory
#
#obj-$(CONFIG_PLATFORM_GENERIC) += generic/
obj-y += platform.o
arch/microblaze/platform/generic/Kconfig.auto deleted 100644 → 0
View file @ 9e897e13
#
# (C) Copyright 2007 Michal Simek
#
# Michal SIMEK <monstr@monstr.eu>
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
# Definitions for MICROBLAZE0
comment "Definitions for MICROBLAZE0"
config KERNEL_BASE_ADDR
hex "Physical address where Linux Kernel is"
default "0x90000000"
help
BASE Address for kernel
config XILINX_MICROBLAZE0_FAMILY
string "Targeted FPGA family"
default "virtex5"
config XILINX_MICROBLAZE0_USE_MSR_INSTR
int "USE_MSR_INSTR range (0:1)"
default 0
config XILINX_MICROBLAZE0_USE_PCMP_INSTR
int "USE_PCMP_INSTR range (0:1)"
default 0
config XILINX_MICROBLAZE0_USE_BARREL
int "USE_BARREL range (0:1)"
default 0
config XILINX_MICROBLAZE0_USE_DIV
int "USE_DIV range (0:1)"
default 0
config XILINX_MICROBLAZE0_USE_HW_MUL
int "USE_HW_MUL values (0=NONE, 1=MUL32, 2=MUL64)"
default 0
config XILINX_MICROBLAZE0_USE_FPU
int "USE_FPU values (0=NONE, 1=BASIC, 2=EXTENDED)"
default 0
config XILINX_MICROBLAZE0_HW_VER
string "Core version number"
default 7.10.d
arch/microblaze/platform/generic/Makefile deleted 100644 → 0
View file @ 9e897e13
#
# Empty Makefile to keep make clean happy
#
arch/microblaze/platform/generic/system.dts deleted 100644 → 0
View file @ 9e897e13
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