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Commit bdb5d8ec authored by Alexander Lobakin's avatar Alexander Lobakin Committed by David S. Miller
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qed, qede, qedf: convert link mode from u32 to ETHTOOL_LINK_MODE 

Currently qed driver already ran out of 32 bits to store link modes,
and this doesn't allow to add and support more speeds.
Convert custom link mode to generic Ethtool bitmap and definitions
(convenient Phylink shorthands are used for elegance and readability).
This allowed us to drop all conversions/mappings between the driver
and Ethtool.

This involves changes in qede and qedf as well, as they used definitions
from shared "qed_if.h".
Suggested-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarAlexander Lobakin <alobakin@marvell.com>
Signed-off-by: default avatarIgor Russkikh <irusskikh@marvell.com>
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent e812916d
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Showing with 268 additions and 345 deletions
drivers/net/ethernet/qlogic/qed/qed_main.c
View file @ bdb5d8ec
...@@ -24,6 +24,7 @@ ...@@ -24,6 +24,7 @@
#include <linux/qed/qed_ll2_if.h> #include <linux/qed/qed_ll2_if.h>
#include <net/devlink.h> #include <net/devlink.h>
#include <linux/aer.h> #include <linux/aer.h>
#include <linux/phylink.h>
#include "qed.h" #include "qed.h"
#include "qed_sriov.h" #include "qed_sriov.h"
...@@ -1456,10 +1457,11 @@ static bool qed_can_link_change(struct qed_dev *cdev) ...@@ -1456,10 +1457,11 @@ static bool qed_can_link_change(struct qed_dev *cdev)
static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params) static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params)
{ {
struct qed_hwfn *hwfn; __ETHTOOL_DECLARE_LINK_MODE_MASK(sup_caps);
struct qed_mcp_link_params *link_params; struct qed_mcp_link_params *link_params;
struct qed_hwfn *hwfn;
struct qed_ptt *ptt; struct qed_ptt *ptt;
u32 sup_caps; u32 as;
int rc; int rc;
if (!cdev) if (!cdev)
...@@ -1482,57 +1484,79 @@ static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params) ...@@ -1482,57 +1484,79 @@ static int qed_set_link(struct qed_dev *cdev, struct qed_link_params *params)
return -EBUSY; return -EBUSY;
link_params = qed_mcp_get_link_params(hwfn); link_params = qed_mcp_get_link_params(hwfn);
if (!link_params)
return -ENODATA;
if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG) if (params->override_flags & QED_LINK_OVERRIDE_SPEED_AUTONEG)
link_params->speed.autoneg = params->autoneg; link_params->speed.autoneg = params->autoneg;
if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) { if (params->override_flags & QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS) {
link_params->speed.advertised_speeds = 0; as = 0;
sup_caps = QED_LM_1000baseT_Full_BIT |
QED_LM_1000baseKX_Full_BIT | phylink_zero(sup_caps);
QED_LM_1000baseX_Full_BIT; phylink_set(sup_caps, 1000baseT_Full);
if (params->adv_speeds & sup_caps) phylink_set(sup_caps, 1000baseKX_Full);
link_params->speed.advertised_speeds |= phylink_set(sup_caps, 1000baseX_Full);
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
sup_caps = QED_LM_10000baseT_Full_BIT | if (linkmode_intersects(params->adv_speeds, sup_caps))
QED_LM_10000baseKR_Full_BIT | as |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G;
QED_LM_10000baseKX4_Full_BIT |
QED_LM_10000baseR_FEC_BIT | phylink_zero(sup_caps);
QED_LM_10000baseCR_Full_BIT | phylink_set(sup_caps, 10000baseT_Full);
QED_LM_10000baseSR_Full_BIT | phylink_set(sup_caps, 10000baseKR_Full);
QED_LM_10000baseLR_Full_BIT | phylink_set(sup_caps, 10000baseKX4_Full);
QED_LM_10000baseLRM_Full_BIT; phylink_set(sup_caps, 10000baseR_FEC);
if (params->adv_speeds & sup_caps) phylink_set(sup_caps, 10000baseCR_Full);
link_params->speed.advertised_speeds |= phylink_set(sup_caps, 10000baseSR_Full);
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G; phylink_set(sup_caps, 10000baseLR_Full);
if (params->adv_speeds & QED_LM_20000baseKR2_Full_BIT) phylink_set(sup_caps, 10000baseLRM_Full);
link_params->speed.advertised_speeds |=
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G; if (linkmode_intersects(params->adv_speeds, sup_caps))
sup_caps = QED_LM_25000baseKR_Full_BIT | as |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G;
QED_LM_25000baseCR_Full_BIT |
QED_LM_25000baseSR_Full_BIT; phylink_zero(sup_caps);
if (params->adv_speeds & sup_caps) phylink_set(sup_caps, 20000baseKR2_Full);
link_params->speed.advertised_speeds |=
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G; if (linkmode_intersects(params->adv_speeds, sup_caps))
sup_caps = QED_LM_40000baseLR4_Full_BIT | as |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G;
QED_LM_40000baseKR4_Full_BIT |
QED_LM_40000baseCR4_Full_BIT | phylink_zero(sup_caps);
QED_LM_40000baseSR4_Full_BIT; phylink_set(sup_caps, 25000baseKR_Full);
if (params->adv_speeds & sup_caps) phylink_set(sup_caps, 25000baseCR_Full);
link_params->speed.advertised_speeds |= phylink_set(sup_caps, 25000baseSR_Full);
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
sup_caps = QED_LM_50000baseKR2_Full_BIT | if (linkmode_intersects(params->adv_speeds, sup_caps))
QED_LM_50000baseCR2_Full_BIT | as |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G;
QED_LM_50000baseSR2_Full_BIT;
if (params->adv_speeds & sup_caps) phylink_zero(sup_caps);
link_params->speed.advertised_speeds |= phylink_set(sup_caps, 40000baseLR4_Full);
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G; phylink_set(sup_caps, 40000baseKR4_Full);
sup_caps = QED_LM_100000baseKR4_Full_BIT | phylink_set(sup_caps, 40000baseCR4_Full);
QED_LM_100000baseSR4_Full_BIT | phylink_set(sup_caps, 40000baseSR4_Full);
QED_LM_100000baseCR4_Full_BIT |
QED_LM_100000baseLR4_ER4_Full_BIT; if (linkmode_intersects(params->adv_speeds, sup_caps))
if (params->adv_speeds & sup_caps) as |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G;
link_params->speed.advertised_speeds |=
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G; phylink_zero(sup_caps);
phylink_set(sup_caps, 50000baseKR2_Full);
phylink_set(sup_caps, 50000baseCR2_Full);
phylink_set(sup_caps, 50000baseSR2_Full);
if (linkmode_intersects(params->adv_speeds, sup_caps))
as |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G;
phylink_zero(sup_caps);
phylink_set(sup_caps, 100000baseKR4_Full);
phylink_set(sup_caps, 100000baseSR4_Full);
phylink_set(sup_caps, 100000baseCR4_Full);
phylink_set(sup_caps, 100000baseLR4_ER4_Full);
if (linkmode_intersects(params->adv_speeds, sup_caps))
as |= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G;
link_params->speed.advertised_speeds = as;
} }
if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED) if (params->override_flags & QED_LINK_OVERRIDE_SPEED_FORCED_SPEED)
link_params->speed.forced_speed = params->forced_speed; link_params->speed.forced_speed = params->forced_speed;
if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) { if (params->override_flags & QED_LINK_OVERRIDE_PAUSE_CONFIG) {
...@@ -1644,7 +1668,7 @@ static int qed_get_link_data(struct qed_hwfn *hwfn, ...@@ -1644,7 +1668,7 @@ static int qed_get_link_data(struct qed_hwfn *hwfn,
static void qed_fill_link_capability(struct qed_hwfn *hwfn, static void qed_fill_link_capability(struct qed_hwfn *hwfn,
struct qed_ptt *ptt, u32 capability, struct qed_ptt *ptt, u32 capability,
u32 *if_capability) unsigned long *if_caps)
{ {
u32 media_type, tcvr_state, tcvr_type; u32 media_type, tcvr_state, tcvr_type;
u32 speed_mask, board_cfg; u32 speed_mask, board_cfg;
...@@ -1667,113 +1691,117 @@ static void qed_fill_link_capability(struct qed_hwfn *hwfn, ...@@ -1667,113 +1691,117 @@ static void qed_fill_link_capability(struct qed_hwfn *hwfn,
switch (media_type) { switch (media_type) {
case MEDIA_DA_TWINAX: case MEDIA_DA_TWINAX:
*if_capability |= QED_LM_FIBRE_BIT; phylink_set(if_caps, FIBRE);
if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G) if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
*if_capability |= QED_LM_20000baseKR2_Full_BIT; phylink_set(if_caps, 20000baseKR2_Full);
/* For DAC media multiple speed capabilities are supported*/ /* For DAC media multiple speed capabilities are supported*/
capability = capability & speed_mask; capability = capability & speed_mask;
if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
*if_capability |= QED_LM_1000baseKX_Full_BIT; phylink_set(if_caps, 1000baseKX_Full);
if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
*if_capability |= QED_LM_10000baseCR_Full_BIT; phylink_set(if_caps, 10000baseCR_Full);
if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
*if_capability |= QED_LM_40000baseCR4_Full_BIT; phylink_set(if_caps, 40000baseCR4_Full);
if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
*if_capability |= QED_LM_25000baseCR_Full_BIT; phylink_set(if_caps, 25000baseCR_Full);
if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
*if_capability |= QED_LM_50000baseCR2_Full_BIT; phylink_set(if_caps, 50000baseCR2_Full);
if (capability & if (capability &
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
*if_capability |= QED_LM_100000baseCR4_Full_BIT; phylink_set(if_caps, 100000baseCR4_Full);
break; break;
case MEDIA_BASE_T: case MEDIA_BASE_T:
*if_capability |= QED_LM_TP_BIT; phylink_set(if_caps, TP);
if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_EXT_PHY) { if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_EXT_PHY) {
if (capability & if (capability &
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) { NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
*if_capability |= QED_LM_1000baseT_Full_BIT; phylink_set(if_caps, 1000baseT_Full);
}
if (capability & if (capability &
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) { NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
*if_capability |= QED_LM_10000baseT_Full_BIT; phylink_set(if_caps, 10000baseT_Full);
}
} }
if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_MODULE) { if (board_cfg & NVM_CFG1_PORT_PORT_TYPE_MODULE) {
*if_capability |= QED_LM_FIBRE_BIT; phylink_set(if_caps, FIBRE);
if (tcvr_type == ETH_TRANSCEIVER_TYPE_1000BASET) if (tcvr_type == ETH_TRANSCEIVER_TYPE_1000BASET)
*if_capability |= QED_LM_1000baseT_Full_BIT; phylink_set(if_caps, 1000baseT_Full);
if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_BASET) if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_BASET)
*if_capability |= QED_LM_10000baseT_Full_BIT; phylink_set(if_caps, 10000baseT_Full);
} }
break; break;
case MEDIA_SFP_1G_FIBER: case MEDIA_SFP_1G_FIBER:
case MEDIA_SFPP_10G_FIBER: case MEDIA_SFPP_10G_FIBER:
case MEDIA_XFP_FIBER: case MEDIA_XFP_FIBER:
case MEDIA_MODULE_FIBER: case MEDIA_MODULE_FIBER:
*if_capability |= QED_LM_FIBRE_BIT; phylink_set(if_caps, FIBRE);
if (capability &
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) { if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) {
if ((tcvr_type == ETH_TRANSCEIVER_TYPE_1G_LX) || if ((tcvr_type == ETH_TRANSCEIVER_TYPE_1G_LX) ||
(tcvr_type == ETH_TRANSCEIVER_TYPE_1G_SX)) (tcvr_type == ETH_TRANSCEIVER_TYPE_1G_SX))
*if_capability |= QED_LM_1000baseKX_Full_BIT; phylink_set(if_caps, 1000baseKX_Full);
} }
if (capability &
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) { if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) {
if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_SR) if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_SR)
*if_capability |= QED_LM_10000baseSR_Full_BIT; phylink_set(if_caps, 10000baseSR_Full);
if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_LR) if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_LR)
*if_capability |= QED_LM_10000baseLR_Full_BIT; phylink_set(if_caps, 10000baseLR_Full);
if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_LRM) if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_LRM)
*if_capability |= QED_LM_10000baseLRM_Full_BIT; phylink_set(if_caps, 10000baseLRM_Full);
if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_ER) if (tcvr_type == ETH_TRANSCEIVER_TYPE_10G_ER)
*if_capability |= QED_LM_10000baseR_FEC_BIT; phylink_set(if_caps, 10000baseR_FEC);
} }
if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G) if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
*if_capability |= QED_LM_20000baseKR2_Full_BIT; phylink_set(if_caps, 20000baseKR2_Full);
if (capability &
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) { if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) {
if (tcvr_type == ETH_TRANSCEIVER_TYPE_25G_SR) if (tcvr_type == ETH_TRANSCEIVER_TYPE_25G_SR)
*if_capability |= QED_LM_25000baseSR_Full_BIT; phylink_set(if_caps, 25000baseSR_Full);
} }
if (capability &
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) { if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G) {
if (tcvr_type == ETH_TRANSCEIVER_TYPE_40G_LR4) if (tcvr_type == ETH_TRANSCEIVER_TYPE_40G_LR4)
*if_capability |= QED_LM_40000baseLR4_Full_BIT; phylink_set(if_caps, 40000baseLR4_Full);
if (tcvr_type == ETH_TRANSCEIVER_TYPE_40G_SR4) if (tcvr_type == ETH_TRANSCEIVER_TYPE_40G_SR4)
*if_capability |= QED_LM_40000baseSR4_Full_BIT; phylink_set(if_caps, 40000baseSR4_Full);
} }
if (capability &
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G) if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
*if_capability |= QED_LM_50000baseKR2_Full_BIT; phylink_set(if_caps, 50000baseKR2_Full);
if (capability & if (capability &
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) { NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) {
if (tcvr_type == ETH_TRANSCEIVER_TYPE_100G_SR4) if (tcvr_type == ETH_TRANSCEIVER_TYPE_100G_SR4)
*if_capability |= QED_LM_100000baseSR4_Full_BIT; phylink_set(if_caps, 100000baseSR4_Full);
} }
break; break;
case MEDIA_KR: case MEDIA_KR:
*if_capability |= QED_LM_Backplane_BIT; phylink_set(if_caps, Backplane);
if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G) if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G)
*if_capability |= QED_LM_20000baseKR2_Full_BIT; phylink_set(if_caps, 20000baseKR2_Full);
if (capability & if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G)
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G) phylink_set(if_caps, 1000baseKX_Full);
*if_capability |= QED_LM_1000baseKX_Full_BIT; if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G)
if (capability & phylink_set(if_caps, 10000baseKR_Full);
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G) if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G)
*if_capability |= QED_LM_10000baseKR_Full_BIT; phylink_set(if_caps, 25000baseKR_Full);
if (capability & if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G) phylink_set(if_caps, 40000baseKR4_Full);
*if_capability |= QED_LM_25000baseKR_Full_BIT; if (capability & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
if (capability & phylink_set(if_caps, 50000baseKR2_Full);
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G)
*if_capability |= QED_LM_40000baseKR4_Full_BIT;
if (capability &
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G)
*if_capability |= QED_LM_50000baseKR2_Full_BIT;
if (capability & if (capability &
NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G) NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G)
*if_capability |= QED_LM_100000baseKR4_Full_BIT; phylink_set(if_caps, 100000baseKR4_Full);
break; break;
case MEDIA_UNSPECIFIED: case MEDIA_UNSPECIFIED:
case MEDIA_NOT_PRESENT: case MEDIA_NOT_PRESENT:
...@@ -1806,26 +1834,27 @@ static void qed_fill_link(struct qed_hwfn *hwfn, ...@@ -1806,26 +1834,27 @@ static void qed_fill_link(struct qed_hwfn *hwfn,
/* TODO - at the moment assume supported and advertised speed equal */ /* TODO - at the moment assume supported and advertised speed equal */
if (link_caps.default_speed_autoneg) if (link_caps.default_speed_autoneg)
if_link->supported_caps |= QED_LM_Autoneg_BIT; phylink_set(if_link->supported_caps, Autoneg);
if (params.pause.autoneg || if (params.pause.autoneg ||
(params.pause.forced_rx && params.pause.forced_tx)) (params.pause.forced_rx && params.pause.forced_tx))
if_link->supported_caps |= QED_LM_Asym_Pause_BIT; phylink_set(if_link->supported_caps, Asym_Pause);
if (params.pause.autoneg || params.pause.forced_rx || if (params.pause.autoneg || params.pause.forced_rx ||
params.pause.forced_tx) params.pause.forced_tx)
if_link->supported_caps |= QED_LM_Pause_BIT; phylink_set(if_link->supported_caps, Pause);
linkmode_copy(if_link->advertised_caps, if_link->supported_caps);
if_link->advertised_caps = if_link->supported_caps;
if (params.speed.autoneg) if (params.speed.autoneg)
if_link->advertised_caps |= QED_LM_Autoneg_BIT; phylink_set(if_link->advertised_caps, Autoneg);
else else
if_link->advertised_caps &= ~QED_LM_Autoneg_BIT; phylink_clear(if_link->advertised_caps, Autoneg);
/* Fill link advertised capability*/ /* Fill link advertised capability*/
qed_fill_link_capability(hwfn, ptt, params.speed.advertised_speeds, qed_fill_link_capability(hwfn, ptt, params.speed.advertised_speeds,
&if_link->advertised_caps); if_link->advertised_caps);
/* Fill link supported capability*/ /* Fill link supported capability*/
qed_fill_link_capability(hwfn, ptt, link_caps.speed_capabilities, qed_fill_link_capability(hwfn, ptt, link_caps.speed_capabilities,
&if_link->supported_caps); if_link->supported_caps);
if (link.link_up) if (link.link_up)
if_link->speed = link.speed; if_link->speed = link.speed;
...@@ -1845,30 +1874,29 @@ static void qed_fill_link(struct qed_hwfn *hwfn, ...@@ -1845,30 +1874,29 @@ static void qed_fill_link(struct qed_hwfn *hwfn,
if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE; if_link->pause_config |= QED_LINK_PAUSE_TX_ENABLE;
/* Link partner capabilities */ /* Link partner capabilities */
if (link.partner_adv_speed &
QED_LINK_PARTNER_SPEED_1G_FD) if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_1G_FD)
if_link->lp_caps |= QED_LM_1000baseT_Full_BIT; phylink_set(if_link->lp_caps, 1000baseT_Full);
if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G) if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_10G)
if_link->lp_caps |= QED_LM_10000baseKR_Full_BIT; phylink_set(if_link->lp_caps, 10000baseKR_Full);
if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_20G) if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_20G)
if_link->lp_caps |= QED_LM_20000baseKR2_Full_BIT; phylink_set(if_link->lp_caps, 20000baseKR2_Full);
if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G) if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_25G)
if_link->lp_caps |= QED_LM_25000baseKR_Full_BIT; phylink_set(if_link->lp_caps, 25000baseKR_Full);
if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G) if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_40G)
if_link->lp_caps |= QED_LM_40000baseLR4_Full_BIT; phylink_set(if_link->lp_caps, 40000baseLR4_Full);
if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G) if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_50G)
if_link->lp_caps |= QED_LM_50000baseKR2_Full_BIT; phylink_set(if_link->lp_caps, 50000baseKR2_Full);
if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G) if (link.partner_adv_speed & QED_LINK_PARTNER_SPEED_100G)
if_link->lp_caps |= QED_LM_100000baseKR4_Full_BIT; phylink_set(if_link->lp_caps, 100000baseKR4_Full);
if (link.an_complete) if (link.an_complete)
if_link->lp_caps |= QED_LM_Autoneg_BIT; phylink_set(if_link->lp_caps, Autoneg);
if (link.partner_adv_pause) if (link.partner_adv_pause)
if_link->lp_caps |= QED_LM_Pause_BIT; phylink_set(if_link->lp_caps, Pause);
if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE || if (link.partner_adv_pause == QED_LINK_PARTNER_ASYMMETRIC_PAUSE ||
link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE) link.partner_adv_pause == QED_LINK_PARTNER_BOTH_PAUSE)
if_link->lp_caps |= QED_LM_Asym_Pause_BIT; phylink_set(if_link->lp_caps, Asym_Pause);
if (link_caps.default_eee == QED_MCP_EEE_UNSUPPORTED) { if (link_caps.default_eee == QED_MCP_EEE_UNSUPPORTED) {
if_link->eee_supported = false; if_link->eee_supported = false;
......
drivers/net/ethernet/qlogic/qede/qede_ethtool.c
View file @ bdb5d8ec
...@@ -13,6 +13,8 @@ ...@@ -13,6 +13,8 @@
#include <linux/pci.h> #include <linux/pci.h>
#include <linux/capability.h> #include <linux/capability.h>
#include <linux/vmalloc.h> #include <linux/vmalloc.h>
#include <linux/phylink.h>
#include "qede.h" #include "qede.h"
#include "qede_ptp.h" #include "qede_ptp.h"
...@@ -418,76 +420,10 @@ static int qede_set_priv_flags(struct net_device *dev, u32 flags) ...@@ -418,76 +420,10 @@ static int qede_set_priv_flags(struct net_device *dev, u32 flags)
return 0; return 0;
} }
struct qede_link_mode_mapping {
u32 qed_link_mode;
u32 ethtool_link_mode;
};
static const struct qede_link_mode_mapping qed_lm_map[] = {
{QED_LM_FIBRE_BIT, ETHTOOL_LINK_MODE_FIBRE_BIT},
{QED_LM_Autoneg_BIT, ETHTOOL_LINK_MODE_Autoneg_BIT},
{QED_LM_Asym_Pause_BIT, ETHTOOL_LINK_MODE_Asym_Pause_BIT},
{QED_LM_Pause_BIT, ETHTOOL_LINK_MODE_Pause_BIT},
{QED_LM_1000baseT_Full_BIT, ETHTOOL_LINK_MODE_1000baseT_Full_BIT},
{QED_LM_10000baseT_Full_BIT, ETHTOOL_LINK_MODE_10000baseT_Full_BIT},
{QED_LM_TP_BIT, ETHTOOL_LINK_MODE_TP_BIT},
{QED_LM_Backplane_BIT, ETHTOOL_LINK_MODE_Backplane_BIT},
{QED_LM_1000baseKX_Full_BIT, ETHTOOL_LINK_MODE_1000baseKX_Full_BIT},
{QED_LM_10000baseKX4_Full_BIT, ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT},
{QED_LM_10000baseKR_Full_BIT, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT},
{QED_LM_10000baseKR_Full_BIT, ETHTOOL_LINK_MODE_10000baseKR_Full_BIT},
{QED_LM_10000baseR_FEC_BIT, ETHTOOL_LINK_MODE_10000baseR_FEC_BIT},
{QED_LM_20000baseKR2_Full_BIT, ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT},
{QED_LM_40000baseKR4_Full_BIT, ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT},
{QED_LM_40000baseCR4_Full_BIT, ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT},
{QED_LM_40000baseSR4_Full_BIT, ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT},
{QED_LM_40000baseLR4_Full_BIT, ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT},
{QED_LM_25000baseCR_Full_BIT, ETHTOOL_LINK_MODE_25000baseCR_Full_BIT},
{QED_LM_25000baseKR_Full_BIT, ETHTOOL_LINK_MODE_25000baseKR_Full_BIT},
{QED_LM_25000baseSR_Full_BIT, ETHTOOL_LINK_MODE_25000baseSR_Full_BIT},
{QED_LM_50000baseCR2_Full_BIT, ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT},
{QED_LM_50000baseKR2_Full_BIT, ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT},
{QED_LM_100000baseKR4_Full_BIT,
ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT},
{QED_LM_100000baseSR4_Full_BIT,
ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT},
{QED_LM_100000baseCR4_Full_BIT,
ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT},
{QED_LM_100000baseLR4_ER4_Full_BIT,
ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT},
{QED_LM_50000baseSR2_Full_BIT, ETHTOOL_LINK_MODE_50000baseSR2_Full_BIT},
{QED_LM_1000baseX_Full_BIT, ETHTOOL_LINK_MODE_1000baseX_Full_BIT},
{QED_LM_10000baseCR_Full_BIT, ETHTOOL_LINK_MODE_10000baseCR_Full_BIT},
{QED_LM_10000baseSR_Full_BIT, ETHTOOL_LINK_MODE_10000baseSR_Full_BIT},
{QED_LM_10000baseLR_Full_BIT, ETHTOOL_LINK_MODE_10000baseLR_Full_BIT},
{QED_LM_10000baseLRM_Full_BIT, ETHTOOL_LINK_MODE_10000baseLRM_Full_BIT},
};
#define QEDE_DRV_TO_ETHTOOL_CAPS(caps, lk_ksettings, name) \
{ \
int i; \
\
for (i = 0; i < ARRAY_SIZE(qed_lm_map); i++) { \
if ((caps) & (qed_lm_map[i].qed_link_mode)) \
__set_bit(qed_lm_map[i].ethtool_link_mode,\
lk_ksettings->link_modes.name); \
} \
}
#define QEDE_ETHTOOL_TO_DRV_CAPS(caps, lk_ksettings, name) \
{ \
int i; \
\
for (i = 0; i < ARRAY_SIZE(qed_lm_map); i++) { \
if (test_bit(qed_lm_map[i].ethtool_link_mode, \
lk_ksettings->link_modes.name)) \
caps |= qed_lm_map[i].qed_link_mode; \
} \
}
static int qede_get_link_ksettings(struct net_device *dev, static int qede_get_link_ksettings(struct net_device *dev,
struct ethtool_link_ksettings *cmd) struct ethtool_link_ksettings *cmd)
{ {
typeof(cmd->link_modes) *link_modes = &cmd->link_modes;
struct ethtool_link_settings *base = &cmd->base; struct ethtool_link_settings *base = &cmd->base;
struct qede_dev *edev = netdev_priv(dev); struct qede_dev *edev = netdev_priv(dev);
struct qed_link_output current_link; struct qed_link_output current_link;
...@@ -497,14 +433,9 @@ static int qede_get_link_ksettings(struct net_device *dev, ...@@ -497,14 +433,9 @@ static int qede_get_link_ksettings(struct net_device *dev,
memset(&current_link, 0, sizeof(current_link)); memset(&current_link, 0, sizeof(current_link));
edev->ops->common->get_link(edev->cdev, &current_link); edev->ops->common->get_link(edev->cdev, &current_link);
ethtool_link_ksettings_zero_link_mode(cmd, supported); linkmode_copy(link_modes->supported, current_link.supported_caps);
QEDE_DRV_TO_ETHTOOL_CAPS(current_link.supported_caps, cmd, supported) linkmode_copy(link_modes->advertising, current_link.advertised_caps);
linkmode_copy(link_modes->lp_advertising, current_link.lp_caps);
ethtool_link_ksettings_zero_link_mode(cmd, advertising);
QEDE_DRV_TO_ETHTOOL_CAPS(current_link.advertised_caps, cmd, advertising)
ethtool_link_ksettings_zero_link_mode(cmd, lp_advertising);
QEDE_DRV_TO_ETHTOOL_CAPS(current_link.lp_caps, cmd, lp_advertising)
if ((edev->state == QEDE_STATE_OPEN) && (current_link.link_up)) { if ((edev->state == QEDE_STATE_OPEN) && (current_link.link_up)) {
base->speed = current_link.speed; base->speed = current_link.speed;
...@@ -527,10 +458,10 @@ static int qede_set_link_ksettings(struct net_device *dev, ...@@ -527,10 +458,10 @@ static int qede_set_link_ksettings(struct net_device *dev,
const struct ethtool_link_ksettings *cmd) const struct ethtool_link_ksettings *cmd)
{ {
const struct ethtool_link_settings *base = &cmd->base; const struct ethtool_link_settings *base = &cmd->base;
__ETHTOOL_DECLARE_LINK_MODE_MASK(sup_caps);
struct qede_dev *edev = netdev_priv(dev); struct qede_dev *edev = netdev_priv(dev);
struct qed_link_output current_link; struct qed_link_output current_link;
struct qed_link_params params; struct qed_link_params params;
u32 sup_caps;
if (!edev->ops || !edev->ops->common->can_link_change(edev->cdev)) { if (!edev->ops || !edev->ops->common->can_link_change(edev->cdev)) {
DP_INFO(edev, "Link settings are not allowed to be changed\n"); DP_INFO(edev, "Link settings are not allowed to be changed\n");
...@@ -542,105 +473,79 @@ static int qede_set_link_ksettings(struct net_device *dev, ...@@ -542,105 +473,79 @@ static int qede_set_link_ksettings(struct net_device *dev,
params.override_flags |= QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS; params.override_flags |= QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS;
params.override_flags |= QED_LINK_OVERRIDE_SPEED_AUTONEG; params.override_flags |= QED_LINK_OVERRIDE_SPEED_AUTONEG;
if (base->autoneg == AUTONEG_ENABLE) { if (base->autoneg == AUTONEG_ENABLE) {
if (!(current_link.supported_caps & QED_LM_Autoneg_BIT)) { if (!phylink_test(current_link.supported_caps, Autoneg)) {
DP_INFO(edev, "Auto negotiation is not supported\n"); DP_INFO(edev, "Auto negotiation is not supported\n");
return -EOPNOTSUPP; return -EOPNOTSUPP;
} }
params.autoneg = true; params.autoneg = true;
params.forced_speed = 0; params.forced_speed = 0;
QEDE_ETHTOOL_TO_DRV_CAPS(params.adv_speeds, cmd, advertising)
linkmode_copy(params.adv_speeds, cmd->link_modes.advertising);
} else { /* forced speed */ } else { /* forced speed */
params.override_flags |= QED_LINK_OVERRIDE_SPEED_FORCED_SPEED; params.override_flags |= QED_LINK_OVERRIDE_SPEED_FORCED_SPEED;
params.autoneg = false; params.autoneg = false;
params.forced_speed = base->speed; params.forced_speed = base->speed;
phylink_zero(sup_caps);
switch (base->speed) { switch (base->speed) {
case SPEED_1000: case SPEED_1000:
sup_caps = QED_LM_1000baseT_Full_BIT | phylink_set(sup_caps, 1000baseT_Full);
QED_LM_1000baseKX_Full_BIT | phylink_set(sup_caps, 1000baseKX_Full);
QED_LM_1000baseX_Full_BIT; phylink_set(sup_caps, 1000baseX_Full);
if (!(current_link.supported_caps & sup_caps)) {
DP_INFO(edev, "1G speed not supported\n");
return -EINVAL;
}
params.adv_speeds = current_link.supported_caps &
sup_caps;
break; break;
case SPEED_10000: case SPEED_10000:
sup_caps = QED_LM_10000baseT_Full_BIT | phylink_set(sup_caps, 10000baseT_Full);
QED_LM_10000baseKR_Full_BIT | phylink_set(sup_caps, 10000baseKR_Full);
QED_LM_10000baseKX4_Full_BIT | phylink_set(sup_caps, 10000baseKX4_Full);
QED_LM_10000baseR_FEC_BIT | phylink_set(sup_caps, 10000baseR_FEC);
QED_LM_10000baseCR_Full_BIT | phylink_set(sup_caps, 10000baseCR_Full);
QED_LM_10000baseSR_Full_BIT | phylink_set(sup_caps, 10000baseSR_Full);
QED_LM_10000baseLR_Full_BIT | phylink_set(sup_caps, 10000baseLR_Full);
QED_LM_10000baseLRM_Full_BIT; phylink_set(sup_caps, 10000baseLRM_Full);
if (!(current_link.supported_caps & sup_caps)) {
DP_INFO(edev, "10G speed not supported\n");
return -EINVAL;
}
params.adv_speeds = current_link.supported_caps &
sup_caps;
break; break;
case SPEED_20000: case SPEED_20000:
if (!(current_link.supported_caps & phylink_set(sup_caps, 20000baseKR2_Full);
QED_LM_20000baseKR2_Full_BIT)) {
DP_INFO(edev, "20G speed not supported\n");
return -EINVAL;
}
params.adv_speeds = QED_LM_20000baseKR2_Full_BIT;
break; break;
case SPEED_25000: case SPEED_25000:
sup_caps = QED_LM_25000baseKR_Full_BIT | phylink_set(sup_caps, 25000baseKR_Full);
QED_LM_25000baseCR_Full_BIT | phylink_set(sup_caps, 25000baseCR_Full);
QED_LM_25000baseSR_Full_BIT; phylink_set(sup_caps, 25000baseSR_Full);
if (!(current_link.supported_caps & sup_caps)) {
DP_INFO(edev, "25G speed not supported\n");
return -EINVAL;
}
params.adv_speeds = current_link.supported_caps &
sup_caps;
break; break;
case SPEED_40000: case SPEED_40000:
sup_caps = QED_LM_40000baseLR4_Full_BIT | phylink_set(sup_caps, 40000baseLR4_Full);
QED_LM_40000baseKR4_Full_BIT | phylink_set(sup_caps, 40000baseKR4_Full);
QED_LM_40000baseCR4_Full_BIT | phylink_set(sup_caps, 40000baseCR4_Full);
QED_LM_40000baseSR4_Full_BIT; phylink_set(sup_caps, 40000baseSR4_Full);
if (!(current_link.supported_caps & sup_caps)) {
DP_INFO(edev, "40G speed not supported\n");
return -EINVAL;
}
params.adv_speeds = current_link.supported_caps &
sup_caps;
break; break;
case SPEED_50000: case SPEED_50000:
sup_caps = QED_LM_50000baseKR2_Full_BIT | phylink_set(sup_caps, 50000baseKR2_Full);
QED_LM_50000baseCR2_Full_BIT | phylink_set(sup_caps, 50000baseCR2_Full);
QED_LM_50000baseSR2_Full_BIT; phylink_set(sup_caps, 50000baseSR2_Full);
if (!(current_link.supported_caps & sup_caps)) {
DP_INFO(edev, "50G speed not supported\n");
return -EINVAL;
}
params.adv_speeds = current_link.supported_caps &
sup_caps;
break; break;
case SPEED_100000: case SPEED_100000:
sup_caps = QED_LM_100000baseKR4_Full_BIT | phylink_set(sup_caps, 100000baseKR4_Full);
QED_LM_100000baseSR4_Full_BIT | phylink_set(sup_caps, 100000baseSR4_Full);
QED_LM_100000baseCR4_Full_BIT | phylink_set(sup_caps, 100000baseCR4_Full);
QED_LM_100000baseLR4_ER4_Full_BIT; phylink_set(sup_caps, 100000baseLR4_ER4_Full);
if (!(current_link.supported_caps & sup_caps)) {
DP_INFO(edev, "100G speed not supported\n");
return -EINVAL;
}
params.adv_speeds = current_link.supported_caps &
sup_caps;
break; break;
default: default:
DP_INFO(edev, "Unsupported speed %u\n", base->speed); DP_INFO(edev, "Unsupported speed %u\n", base->speed);
return -EINVAL; return -EINVAL;
} }
if (!linkmode_intersects(current_link.supported_caps,
sup_caps)) {
DP_INFO(edev, "%uG speed not supported\n",
base->speed / 1000);
return -EINVAL;
}
linkmode_and(params.adv_speeds, current_link.supported_caps,
sup_caps);
} }
params.link_up = true; params.link_up = true;
...@@ -1006,13 +911,16 @@ static int qede_set_pauseparam(struct net_device *dev, ...@@ -1006,13 +911,16 @@ static int qede_set_pauseparam(struct net_device *dev,
memset(&params, 0, sizeof(params)); memset(&params, 0, sizeof(params));
params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG; params.override_flags |= QED_LINK_OVERRIDE_PAUSE_CONFIG;
if (epause->autoneg) { if (epause->autoneg) {
if (!(current_link.supported_caps & QED_LM_Autoneg_BIT)) { if (!phylink_test(current_link.supported_caps, Autoneg)) {
DP_INFO(edev, "autoneg not supported\n"); DP_INFO(edev, "autoneg not supported\n");
return -EINVAL; return -EINVAL;
} }
params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE; params.pause_config |= QED_LINK_PAUSE_AUTONEG_ENABLE;
} }
if (epause->rx_pause) if (epause->rx_pause)
params.pause_config |= QED_LINK_PAUSE_RX_ENABLE; params.pause_config |= QED_LINK_PAUSE_RX_ENABLE;
if (epause->tx_pause) if (epause->tx_pause)
......
drivers/scsi/qedf/qedf_main.c
View file @ bdb5d8ec
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/list.h> #include <linux/list.h>
#include <linux/kthread.h> #include <linux/kthread.h>
#include <linux/phylink.h>
#include <scsi/libfc.h> #include <scsi/libfc.h>
#include <scsi/scsi_host.h> #include <scsi/scsi_host.h>
#include <scsi/fc_frame.h> #include <scsi/fc_frame.h>
...@@ -440,6 +441,7 @@ static void qedf_link_recovery(struct work_struct *work) ...@@ -440,6 +441,7 @@ static void qedf_link_recovery(struct work_struct *work)
static void qedf_update_link_speed(struct qedf_ctx *qedf, static void qedf_update_link_speed(struct qedf_ctx *qedf,
struct qed_link_output *link) struct qed_link_output *link)
{ {
__ETHTOOL_DECLARE_LINK_MODE_MASK(sup_caps);
struct fc_lport *lport = qedf->lport; struct fc_lport *lport = qedf->lport;
lport->link_speed = FC_PORTSPEED_UNKNOWN; lport->link_speed = FC_PORTSPEED_UNKNOWN;
...@@ -474,40 +476,60 @@ static void qedf_update_link_speed(struct qedf_ctx *qedf, ...@@ -474,40 +476,60 @@ static void qedf_update_link_speed(struct qedf_ctx *qedf,
* Set supported link speed by querying the supported * Set supported link speed by querying the supported
* capabilities of the link. * capabilities of the link.
*/ */
if ((link->supported_caps & QED_LM_10000baseT_Full_BIT) ||
(link->supported_caps & QED_LM_10000baseKX4_Full_BIT) || phylink_zero(sup_caps);
(link->supported_caps & QED_LM_10000baseR_FEC_BIT) || phylink_set(sup_caps, 10000baseT_Full);
(link->supported_caps & QED_LM_10000baseCR_Full_BIT) || phylink_set(sup_caps, 10000baseKX4_Full);
(link->supported_caps & QED_LM_10000baseSR_Full_BIT) || phylink_set(sup_caps, 10000baseR_FEC);
(link->supported_caps & QED_LM_10000baseLR_Full_BIT) || phylink_set(sup_caps, 10000baseCR_Full);
(link->supported_caps & QED_LM_10000baseLRM_Full_BIT) || phylink_set(sup_caps, 10000baseSR_Full);
(link->supported_caps & QED_LM_10000baseKR_Full_BIT)) { phylink_set(sup_caps, 10000baseLR_Full);
phylink_set(sup_caps, 10000baseLRM_Full);
phylink_set(sup_caps, 10000baseKR_Full);
if (linkmode_intersects(link->supported_caps, sup_caps))
lport->link_supported_speeds |= FC_PORTSPEED_10GBIT; lport->link_supported_speeds |= FC_PORTSPEED_10GBIT;
}
if ((link->supported_caps & QED_LM_25000baseKR_Full_BIT) || phylink_zero(sup_caps);
(link->supported_caps & QED_LM_25000baseCR_Full_BIT) || phylink_set(sup_caps, 25000baseKR_Full);
(link->supported_caps & QED_LM_25000baseSR_Full_BIT)) { phylink_set(sup_caps, 25000baseCR_Full);
phylink_set(sup_caps, 25000baseSR_Full);
if (linkmode_intersects(link->supported_caps, sup_caps))
lport->link_supported_speeds |= FC_PORTSPEED_25GBIT; lport->link_supported_speeds |= FC_PORTSPEED_25GBIT;
}
if ((link->supported_caps & QED_LM_40000baseLR4_Full_BIT) || phylink_zero(sup_caps);
(link->supported_caps & QED_LM_40000baseKR4_Full_BIT) || phylink_set(sup_caps, 40000baseLR4_Full);
(link->supported_caps & QED_LM_40000baseCR4_Full_BIT) || phylink_set(sup_caps, 40000baseKR4_Full);
(link->supported_caps & QED_LM_40000baseSR4_Full_BIT)) { phylink_set(sup_caps, 40000baseCR4_Full);
phylink_set(sup_caps, 40000baseSR4_Full);
if (linkmode_intersects(link->supported_caps, sup_caps))
lport->link_supported_speeds |= FC_PORTSPEED_40GBIT; lport->link_supported_speeds |= FC_PORTSPEED_40GBIT;
}
if ((link->supported_caps & QED_LM_50000baseKR2_Full_BIT) || phylink_zero(sup_caps);
(link->supported_caps & QED_LM_50000baseCR2_Full_BIT) || phylink_set(sup_caps, 50000baseKR2_Full);
(link->supported_caps & QED_LM_50000baseSR2_Full_BIT)) { phylink_set(sup_caps, 50000baseCR2_Full);
phylink_set(sup_caps, 50000baseSR2_Full);
if (linkmode_intersects(link->supported_caps, sup_caps))
lport->link_supported_speeds |= FC_PORTSPEED_50GBIT; lport->link_supported_speeds |= FC_PORTSPEED_50GBIT;
}
if ((link->supported_caps & QED_LM_100000baseKR4_Full_BIT) || phylink_zero(sup_caps);
(link->supported_caps & QED_LM_100000baseSR4_Full_BIT) || phylink_set(sup_caps, 100000baseKR4_Full);
(link->supported_caps & QED_LM_100000baseCR4_Full_BIT) || phylink_set(sup_caps, 100000baseSR4_Full);
(link->supported_caps & QED_LM_100000baseLR4_ER4_Full_BIT)) { phylink_set(sup_caps, 100000baseCR4_Full);
phylink_set(sup_caps, 100000baseLR4_ER4_Full);
if (linkmode_intersects(link->supported_caps, sup_caps))
lport->link_supported_speeds |= FC_PORTSPEED_100GBIT; lport->link_supported_speeds |= FC_PORTSPEED_100GBIT;
}
if (link->supported_caps & QED_LM_20000baseKR2_Full_BIT) phylink_zero(sup_caps);
phylink_set(sup_caps, 20000baseKR2_Full);
if (linkmode_intersects(link->supported_caps, sup_caps))
lport->link_supported_speeds |= FC_PORTSPEED_20GBIT; lport->link_supported_speeds |= FC_PORTSPEED_20GBIT;
fc_host_supported_speeds(lport->host) = lport->link_supported_speeds; fc_host_supported_speeds(lport->host) = lport->link_supported_speeds;
} }
......
include/linux/qed/qed_if.h
View file @ bdb5d8ec
...@@ -661,42 +661,6 @@ enum qed_protocol { ...@@ -661,42 +661,6 @@ enum qed_protocol {
QED_PROTOCOL_FCOE, QED_PROTOCOL_FCOE,
}; };
enum qed_link_mode_bits {
QED_LM_FIBRE_BIT = BIT(0),
QED_LM_Autoneg_BIT = BIT(1),
QED_LM_Asym_Pause_BIT = BIT(2),
QED_LM_Pause_BIT = BIT(3),
QED_LM_1000baseT_Full_BIT = BIT(4),
QED_LM_10000baseT_Full_BIT = BIT(5),
QED_LM_10000baseKR_Full_BIT = BIT(6),
QED_LM_20000baseKR2_Full_BIT = BIT(7),
QED_LM_25000baseKR_Full_BIT = BIT(8),
QED_LM_40000baseLR4_Full_BIT = BIT(9),
QED_LM_50000baseKR2_Full_BIT = BIT(10),
QED_LM_100000baseKR4_Full_BIT = BIT(11),
QED_LM_TP_BIT = BIT(12),
QED_LM_Backplane_BIT = BIT(13),
QED_LM_1000baseKX_Full_BIT = BIT(14),
QED_LM_10000baseKX4_Full_BIT = BIT(15),
QED_LM_10000baseR_FEC_BIT = BIT(16),
QED_LM_40000baseKR4_Full_BIT = BIT(17),
QED_LM_40000baseCR4_Full_BIT = BIT(18),
QED_LM_40000baseSR4_Full_BIT = BIT(19),
QED_LM_25000baseCR_Full_BIT = BIT(20),
QED_LM_25000baseSR_Full_BIT = BIT(21),
QED_LM_50000baseCR2_Full_BIT = BIT(22),
QED_LM_100000baseSR4_Full_BIT = BIT(23),
QED_LM_100000baseCR4_Full_BIT = BIT(24),
QED_LM_100000baseLR4_ER4_Full_BIT = BIT(25),
QED_LM_50000baseSR2_Full_BIT = BIT(26),
QED_LM_1000baseX_Full_BIT = BIT(27),
QED_LM_10000baseCR_Full_BIT = BIT(28),
QED_LM_10000baseSR_Full_BIT = BIT(29),
QED_LM_10000baseLR_Full_BIT = BIT(30),
QED_LM_10000baseLRM_Full_BIT = BIT(31),
QED_LM_COUNT = 32
};
struct qed_link_params { struct qed_link_params {
bool link_up; bool link_up;
...@@ -708,7 +672,9 @@ struct qed_link_params { ...@@ -708,7 +672,9 @@ struct qed_link_params {
#define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5) #define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5)
u32 override_flags; u32 override_flags;
bool autoneg; bool autoneg;
u32 adv_speeds;
__ETHTOOL_DECLARE_LINK_MODE_MASK(adv_speeds);
u32 forced_speed; u32 forced_speed;
#define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0) #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0)
#define QED_LINK_PAUSE_RX_ENABLE BIT(1) #define QED_LINK_PAUSE_RX_ENABLE BIT(1)
...@@ -726,10 +692,9 @@ struct qed_link_params { ...@@ -726,10 +692,9 @@ struct qed_link_params {
struct qed_link_output { struct qed_link_output {
bool link_up; bool link_up;
/* In QED_LM_* defs */ __ETHTOOL_DECLARE_LINK_MODE_MASK(supported_caps);
u32 supported_caps; __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised_caps);
u32 advertised_caps; __ETHTOOL_DECLARE_LINK_MODE_MASK(lp_caps);
u32 lp_caps;
u32 speed; /* In Mb/s */ u32 speed; /* In Mb/s */
u8 duplex; /* In DUPLEX defs */ u8 duplex; /* In DUPLEX defs */
......
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