arm64: dts: freescale: add missing cache properties

As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:

  fsl-ls2080a-simu.dtb: l2-cache3: 'cache-unified' is a required property
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

@@ -47,6 +47,7 @@ cpu1: cpu@1 {
 		l2: l2-cache {
 			compatible = "cache";
 			cache-level = <2>;
+			cache-unified;
 		};
 	};
 

arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi

@@ -85,6 +85,7 @@ cpu3: cpu@3 {
 		l2: l2-cache {
 			compatible = "cache";
 			cache-level = <2>;
+			cache-unified;
 		};
 	};
 

arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi

@@ -80,6 +80,7 @@ cpu3: cpu@3 {
 		l2: l2-cache {
 			compatible = "cache";
 			cache-level = <2>;
+			cache-unified;
 		};
 	};
 

arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi

@@ -96,21 +96,25 @@ cpu7: cpu@301 {
 	cluster0_l2: l2-cache0 {
 		compatible = "cache";
 		cache-level = <2>;
+		cache-unified;
 	};
 
 	cluster1_l2: l2-cache1 {
 		compatible = "cache";
 		cache-level = <2>;
+		cache-unified;
 	};
 
 	cluster2_l2: l2-cache2 {
 		compatible = "cache";
 		cache-level = <2>;
+		cache-unified;
 	};
 
 	cluster3_l2: l2-cache3 {
 		compatible = "cache";
 		cache-level = <2>;
+		cache-unified;
 	};
 
 	CPU_PW20: cpu-pw20 {

arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi

@@ -96,21 +96,25 @@ cpu7: cpu@301 {
 	cluster0_l2: l2-cache0 {
 		compatible = "cache";
 		cache-level = <2>;
+		cache-unified;
 	};
 
 	cluster1_l2: l2-cache1 {
 		compatible = "cache";
 		cache-level = <2>;
+		cache-unified;
 	};
 
 	cluster2_l2: l2-cache2 {
 		compatible = "cache";
 		cache-level = <2>;
+		cache-unified;
 	};
 
 	cluster3_l2: l2-cache3 {
 		compatible = "cache";
 		cache-level = <2>;
+		cache-unified;
 	};
 
 	CPU_PW20: cpu-pw20 {