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Commit ce63eb7d authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'samsung-dt64-4.16' of... 

Merge tag 'samsung-dt64-4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt

Pull "Samsung DTS ARM64 changes for v4.16" from Krzysztof Kozłowski:

1. Add CPU perf counters to Exynos5433.
2. Add missing power domains to Exynos5433.
3. Add NFC chip to Exynos5433 TM2/TM2E.
4. Fix obscure bugs on I2C transfers to MHL chip on TM2/TM2E.

* tag 'samsung-dt64-4.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: dts: exynos: Increase bus frequency for MHL chip
  arm64: dts: exynos: Add remaining power domains to Exynos5433 SoC
  arm64: dts: exynos: Add AUD power domain to Exynos5433 SoC
  arm64: dts: exynos: Add MFC power domain to Exynos 5433 SoC
  arm64: dts: exynos: Add MSCL power domain to Exynos 5433 SoC
  arm64: dts: exynos: Add DISP power domain to Exynos 5433 SoC
  arm64: dts: exynos: Add GSCL power domain to Exynos 5433 SoC
  arm64: dts: exynos: Add support for S3FWRN5 NFC chip to TM2(e) boards
  arm64: dts: exynos: Add CPU performance counters to Exynos5433 boards
parents cb5a94a4 38083547
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arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
View file @ ce63eb7d
......@@ -741,6 +741,19 @@ buck10_reg: BUCK10 {
};
};
&hsi2c_4 {
status = "okay";
s3fwrn5: nfc@27 {
compatible = "samsung,s3fwrn5-i2c";
reg = <0x27>;
interrupt-parent = <&gpa1>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
s3fwrn5,en-gpios = <&gpf1 4 GPIO_ACTIVE_HIGH>;
s3fwrn5,fw-gpios = <&gpj0 2 GPIO_ACTIVE_HIGH>;
};
};
&hsi2c_5 {
status = "okay";
......@@ -756,6 +769,7 @@ stmfts: touchscreen@49 {
&hsi2c_7 {
status = "okay";
clock-frequency = <1000000>;
sii8620@39 {
reg = <0x39>;
......
arch/arm64/boot/dts/exynos/exynos5433.dtsi
View file @ ce63eb7d
......@@ -247,6 +247,24 @@ soc: soc {
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x18000000>;
arm_a53_pmu {
compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
arm_a57_pmu {
compatible = "arm,cortex-a57-pmu", "arm,armv8-pmuv3";
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
};
chipid@10000000 {
compatible = "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
......@@ -343,6 +361,7 @@ cmu_g2d: clock-controller@12460000 {
clocks = <&xxti>,
<&cmu_top CLK_ACLK_G2D_266>,
<&cmu_top CLK_ACLK_G2D_400>;
power-domains = <&pd_g2d>;
};
cmu_disp: clock-controller@13b90000 {
......@@ -368,6 +387,7 @@ cmu_disp: clock-controller@13b90000 {
<&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
<&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
<&cmu_mif CLK_ACLK_DISP_333>;
power-domains = <&pd_disp>;
};
cmu_aud: clock-controller@114c0000 {
......@@ -376,6 +396,7 @@ cmu_aud: clock-controller@114c0000 {
#clock-cells = <1>;
clock-names = "oscclk", "fout_aud_pll";
clocks = <&xxti>, <&cmu_top CLK_FOUT_AUD_PLL>;
power-domains = <&pd_aud>;
};
cmu_bus0: clock-controller@13600000 {
......@@ -412,6 +433,7 @@ cmu_g3d: clock-controller@14aa0000 {
clock-names = "oscclk", "aclk_g3d_400";
clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
power-domains = <&pd_g3d>;
};
cmu_gscl: clock-controller@13cf0000 {
......@@ -425,6 +447,7 @@ cmu_gscl: clock-controller@13cf0000 {
clocks = <&xxti>,
<&cmu_top CLK_ACLK_GSCL_111>,
<&cmu_top CLK_ACLK_GSCL_333>;
power-domains = <&pd_gscl>;
};
cmu_apollo: clock-controller@11900000 {
......@@ -456,6 +479,7 @@ cmu_mscl: clock-controller@105d0000 {
clocks = <&xxti>,
<&cmu_top CLK_SCLK_JPEG_MSCL>,
<&cmu_top CLK_ACLK_MSCL_400>;
power-domains = <&pd_mscl>;
};
cmu_mfc: clock-controller@15280000 {
......@@ -465,6 +489,7 @@ cmu_mfc: clock-controller@15280000 {
clock-names = "oscclk", "aclk_mfc_400";
clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
power-domains = <&pd_mfc>;
};
cmu_hevc: clock-controller@14f80000 {
......@@ -474,6 +499,7 @@ cmu_hevc: clock-controller@14f80000 {
clock-names = "oscclk", "aclk_hevc_400";
clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
power-domains = <&pd_hevc>;
};
cmu_isp: clock-controller@146d0000 {
......@@ -487,6 +513,7 @@ cmu_isp: clock-controller@146d0000 {
clocks = <&xxti>,
<&cmu_top CLK_ACLK_ISP_DIS_400>,
<&cmu_top CLK_ACLK_ISP_400>;
power-domains = <&pd_isp>;
};
cmu_cam0: clock-controller@120d0000 {
......@@ -502,6 +529,7 @@ cmu_cam0: clock-controller@120d0000 {
<&cmu_top CLK_ACLK_CAM0_333>,
<&cmu_top CLK_ACLK_CAM0_400>,
<&cmu_top CLK_ACLK_CAM0_552>;
power-domains = <&pd_cam0>;
};
cmu_cam1: clock-controller@145d0000 {
......@@ -523,6 +551,86 @@ cmu_cam1: clock-controller@145d0000 {
<&cmu_top CLK_ACLK_CAM1_333>,
<&cmu_top CLK_ACLK_CAM1_400>,
<&cmu_top CLK_ACLK_CAM1_552>;
power-domains = <&pd_cam1>;
};
pd_gscl: power-domain@105c4000 {
compatible = "samsung,exynos5433-pd";
reg = <0x105c4000 0x20>;
#power-domain-cells = <0>;
label = "GSCL";
};
pd_cam0: power-domain@105c4020 {
compatible = "samsung,exynos5433-pd";
reg = <0x105c4020 0x20>;
#power-domain-cells = <0>;
power-domains = <&pd_cam1>;
label = "CAM0";
};
pd_mscl: power-domain@105c4040 {
compatible = "samsung,exynos5433-pd";
reg = <0x105c4040 0x20>;
#power-domain-cells = <0>;
label = "MSCL";
};
pd_g3d: power-domain@105c4060 {
compatible = "samsung,exynos5433-pd";
reg = <0x105c4060 0x20>;
#power-domain-cells = <0>;
label = "G3D";
};
pd_disp: power-domain@105c4080 {
compatible = "samsung,exynos5433-pd";
reg = <0x105c4080 0x20>;
#power-domain-cells = <0>;
label = "DISP";
};
pd_cam1: power-domain@105c40a0 {
compatible = "samsung,exynos5433-pd";
reg = <0x105c40a0 0x20>;
#power-domain-cells = <0>;
label = "CAM1";
};
pd_aud: power-domain@105c40c0 {
compatible = "samsung,exynos5433-pd";
reg = <0x105c40c0 0x20>;
#power-domain-cells = <0>;
label = "AUD";
};
pd_g2d: power-domain@105c4120 {
compatible = "samsung,exynos5433-pd";
reg = <0x105c4120 0x20>;
#power-domain-cells = <0>;
label = "G2D";
};
pd_isp: power-domain@105c4140 {
compatible = "samsung,exynos5433-pd";
reg = <0x105c4140 0x20>;
#power-domain-cells = <0>;
power-domains = <&pd_cam0>;
label = "ISP";
};
pd_mfc: power-domain@105c4180 {
compatible = "samsung,exynos5433-pd";
reg = <0x105c4180 0x20>;
#power-domain-cells = <0>;
label = "MFC";
};
pd_hevc: power-domain@105c41c0 {
compatible = "samsung,exynos5433-pd";
reg = <0x105c41c0 0x20>;
#power-domain-cells = <0>;
label = "HEVC";
};
tmu_atlas0: tmu@10060000 {
......@@ -637,6 +745,7 @@ pinctrl_aud: pinctrl@114b0000 {
compatible = "samsung,exynos5433-pinctrl";
reg = <0x114b0000 0x1000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_aud>;
};
pinctrl_cpif: pinctrl@10fe0000 {
......@@ -728,6 +837,7 @@ decon: decon@13800000 {
clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
"aclk_xiu_decon0x", "pclk_smmu_decon0x",
"sclk_decon_vclk", "sclk_decon_eclk";
power-domains = <&pd_disp>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
......@@ -765,6 +875,7 @@ decon_tv: decon@13880000 {
"aclk_xiu_decon0x", "pclk_smmu_decon0x",
"sclk_decon_vclk", "sclk_decon_eclk";
samsung,disp-sysreg = <&syscon_disp>;
power-domains = <&pd_disp>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
......@@ -790,6 +901,7 @@ dsi: dsi@13900000 {
"phyclk_mipidphy0_rxclkesc0",
"sclk_rgb_vclk_to_dsim0",
"sclk_mipi";
power-domains = <&pd_disp>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
......@@ -813,6 +925,7 @@ mic: mic@13930000 {
clocks = <&cmu_disp CLK_PCLK_MIC0>,
<&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
power-domains = <&pd_disp>;
samsung,disp-syscon = <&syscon_disp>;
status = "disabled";
......@@ -892,6 +1005,7 @@ gsc_0: video-scaler@13C00000 {
<&cmu_gscl CLK_ACLK_XIU_GSCLX>,
<&cmu_gscl CLK_ACLK_GSCLBEND_333>;
iommus = <&sysmmu_gscl0>;
power-domains = <&pd_gscl>;
};
gsc_1: video-scaler@13C10000 {
......@@ -905,6 +1019,7 @@ gsc_1: video-scaler@13C10000 {
<&cmu_gscl CLK_ACLK_XIU_GSCLX>,
<&cmu_gscl CLK_ACLK_GSCLBEND_333>;
iommus = <&sysmmu_gscl1>;
power-domains = <&pd_gscl>;
};
gsc_2: video-scaler@13C20000 {
......@@ -918,6 +1033,7 @@ gsc_2: video-scaler@13C20000 {
<&cmu_gscl CLK_ACLK_XIU_GSCLX>,
<&cmu_gscl CLK_ACLK_GSCLBEND_333>;
iommus = <&sysmmu_gscl2>;
power-domains = <&pd_gscl>;
};
jpeg: codec@15020000 {
......@@ -930,6 +1046,7 @@ jpeg: codec@15020000 {
<&cmu_mscl CLK_ACLK_XIU_MSCLX>,
<&cmu_mscl CLK_SCLK_JPEG>;
iommus = <&sysmmu_jpeg>;
power-domains = <&pd_mscl>;
};
mfc: codec@152E0000 {
......@@ -942,6 +1059,7 @@ mfc: codec@152E0000 {
<&cmu_mfc CLK_ACLK_XIU_MFCX>;
iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
iommu-names = "left", "right";
power-domains = <&pd_mfc>;
};
sysmmu_decon0x: sysmmu@13a00000 {
......@@ -951,6 +1069,7 @@ sysmmu_decon0x: sysmmu@13a00000 {
clock-names = "pclk", "aclk";
clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
<&cmu_disp CLK_ACLK_SMMU_DECON0X>;
power-domains = <&pd_disp>;
#iommu-cells = <0>;
};
......@@ -962,6 +1081,7 @@ sysmmu_decon1x: sysmmu@13a10000 {
clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
<&cmu_disp CLK_ACLK_SMMU_DECON1X>;
#iommu-cells = <0>;
power-domains = <&pd_disp>;
};
sysmmu_tv0x: sysmmu@13a20000 {
......@@ -972,6 +1092,7 @@ sysmmu_tv0x: sysmmu@13a20000 {
clocks = <&cmu_disp CLK_PCLK_SMMU_TV0X>,
<&cmu_disp CLK_ACLK_SMMU_TV0X>;
#iommu-cells = <0>;
power-domains = <&pd_disp>;
};
sysmmu_tv1x: sysmmu@13a30000 {
......@@ -982,6 +1103,7 @@ sysmmu_tv1x: sysmmu@13a30000 {
clocks = <&cmu_disp CLK_PCLK_SMMU_TV1X>,
<&cmu_disp CLK_ACLK_SMMU_TV1X>;
#iommu-cells = <0>;
power-domains = <&pd_disp>;
};
sysmmu_gscl0: sysmmu@13c80000 {
......@@ -992,6 +1114,7 @@ sysmmu_gscl0: sysmmu@13c80000 {
clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>,
<&cmu_gscl CLK_PCLK_SMMU_GSCL0>;
#iommu-cells = <0>;
power-domains = <&pd_gscl>;
};
sysmmu_gscl1: sysmmu@13c90000 {
......@@ -1002,6 +1125,7 @@ sysmmu_gscl1: sysmmu@13c90000 {
clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>,
<&cmu_gscl CLK_PCLK_SMMU_GSCL1>;
#iommu-cells = <0>;
power-domains = <&pd_gscl>;
};
sysmmu_gscl2: sysmmu@13ca0000 {
......@@ -1012,6 +1136,7 @@ sysmmu_gscl2: sysmmu@13ca0000 {
clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>,
<&cmu_gscl CLK_PCLK_SMMU_GSCL2>;
#iommu-cells = <0>;
power-domains = <&pd_gscl>;
};
sysmmu_jpeg: sysmmu@15060000 {
......@@ -1022,6 +1147,7 @@ sysmmu_jpeg: sysmmu@15060000 {
clocks = <&cmu_mscl CLK_PCLK_SMMU_JPEG>,
<&cmu_mscl CLK_ACLK_SMMU_JPEG>;
#iommu-cells = <0>;
power-domains = <&pd_mscl>;
};
sysmmu_mfc_0: sysmmu@15200000 {
......@@ -1032,6 +1158,7 @@ sysmmu_mfc_0: sysmmu@15200000 {
clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>,
<&cmu_mfc CLK_ACLK_SMMU_MFC_0>;
#iommu-cells = <0>;
power-domains = <&pd_mfc>;
};
sysmmu_mfc_1: sysmmu@15210000 {
......@@ -1042,6 +1169,7 @@ sysmmu_mfc_1: sysmmu@15210000 {
clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>,
<&cmu_mfc CLK_ACLK_SMMU_MFC_1>;
#iommu-cells = <0>;
power-domains = <&pd_mfc>;
};
serial_0: serial@14c10000 {
......@@ -1497,6 +1625,7 @@ audio-subsystem@11400000 {
clocks = <&cmu_aud CLK_PCLK_SFR0_CTRL>;
clock-names = "sfr0_ctrl";
samsung,pmu-syscon = <&pmu_system_controller>;
power-domains = <&pd_aud>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
......@@ -1510,6 +1639,7 @@ adma: adma@11420000 {
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
power-domains = <&pd_aud>;
};
i2s0: i2s0@11440000 {
......@@ -1526,6 +1656,7 @@ i2s0: i2s0@11440000 {
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
power-domains = <&pd_aud>;
status = "disabled";
};
......@@ -1538,6 +1669,7 @@ serial_3: serial@11460000 {
clock-names = "uart", "clk_uart_baud0";
pinctrl-names = "default";
pinctrl-0 = <&uart_aud_bus>;
power-domains = <&pd_aud>;
status = "disabled";
};
};
......
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