Commit d639af62 authored by Mark Bloch's avatar Mark Bloch Committed by Saeed Mahameed

net/mlx5: fs, split software and IFC flow destination definitions

Separate flow destinations between software and IFC.
Flow destination type passed by callers was used as the input in
firmware commands and over the years software only types were added
which resulted in mixing between the two.

Create an IFC enum that contains only the flow destinations defined
when talking to the firmware.

Now that there is a proper software only enum for flow destinations
the hardcoded values can be removed as the values are no longer used
in firmware commands.
Signed-off-by: default avatarMark Bloch <mbloch@nvidia.com>
Reviewed-by: default avatarMaor Gottlieb <maorg@nvidia.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
parent c70c3336
...@@ -571,7 +571,9 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev, ...@@ -571,7 +571,9 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev,
int list_size = 0; int list_size = 0;
list_for_each_entry(dst, &fte->node.children, node.list) { list_for_each_entry(dst, &fte->node.children, node.list) {
unsigned int id, type = dst->dest_attr.type; enum mlx5_flow_destination_type type = dst->dest_attr.type;
enum mlx5_ifc_flow_destination_type ifc_type;
unsigned int id;
if (type == MLX5_FLOW_DESTINATION_TYPE_COUNTER) if (type == MLX5_FLOW_DESTINATION_TYPE_COUNTER)
continue; continue;
...@@ -579,10 +581,11 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev, ...@@ -579,10 +581,11 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev,
switch (type) { switch (type) {
case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM: case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM:
id = dst->dest_attr.ft_num; id = dst->dest_attr.ft_num;
type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; ifc_type = MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE;
break; break;
case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE: case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE:
id = dst->dest_attr.ft->id; id = dst->dest_attr.ft->id;
ifc_type = MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE;
break; break;
case MLX5_FLOW_DESTINATION_TYPE_UPLINK: case MLX5_FLOW_DESTINATION_TYPE_UPLINK:
case MLX5_FLOW_DESTINATION_TYPE_VPORT: case MLX5_FLOW_DESTINATION_TYPE_VPORT:
...@@ -596,8 +599,10 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev, ...@@ -596,8 +599,10 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev,
if (type == MLX5_FLOW_DESTINATION_TYPE_UPLINK) { if (type == MLX5_FLOW_DESTINATION_TYPE_UPLINK) {
/* destination_id is reserved */ /* destination_id is reserved */
id = 0; id = 0;
ifc_type = MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK;
break; break;
} }
ifc_type = MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT;
id = dst->dest_attr.vport.num; id = dst->dest_attr.vport.num;
if (extended_dest && if (extended_dest &&
dst->dest_attr.vport.pkt_reformat) { dst->dest_attr.vport.pkt_reformat) {
...@@ -612,13 +617,15 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev, ...@@ -612,13 +617,15 @@ static int mlx5_cmd_set_fte(struct mlx5_core_dev *dev,
break; break;
case MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER: case MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER:
id = dst->dest_attr.sampler_id; id = dst->dest_attr.sampler_id;
ifc_type = MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER;
break; break;
default: default:
id = dst->dest_attr.tir_num; id = dst->dest_attr.tir_num;
ifc_type = MLX5_IFC_FLOW_DESTINATION_TYPE_TIR;
} }
MLX5_SET(dest_format_struct, in_dests, destination_type, MLX5_SET(dest_format_struct, in_dests, destination_type,
type); ifc_type);
MLX5_SET(dest_format_struct, in_dests, destination_id, id); MLX5_SET(dest_format_struct, in_dests, destination_id, id);
in_dests += dst_cnt_size; in_dests += dst_cnt_size;
list_size++; list_size++;
......
...@@ -311,7 +311,7 @@ int mlx5dr_cmd_set_fte_modify_and_vport(struct mlx5_core_dev *mdev, ...@@ -311,7 +311,7 @@ int mlx5dr_cmd_set_fte_modify_and_vport(struct mlx5_core_dev *mdev,
in_dests = MLX5_ADDR_OF(flow_context, in_flow_context, destination); in_dests = MLX5_ADDR_OF(flow_context, in_flow_context, destination);
MLX5_SET(dest_format_struct, in_dests, destination_type, MLX5_SET(dest_format_struct, in_dests, destination_type,
MLX5_FLOW_DESTINATION_TYPE_VPORT); MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT);
MLX5_SET(dest_format_struct, in_dests, destination_id, vport); MLX5_SET(dest_format_struct, in_dests, destination_id, vport);
err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out)); err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
...@@ -719,7 +719,9 @@ int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev, ...@@ -719,7 +719,9 @@ int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev,
int list_size = 0; int list_size = 0;
for (i = 0; i < fte->dests_size; i++) { for (i = 0; i < fte->dests_size; i++) {
unsigned int id, type = fte->dest_arr[i].type; enum mlx5_flow_destination_type type = fte->dest_arr[i].type;
enum mlx5_ifc_flow_destination_type ifc_type;
unsigned int id;
if (type == MLX5_FLOW_DESTINATION_TYPE_COUNTER) if (type == MLX5_FLOW_DESTINATION_TYPE_COUNTER)
continue; continue;
...@@ -727,10 +729,12 @@ int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev, ...@@ -727,10 +729,12 @@ int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev,
switch (type) { switch (type) {
case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM: case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM:
id = fte->dest_arr[i].ft_num; id = fte->dest_arr[i].ft_num;
type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE; ifc_type = MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE;
break; break;
case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE: case MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE:
id = fte->dest_arr[i].ft_id; id = fte->dest_arr[i].ft_id;
ifc_type = MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE;
break; break;
case MLX5_FLOW_DESTINATION_TYPE_UPLINK: case MLX5_FLOW_DESTINATION_TYPE_UPLINK:
case MLX5_FLOW_DESTINATION_TYPE_VPORT: case MLX5_FLOW_DESTINATION_TYPE_VPORT:
...@@ -740,8 +744,10 @@ int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev, ...@@ -740,8 +744,10 @@ int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev,
destination_eswitch_owner_vhca_id_valid, destination_eswitch_owner_vhca_id_valid,
!!(fte->dest_arr[i].vport.flags & !!(fte->dest_arr[i].vport.flags &
MLX5_FLOW_DEST_VPORT_VHCA_ID)); MLX5_FLOW_DEST_VPORT_VHCA_ID));
ifc_type = MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT;
} else { } else {
id = 0; id = 0;
ifc_type = MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK;
MLX5_SET(dest_format_struct, in_dests, MLX5_SET(dest_format_struct, in_dests,
destination_eswitch_owner_vhca_id_valid, 1); destination_eswitch_owner_vhca_id_valid, 1);
} }
...@@ -761,13 +767,15 @@ int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev, ...@@ -761,13 +767,15 @@ int mlx5dr_cmd_set_fte(struct mlx5_core_dev *dev,
break; break;
case MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER: case MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER:
id = fte->dest_arr[i].sampler_id; id = fte->dest_arr[i].sampler_id;
ifc_type = MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER;
break; break;
default: default:
id = fte->dest_arr[i].tir_num; id = fte->dest_arr[i].tir_num;
ifc_type = MLX5_IFC_FLOW_DESTINATION_TYPE_TIR;
} }
MLX5_SET(dest_format_struct, in_dests, destination_type, MLX5_SET(dest_format_struct, in_dests, destination_type,
type); ifc_type);
MLX5_SET(dest_format_struct, in_dests, destination_id, id); MLX5_SET(dest_format_struct, in_dests, destination_id, id);
in_dests += dst_cnt_size; in_dests += dst_cnt_size;
list_size++; list_size++;
......
...@@ -40,6 +40,17 @@ ...@@ -40,6 +40,17 @@
#define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v) #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
enum mlx5_flow_destination_type {
MLX5_FLOW_DESTINATION_TYPE_VPORT,
MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE,
MLX5_FLOW_DESTINATION_TYPE_TIR,
MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER,
MLX5_FLOW_DESTINATION_TYPE_UPLINK,
MLX5_FLOW_DESTINATION_TYPE_PORT,
MLX5_FLOW_DESTINATION_TYPE_COUNTER,
MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM,
};
enum { enum {
MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO = 1 << 16, MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO = 1 << 16,
MLX5_FLOW_CONTEXT_ACTION_ENCRYPT = 1 << 17, MLX5_FLOW_CONTEXT_ACTION_ENCRYPT = 1 << 17,
......
...@@ -1806,16 +1806,12 @@ struct mlx5_ifc_cmd_hca_cap_2_bits { ...@@ -1806,16 +1806,12 @@ struct mlx5_ifc_cmd_hca_cap_2_bits {
u8 reserved_at_c0[0x740]; u8 reserved_at_c0[0x740];
}; };
enum mlx5_flow_destination_type { enum mlx5_ifc_flow_destination_type {
MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0,
MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2,
MLX5_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
MLX5_FLOW_DESTINATION_TYPE_UPLINK = 0x8, MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8,
MLX5_FLOW_DESTINATION_TYPE_PORT = 0x99,
MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM = 0x101,
}; };
enum mlx5_flow_table_miss_action { enum mlx5_flow_table_miss_action {
......
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