Commit d6d14854 authored by Michal Wajdeczko's avatar Michal Wajdeczko Committed by Rodrigo Vivi

drm/xe: Add device flag to indicate SR-IOV support

The Single Root I/O Virtualization (SR-IOV) extension to
the PCI Express (PCIe) specification suite is supported
starting from 12th generation of Intel Graphics processors.

Add a device flag that we will use to enable SR-IOV specific
code paths and to indicate our readiness to support SR-IOV.

We will enable this flag for the specific platforms once all
required changes and additions will be ready and merged.

Bspec: 52391
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20231115073804.1861-1-michal.wajdeczko@intel.comSigned-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent 8bfbe174
...@@ -158,6 +158,11 @@ static inline bool xe_device_has_flat_ccs(struct xe_device *xe) ...@@ -158,6 +158,11 @@ static inline bool xe_device_has_flat_ccs(struct xe_device *xe)
return xe->info.has_flat_ccs; return xe->info.has_flat_ccs;
} }
static inline bool xe_device_has_sriov(struct xe_device *xe)
{
return xe->info.has_sriov;
}
u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size); u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size);
#endif #endif
...@@ -253,6 +253,8 @@ struct xe_device { ...@@ -253,6 +253,8 @@ struct xe_device {
u8 has_llc:1; u8 has_llc:1;
/** @has_range_tlb_invalidation: Has range based TLB invalidations */ /** @has_range_tlb_invalidation: Has range based TLB invalidations */
u8 has_range_tlb_invalidation:1; u8 has_range_tlb_invalidation:1;
/** @has_sriov: Supports SR-IOV */
u8 has_sriov:1;
/** @enable_display: display enabled */ /** @enable_display: display enabled */
u8 enable_display:1; u8 enable_display:1;
/** @bypass_mtcfg: Bypass Multi-Tile configuration from MTCFG register */ /** @bypass_mtcfg: Bypass Multi-Tile configuration from MTCFG register */
......
...@@ -60,6 +60,7 @@ struct xe_device_desc { ...@@ -60,6 +60,7 @@ struct xe_device_desc {
u8 has_heci_gscfi:1; u8 has_heci_gscfi:1;
u8 has_llc:1; u8 has_llc:1;
u8 has_sriov:1;
u8 bypass_mtcfg:1; u8 bypass_mtcfg:1;
u8 supports_mmio_ext:1; u8 supports_mmio_ext:1;
}; };
...@@ -531,7 +532,6 @@ static void handle_gmdid(struct xe_device *xe, ...@@ -531,7 +532,6 @@ static void handle_gmdid(struct xe_device *xe,
} }
} }
static int xe_info_init(struct xe_device *xe, static int xe_info_init(struct xe_device *xe,
const struct xe_device_desc *desc, const struct xe_device_desc *desc,
const struct xe_subplatform_desc *subplatform_desc) const struct xe_subplatform_desc *subplatform_desc)
...@@ -577,6 +577,7 @@ static int xe_info_init(struct xe_device *xe, ...@@ -577,6 +577,7 @@ static int xe_info_init(struct xe_device *xe,
xe->info.graphics_name = graphics_desc->name; xe->info.graphics_name = graphics_desc->name;
xe->info.media_name = media_desc ? media_desc->name : "none"; xe->info.media_name = media_desc ? media_desc->name : "none";
xe->info.has_llc = desc->has_llc; xe->info.has_llc = desc->has_llc;
xe->info.has_sriov = desc->has_sriov;
xe->info.bypass_mtcfg = desc->bypass_mtcfg; xe->info.bypass_mtcfg = desc->bypass_mtcfg;
xe->info.supports_mmio_ext = desc->supports_mmio_ext; xe->info.supports_mmio_ext = desc->supports_mmio_ext;
xe->info.tile_mmio_ext_size = graphics_desc->tile_mmio_ext_size; xe->info.tile_mmio_ext_size = graphics_desc->tile_mmio_ext_size;
......
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