Commit da2d072a authored by Shiju Jose's avatar Shiju Jose Committed by David S. Miller

net: hns3: Add enable and process hw errors from PPP

This patch enables and process hw errors from the
PPP(Programmable Packet Process) block.
Signed-off-by: default avatarShiju Jose <shiju.jose@huawei.com>
Signed-off-by: default avatarSalil Mehta <salil.mehta@huawei.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent bf1faf94
...@@ -218,6 +218,8 @@ enum hclge_opcode_type { ...@@ -218,6 +218,8 @@ enum hclge_opcode_type {
HCLGE_IGU_COMMON_INT_QUERY = 0x1805, HCLGE_IGU_COMMON_INT_QUERY = 0x1805,
HCLGE_IGU_COMMON_INT_EN = 0x1806, HCLGE_IGU_COMMON_INT_EN = 0x1806,
HCLGE_IGU_COMMON_INT_CLR = 0x1807, HCLGE_IGU_COMMON_INT_CLR = 0x1807,
HCLGE_PPP_CMD0_INT_CMD = 0x2100,
HCLGE_PPP_CMD1_INT_CMD = 0x2101,
HCLGE_NCSI_INT_QUERY = 0x2400, HCLGE_NCSI_INT_QUERY = 0x2400,
HCLGE_NCSI_INT_EN = 0x2401, HCLGE_NCSI_INT_EN = 0x2401,
HCLGE_NCSI_INT_CLR = 0x2402, HCLGE_NCSI_INT_CLR = 0x2402,
......
...@@ -27,6 +27,16 @@ ...@@ -27,6 +27,16 @@
#define HCLGE_IGU_ERR_INT_EN_MASK 0x000F #define HCLGE_IGU_ERR_INT_EN_MASK 0x000F
#define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF #define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF
#define HCLGE_IGU_TNL_ERR_INT_EN_MASK 0x003F #define HCLGE_IGU_TNL_ERR_INT_EN_MASK 0x003F
#define HCLGE_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF
#define HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF
#define HCLGE_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF
#define HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF
#define HCLGE_PPP_PF_ERR_INT_EN 0x0003
#define HCLGE_PPP_PF_ERR_INT_EN_MASK 0x0003
#define HCLGE_PPP_MPF_ECC_ERR_INT2_EN 0x003F
#define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F
#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN 0x003F
#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F
#define HCLGE_NCSI_ERR_INT_EN 0x3 #define HCLGE_NCSI_ERR_INT_EN 0x3
#define HCLGE_NCSI_ERR_INT_TYPE 0x9 #define HCLGE_NCSI_ERR_INT_TYPE 0x9
...@@ -43,6 +53,7 @@ ...@@ -43,6 +53,7 @@
#define HCLGE_TQP_IMP_ERR_CLR_MASK 0x0FFF0001 #define HCLGE_TQP_IMP_ERR_CLR_MASK 0x0FFF0001
#define HCLGE_IGU_COM_INT_MASK 0xF #define HCLGE_IGU_COM_INT_MASK 0xF
#define HCLGE_IGU_EGU_TNL_INT_MASK 0x3F #define HCLGE_IGU_EGU_TNL_INT_MASK 0x3F
#define HCLGE_PPP_PF_INT_MASK 0x100
enum hclge_err_int_type { enum hclge_err_int_type {
HCLGE_ERR_INT_MSIX = 0, HCLGE_ERR_INT_MSIX = 0,
......
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