Commit e50bf7a6 authored by Abel Vesa's avatar Abel Vesa Committed by Shawn Guo

clk: imx: Remove unused clk based API

Now that the i.MX6 and i.MX7 clock drivers have been switched to clk_hw based,
we can remove the clk based API that is not used by any i.MX clock driver.

The following APIs are going away now:
- imx_clk_busy_divider
- imx_clk_busy_mux
- imx_clk_fixup_divider
- imx_clk_fixup_mux
- imx_clk_mux_ldb
- imx_clk_gate_dis_flags
- imx_clk_gate_flags
Signed-off-by: default avatarAbel Vesa <abel.vesa@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 0d381f4c
...@@ -51,12 +51,6 @@ struct imx_pll14xx_clk { ...@@ -51,12 +51,6 @@ struct imx_pll14xx_clk {
int flags; int flags;
}; };
#define imx_clk_busy_divider(name, parent_name, reg, shift, width, busy_reg, busy_shift) \
imx_clk_hw_busy_divider(name, parent_name, reg, shift, width, busy_reg, busy_shift)->clk
#define imx_clk_busy_mux(name, reg, shift, width, busy_reg, busy_shift, parent_names, num_parents) \
imx_clk_hw_busy_mux(name, reg, shift, width, busy_reg, busy_shift, parent_names, num_parents)->clk
#define imx_clk_cpu(name, parent_name, div, mux, pll, step) \ #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \
imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)->clk imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)->clk
...@@ -74,15 +68,6 @@ struct imx_pll14xx_clk { ...@@ -74,15 +68,6 @@ struct imx_pll14xx_clk {
#define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \ #define imx_clk_gate_exclusive(name, parent, reg, shift, exclusive_mask) \
imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask)->clk imx_clk_hw_gate_exclusive(name, parent, reg, shift, exclusive_mask)->clk
#define imx_clk_fixup_divider(name, parent, reg, shift, width, fixup) \
imx_clk_hw_fixup_divider(name, parent, reg, shift, width, fixup)->clk
#define imx_clk_fixup_mux(name, reg, shift, width, parents, num_parents, fixup) \
imx_clk_hw_fixup_mux(name, reg, shift, width, parents, num_parents, fixup)->clk
#define imx_clk_mux_ldb(name, reg, shift, width, parents, num_parents) \
imx_clk_hw_mux_ldb(name, reg, shift, width, parents, num_parents)->clk
#define imx_clk_fixed_factor(name, parent, mult, div) \ #define imx_clk_fixed_factor(name, parent, mult, div) \
imx_clk_hw_fixed_factor(name, parent, mult, div)->clk imx_clk_hw_fixed_factor(name, parent, mult, div)->clk
...@@ -92,21 +77,12 @@ struct imx_pll14xx_clk { ...@@ -92,21 +77,12 @@ struct imx_pll14xx_clk {
#define imx_clk_gate_dis(name, parent, reg, shift) \ #define imx_clk_gate_dis(name, parent, reg, shift) \
imx_clk_hw_gate_dis(name, parent, reg, shift)->clk imx_clk_hw_gate_dis(name, parent, reg, shift)->clk
#define imx_clk_gate_dis_flags(name, parent, reg, shift, flags) \
imx_clk_hw_gate_dis_flags(name, parent, reg, shift, flags)->clk
#define imx_clk_gate_flags(name, parent, reg, shift, flags) \
imx_clk_hw_gate_flags(name, parent, reg, shift, flags)->clk
#define imx_clk_gate2(name, parent, reg, shift) \ #define imx_clk_gate2(name, parent, reg, shift) \
imx_clk_hw_gate2(name, parent, reg, shift)->clk imx_clk_hw_gate2(name, parent, reg, shift)->clk
#define imx_clk_gate2_flags(name, parent, reg, shift, flags) \ #define imx_clk_gate2_flags(name, parent, reg, shift, flags) \
imx_clk_hw_gate2_flags(name, parent, reg, shift, flags)->clk imx_clk_hw_gate2_flags(name, parent, reg, shift, flags)->clk
#define imx_clk_gate2_shared(name, parent, reg, shift, share_count) \
imx_clk_hw_gate2_shared(name, parent, reg, shift, share_count)->clk
#define imx_clk_gate2_shared2(name, parent, reg, shift, share_count) \ #define imx_clk_gate2_shared2(name, parent, reg, shift, share_count) \
imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count)->clk imx_clk_hw_gate2_shared2(name, parent, reg, shift, share_count)->clk
......
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