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Commit eb5a1b89 authored by Linus Torvalds's avatar Linus Torvalds
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Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk 

into ppc970.osdl.org:/home/torvalds/v2.6/linux
parents b3b9be04 d2c04833
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arch/arm/kernel/entry-armv.S
View file @ eb5a1b89
...@@ -23,1000 +23,6 @@ ...@@ -23,1000 +23,6 @@
#include "entry-header.S" #include "entry-header.S"
#ifdef IOC_BASE
/* IOC / IOMD based hardware */
#include <asm/hardware/iomd.h>
.equ ioc_base_high, IOC_BASE & 0xff000000
.equ ioc_base_low, IOC_BASE & 0x00ff0000
.macro disable_fiq
mov r12, #ioc_base_high
.if ioc_base_low
orr r12, r12, #ioc_base_low
.endif
strb r12, [r12, #0x38] @ Disable FIQ register
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov r4, #ioc_base_high @ point at IOC
.if ioc_base_low
orr r4, r4, #ioc_base_low
.endif
ldrb \irqstat, [r4, #IOMD_IRQREQB] @ get high priority first
ldr \base, =irq_prio_h
teq \irqstat, #0
#ifdef IOMD_BASE
ldreqb \irqstat, [r4, #IOMD_DMAREQ] @ get dma
addeq \base, \base, #256 @ irq_prio_h table size
teqeq \irqstat, #0
bne 2406f
#endif
ldreqb \irqstat, [r4, #IOMD_IRQREQA] @ get low priority
addeq \base, \base, #256 @ irq_prio_d table size
teqeq \irqstat, #0
#ifdef IOMD_IRQREQC
ldreqb \irqstat, [r4, #IOMD_IRQREQC]
addeq \base, \base, #256 @ irq_prio_l table size
teqeq \irqstat, #0
#endif
#ifdef IOMD_IRQREQD
ldreqb \irqstat, [r4, #IOMD_IRQREQD]
addeq \base, \base, #256 @ irq_prio_lc table size
teqeq \irqstat, #0
#endif
2406: ldrneb \irqnr, [\base, \irqstat] @ get IRQ number
.endm
/*
* Interrupt table (incorporates priority). Please note that we
* rely on the order of these tables (see above code).
*/
.macro irq_prio_table
irq_prio_h: .byte 0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10
.byte 12, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10
.byte 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
.byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
.byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
#ifdef IOMD_BASE
irq_prio_d: .byte 0,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 20,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
#endif
irq_prio_l: .byte 0, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3
.byte 4, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3
.byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
.byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
.byte 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3
.byte 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3
.byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
.byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
#ifdef IOMD_IRQREQC
irq_prio_lc: .byte 24,24,25,24,26,26,26,26,27,27,27,27,27,27,27,27
.byte 28,24,25,24,26,26,26,26,27,27,27,27,27,27,27,27
.byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
.byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
.byte 30,30,30,30,30,30,30,30,27,27,27,27,27,27,27,27
.byte 30,30,30,30,30,30,30,30,27,27,27,27,27,27,27,27
.byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
.byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
#endif
#ifdef IOMD_IRQREQD
irq_prio_ld: .byte 40,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43
.byte 44,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43
.byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
.byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
.byte 46,46,46,46,46,46,46,46,43,43,43,43,43,43,43,43
.byte 46,46,46,46,46,46,46,46,43,43,43,43,43,43,43,43
.byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
.byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
#endif
.endm
#elif defined(CONFIG_ARCH_EBSA110)
#define IRQ_STAT 0xff000000 /* read */
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, stat, base, tmp
mov \base, #IRQ_STAT
ldrb \stat, [\base] @ get interrupts
mov \irqnr, #0
tst \stat, #15
addeq \irqnr, \irqnr, #4
moveq \stat, \stat, lsr #4
tst \stat, #3
addeq \irqnr, \irqnr, #2
moveq \stat, \stat, lsr #2
tst \stat, #1
addeq \irqnr, \irqnr, #1
moveq \stat, \stat, lsr #1
tst \stat, #1 @ bit 0 should be set
.endm
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_SHARK)
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov r4, #0xe0000000
mov \irqstat, #0x0C
strb \irqstat, [r4, #0x20] @outb(0x0C, 0x20) /* Poll command */
ldrb \irqnr, [r4, #0x20] @irq = inb(0x20) & 7
and \irqstat, \irqnr, #0x80
teq \irqstat, #0
beq 43f
and \irqnr, \irqnr, #7
teq \irqnr, #2
bne 44f
43: mov \irqstat, #0x0C
strb \irqstat, [r4, #0xa0] @outb(0x0C, 0xA0) /* Poll command */
ldrb \irqnr, [r4, #0xa0] @irq = (inb(0xA0) & 7) + 8
and \irqstat, \irqnr, #0x80
teq \irqstat, #0
beq 44f
and \irqnr, \irqnr, #7
add \irqnr, \irqnr, #8
44: teq \irqstat, #0
.endm
.macro irq_prio_table
.endm
#elif defined(CONFIG_FOOTBRIDGE)
#include <asm/hardware/dec21285.h>
.macro disable_fiq
.endm
.equ dc21285_high, ARMCSR_BASE & 0xff000000
.equ dc21285_low, ARMCSR_BASE & 0x00ffffff
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov r4, #dc21285_high
.if dc21285_low
orr r4, r4, #dc21285_low
.endif
ldr \irqstat, [r4, #0x180] @ get interrupts
mov \irqnr, #IRQ_SDRAMPARITY
tst \irqstat, #IRQ_MASK_SDRAMPARITY
bne 1001f
tst \irqstat, #IRQ_MASK_UART_RX
movne \irqnr, #IRQ_CONRX
bne 1001f
tst \irqstat, #IRQ_MASK_DMA1
movne \irqnr, #IRQ_DMA1
bne 1001f
tst \irqstat, #IRQ_MASK_DMA2
movne \irqnr, #IRQ_DMA2
bne 1001f
tst \irqstat, #IRQ_MASK_IN0
movne \irqnr, #IRQ_IN0
bne 1001f
tst \irqstat, #IRQ_MASK_IN1
movne \irqnr, #IRQ_IN1
bne 1001f
tst \irqstat, #IRQ_MASK_IN2
movne \irqnr, #IRQ_IN2
bne 1001f
tst \irqstat, #IRQ_MASK_IN3
movne \irqnr, #IRQ_IN3
bne 1001f
tst \irqstat, #IRQ_MASK_PCI
movne \irqnr, #IRQ_PCI
bne 1001f
tst \irqstat, #IRQ_MASK_DOORBELLHOST
movne \irqnr, #IRQ_DOORBELLHOST
bne 1001f
tst \irqstat, #IRQ_MASK_I2OINPOST
movne \irqnr, #IRQ_I2OINPOST
bne 1001f
tst \irqstat, #IRQ_MASK_TIMER1
movne \irqnr, #IRQ_TIMER1
bne 1001f
tst \irqstat, #IRQ_MASK_TIMER2
movne \irqnr, #IRQ_TIMER2
bne 1001f
tst \irqstat, #IRQ_MASK_TIMER3
movne \irqnr, #IRQ_TIMER3
bne 1001f
tst \irqstat, #IRQ_MASK_UART_TX
movne \irqnr, #IRQ_CONTX
bne 1001f
tst \irqstat, #IRQ_MASK_PCI_ABORT
movne \irqnr, #IRQ_PCI_ABORT
bne 1001f
tst \irqstat, #IRQ_MASK_PCI_SERR
movne \irqnr, #IRQ_PCI_SERR
bne 1001f
tst \irqstat, #IRQ_MASK_DISCARD_TIMER
movne \irqnr, #IRQ_DISCARD_TIMER
bne 1001f
tst \irqstat, #IRQ_MASK_PCI_DPERR
movne \irqnr, #IRQ_PCI_DPERR
bne 1001f
tst \irqstat, #IRQ_MASK_PCI_PERR
movne \irqnr, #IRQ_PCI_PERR
1001:
.endm
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_NEXUSPCI)
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, =INTCONT_BASE
ldr \base, =soft_irq_mask
ldr \irqstat, [\irqstat] @ get interrupts
ldr \base, [\base]
mov \irqnr, #0
and \irqstat, \irqstat, \base @ mask out disabled ones
1001: tst \irqstat, #1
addeq \irqnr, \irqnr, #1
moveq \irqstat, \irqstat, lsr #1
tsteq \irqnr, #32
beq 1001b
teq \irqnr, #32
.endm
.macro irq_prio_table
.ltorg
.bss
ENTRY(soft_irq_mask)
.word 0
.text
.endm
#elif defined(CONFIG_ARCH_TBOX)
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, =0xffff7000
ldr \irqstat, [\irqstat] @ get interrupts
ldr \base, =soft_irq_mask
ldr \base, [\base]
mov \irqnr, #0
and \irqstat, \irqstat, \base @ mask out disabled ones
1001: tst \irqstat, #1
addeq \irqnr, \irqnr, #1
moveq \irqstat, \irqstat, lsr #1
tsteq \irqnr, #32
beq 1001b
teq \irqnr, #32
.endm
.macro irq_prio_table
.ltorg
.bss
ENTRY(soft_irq_mask)
.word 0
.text
.endm
#elif defined(CONFIG_ARCH_SA1100)
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov r4, #0xfa000000 @ ICIP = 0xfa050000
add r4, r4, #0x00050000
ldr \irqstat, [r4] @ get irqs
ldr \irqnr, [r4, #4] @ ICMR = 0xfa050004
ands \irqstat, \irqstat, \irqnr
mov \irqnr, #0
beq 1001f
tst \irqstat, #0xff
moveq \irqstat, \irqstat, lsr #8
addeq \irqnr, \irqnr, #8
tsteq \irqstat, #0xff
moveq \irqstat, \irqstat, lsr #8
addeq \irqnr, \irqnr, #8
tsteq \irqstat, #0xff
moveq \irqstat, \irqstat, lsr #8
addeq \irqnr, \irqnr, #8
tst \irqstat, #0x0f
moveq \irqstat, \irqstat, lsr #4
addeq \irqnr, \irqnr, #4
tst \irqstat, #0x03
moveq \irqstat, \irqstat, lsr #2
addeq \irqnr, \irqnr, #2
tst \irqstat, #0x01
addeqs \irqnr, \irqnr, #1
1001:
.endm
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_L7200)
#include <asm/hardware.h>
.equ irq_base_addr, IO_BASE_2
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqstat, #irq_base_addr @ Virt addr IRQ regs
add \irqstat, \irqstat, #0x00001000 @ Status reg
ldr \irqstat, [\irqstat, #0] @ get interrupts
mov \irqnr, #0
1001: tst \irqstat, #1
addeq \irqnr, \irqnr, #1
moveq \irqstat, \irqstat, lsr #1
tsteq \irqnr, #32
beq 1001b
teq \irqnr, #32
.endm
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_INTEGRATOR)
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
/* FIXME: should not be using soo many LDRs here */
ldr \base, =IO_ADDRESS(INTEGRATOR_IC_BASE)
mov \irqnr, #IRQ_PIC_START
ldr \irqstat, [\base, #IRQ_STATUS] @ get masked status
ldr \base, =IO_ADDRESS(INTEGRATOR_HDR_BASE)
teq \irqstat, #0
ldreq \irqstat, [\base, #(INTEGRATOR_HDR_IC_OFFSET+IRQ_STATUS)]
moveq \irqnr, #IRQ_CIC_START
1001: tst \irqstat, #15
bne 1002f
add \irqnr, \irqnr, #4
movs \irqstat, \irqstat, lsr #4
bne 1001b
1002: tst \irqstat, #1
bne 1003f
add \irqnr, \irqnr, #1
movs \irqstat, \irqstat, lsr #1
bne 1002b
1003: /* EQ will be set if no irqs pending */
.endm
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_VERSATILE)
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE)
ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status
mov \irqnr, #0
teq \irqstat, #0
beq 1003f
1001: tst \irqstat, #15
bne 1002f
add \irqnr, \irqnr, #4
movs \irqstat, \irqstat, lsr #4
bne 1001b
1002: tst \irqstat, #1
bne 1003f
add \irqnr, \irqnr, #1
movs \irqstat, \irqstat, lsr #1
bne 1002b
1003: /* EQ will be set if no irqs pending */
@ clz \irqnr, \irqstat
@1003: /* EQ will be set if we reach MAXIRQNUM */
.endm
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_CLPS711X)
#include <asm/hardware/clps7111.h>
.macro disable_fiq
.endm
#if (INTSR2 - INTSR1) != (INTMR2 - INTMR1)
#error INTSR stride != INTMR stride
#endif
.macro get_irqnr_and_base, irqnr, stat, base, mask
mov \base, #CLPS7111_BASE
ldr \stat, [\base, #INTSR1]
ldr \mask, [\base, #INTMR1]
mov \irqnr, #4
mov \mask, \mask, lsl #16
and \stat, \stat, \mask, lsr #16
movs \stat, \stat, lsr #4
bne 1001f
add \base, \base, #INTSR2 - INTSR1
ldr \stat, [\base, #INTSR1]
ldr \mask, [\base, #INTMR1]
mov \irqnr, #16
mov \mask, \mask, lsl #16
and \stat, \stat, \mask, lsr #16
1001: tst \stat, #255
addeq \irqnr, \irqnr, #8
moveq \stat, \stat, lsr #8
tst \stat, #15
addeq \irqnr, \irqnr, #4
moveq \stat, \stat, lsr #4
tst \stat, #3
addeq \irqnr, \irqnr, #2
moveq \stat, \stat, lsr #2
tst \stat, #1
addeq \irqnr, \irqnr, #1
moveq \stat, \stat, lsr #1
tst \stat, #1 @ bit 0 should be set
.endm
.macro irq_prio_table
.endm
#elif defined (CONFIG_ARCH_CAMELOT)
#include <asm/arch/platform.h>
#undef IRQ_MODE /* same name defined in asm/proc/ptrace.h */
#include <asm/arch/int_ctrl00.h>
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, =INT_ID(IO_ADDRESS(EXC_INT_CTRL00_BASE))
ldr \irqnr,[\irqstat]
cmp \irqnr,#0
subne \irqnr,\irqnr,#1
.endm
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_IOP321)
.macro disable_fiq
.endm
/*
* Note: only deal with normal interrupts, not FIQ
*/
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqnr, #0
mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC
cmp \irqstat, #0
beq 1001f
clz \irqnr, \irqstat
mov \base, #31
subs \irqnr,\base,\irqnr
add \irqnr,\irqnr,#IRQ_IOP321_DMA0_EOT
1001:
.endm
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_IOP331)
.macro disable_fiq
.endm
/*
* Note: only deal with normal interrupts, not FIQ
*/
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqnr, #0
mrc p6, 0, \irqstat, c4, c0, 0 @ Read IINTSRC0
cmp \irqstat, #0
bne 1002f
mrc p6, 0, \irqstat, c5, c0, 0 @ Read IINTSRC1
cmp \irqstat, #0
beq 1001f
clz \irqnr, \irqstat
/*
* mov \base, #31
* subs \irqnr,\base,\irqnr
*/
rsbs \irqnr,\irqnr,#31 @ recommend by RMK
add \irqnr,\irqnr,#IRQ_IOP331_XINT8
b 1001f
1002: clz \irqnr, \irqstat
mov \base, #31
subs \irqnr,\base,\irqnr
add \irqnr,\irqnr,#IRQ_IOP331_DMA0_EOT
1001:
.endm
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_PXA)
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
#ifdef CONFIG_PXA27x
mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP
mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR
#else
mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000
add \base, \base, #0x00d00000
ldr \irqstat, [\base, #0] @ ICIP
ldr \irqnr, [\base, #4] @ ICMR
#endif
ands \irqnr, \irqstat, \irqnr
beq 1001f
rsb \irqstat, \irqnr, #0
and \irqstat, \irqstat, \irqnr
clz \irqnr, \irqstat
rsb \irqnr, \irqnr, #(31 - PXA_IRQ_SKIP)
1001:
.endm
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_IXP2000)
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqnr, #0x0 @clear out irqnr as default
mov \base, #0xfe000000
orr \base, \base, #0x00ff0000
orr \base, \base, #0x0000a000
orr \base, \base, #0x08
ldr \irqstat, [\base] @ get interrupts
mov \tmp, #IXP2000_VALID_IRQ_MASK & 0xff000000
orr \tmp, \tmp, #IXP2000_VALID_IRQ_MASK & 0x00ff0000
orr \tmp, \tmp, #IXP2000_VALID_IRQ_MASK & 0x0000ff00
orr \tmp, \tmp, #IXP2000_VALID_IRQ_MASK & 0x000000ff
and \irqstat, \irqstat, \tmp
cmp \irqstat, #0
beq 1001f
clz \irqnr, \irqstat
mov \base, #31
subs \irqnr, \base, \irqnr
/*
* We handle PCIA and PCIB here so we don't have an
* extra layer of code just to check these two bits.
*/
cmp \irqnr, #IRQ_IXP2000_PCI
bne 1001f
mov \base, #0xfe000000
orr \base, \base, #0x00fd0000
orr \base, \base, #0x0000e100
orr \base, \base, #0x00000058
ldr \irqstat, [\base]
mov \tmp, #(1<<26)
tst \irqstat, \tmp
movne \irqnr, #IRQ_IXP2000_PCIA
bne 1001f
mov \tmp, #(1<<27)
tst \irqstat, \tmp
movne \irqnr, #IRQ_IXP2000_PCIB
1001:
.endm
.macro irq_prio_table
.endm
#elif defined (CONFIG_ARCH_IXP4XX)
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
ldr \irqstat, [\irqstat] @ get interrupts
cmp \irqstat, #0
beq 1002f
clz \irqnr, \irqstat
mov \base, #31
subs \irqnr, \base, \irqnr
/*
1001: tst \irqstat, #1
addeq \irqnr, \irqnr, #1
moveq \irqstat, \irqstat, lsr #1
tsteq \irqnr, #32
beq 1001b
teq \irqnr, #32
*/
1002:
.endm
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_OMAP)
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =IO_ADDRESS(OMAP_IH1_BASE)
ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET]
mov \irqstat, #0xffffffff
bic \tmp, \irqstat, \tmp
tst \irqnr, \tmp
beq 1510f
ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
cmp \irqnr, #0
ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
cmpeq \irqnr, #INT_IH2_IRQ
ldreq \base, =IO_ADDRESS(OMAP_IH2_BASE)
ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
addeqs \irqnr, \irqnr, #32
1510:
.endm
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_S3C2410)
/* S3C2410X IRQ Handler, <ben@simtec.co.uk> */
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
30000:
mov \tmp, #S3C2410_VA_IRQ
ldr \irqnr, [ \tmp, #0x14 ] @ get irq no
teq \irqnr, #4
teqne \irqnr, #5
beq 1002f @ external irq reg
teq \irqnr, #16
beq 1003f @ lcd controller
@ debug check to see if interrupt reported is the same
@ as the offset....
teq \irqnr, #0
beq 20002f
ldr \irqstat, [ \tmp, #0x10 ] @ INTPND
mov \irqstat, \irqstat, lsr \irqnr
tst \irqstat, #1
bne 20002f
#if 1
stmfd r13!, { r0 - r4 , r14 }
ldr r1, [ \tmp, #0x14 ] @ intoffset
ldr r2, [ \tmp, #0x10 ] @ INTPND
ldr r3, [ \tmp, #0x00 ] @ SRCPND
adr r0, 20003f
bl printk
b 20004f
#endif
20003:
.ascii "<7>irq: err - bad offset %d, intpnd=%08x, srcpnd=%08x\n"
.byte 0
.align 4
20004:
mov r1, #1
mov \tmp, #S3C2410_VA_IRQ
ldmfd r13!, { r0 - r4 , r14 }
@ try working out interript number for ourselves
mov \irqnr, #0
ldr \irqstat, [ \tmp, #0x10 ] @ INTPND
10021:
movs \irqstat, \irqstat, lsr#1
bcs 30000b @ try and re-start the proccess
add \irqnr, \irqnr, #1
cmp \irqnr, #32
ble 10021b
@ found no interrupt, set Z flag and leave
movs \irqnr, #0
b 1001f
20005:
20002: @ exit
@ we base the s3c2410x interrupts at 16 and above to allow
@ isa peripherals to have their standard interrupts, also
@ ensure that Z flag is un-set on exit
@ note, we cannot be sure if we get IRQ_EINT0 (0) that
@ there is simply no interrupt pending, so in all other
@ cases we jump to say we have found something, otherwise
@ we check to see if the interrupt really is assrted
adds \irqnr, \irqnr, #IRQ_EINT0
teq \irqnr, #IRQ_EINT0
bne 1001f @ exit
ldr \irqstat, [ \tmp, #0x10 ] @ INTPND
teq \irqstat, #0
moveq \irqnr, #0
b 1001f
@ we get here from no main or external interrupts pending
1002:
add \tmp, \tmp, #S3C2410_VA_GPIO - S3C2410_VA_IRQ
ldr \irqstat, [ \tmp, # 0xa8 ] @ EXTINTPEND
ldr \irqnr, [ \tmp, # 0xa4 ] @ EXTINTMASK
bic \irqstat, \irqstat, \irqnr @ clear masked irqs
mov \irqnr, #IRQ_EINT4 @ start extint nos
mov \irqstat, \irqstat, lsr#4 @ ignore bottom 4 bits
10021:
movs \irqstat, \irqstat, lsr#1
bcs 1004f
add \irqnr, \irqnr, #1
cmp \irqnr, #IRQ_EINT23
ble 10021b
@ found no interrupt, set Z flag and leave
movs \irqnr, #0
b 1001f
1003:
@ lcd interrupt has been asserted...
add \tmp, \tmp, #S3C2410_VA_LCD - S3C2410_VA_IRQ
ldr \irqstat, [ \tmp, # 0x54 ] @ lcd int pending
tst \irqstat, #2
movne \irqnr, #IRQ_LCD_FRAME
tst \irqstat, #1
movne \irqnr, #IRQ_LCD_FIFO
@ fall through to exit with flags updated
1004: @ ensure Z flag clear in case our MOVS shifted out the last bit
teq \irqnr, #0
1001:
@ exit irq routine
.endm
/* currently don't need an disable_fiq macro */
.macro disable_fiq
.endm
/* we don't have an irq priority table */
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_LH7A400)
# if defined (CONFIG_ARCH_LH7A404)
# error "LH7A400 and LH7A404 are mutually exclusive"
# endif
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqnr, #0
mov \base, #io_p2v(0x80000000) @ APB registers
ldr \irqstat, [\base, #0x500] @ PIC INTSR
1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
bcs 1008f @ Bit set; irq found
add \irqnr, \irqnr, #1
bne 1001b @ Until no bits
b 1009f @ Nothing? Hmm.
1008: movs \irqstat, #1 @ Force !Z
1009:
.endm
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_LH7A404)
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqnr, #0 @ VIC1 irq base
mov \base, #io_p2v(0x80000000) @ APB registers
add \base, \base, #0x8000
ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR
tst \tmp, #VA_VECTORED @ Direct vectored
bne 1002f
tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1
ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS
bne 1001f
add \base, \base, #(0xa000 - 0x8000)
ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR
tst \tmp, #VA_VECTORED @ Direct vectored
bne 1002f
ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS
mov \irqnr, #32 @ VIC2 irq base
1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
bcs 1008f @ Bit set; irq found
add \irqnr, \irqnr, #1
bne 1001b @ Until no bits
b 1009f @ Nothing? Hmm.
1002: and \irqnr, \tmp, #0x3f @ Mask for valid bits
1008: movs \irqstat, #1 @ Force !Z
str \tmp, [\base, #0x0030] @ Clear vector
1009:
.endm
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_IMX)
.macro disable_fiq
.endm
#define AITC_NIVECSR 0x40
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, =IO_ADDRESS(IMX_AITC_BASE)
@ Load offset & priority of the highest priority
@ interrupt pending.
ldr \irqnr, [\irqstat, #AITC_NIVECSR]
@ Shift off the priority leaving the offset or
@ "interrupt number"
mov \irqnr, \irqnr, lsr #16
ldr \irqstat, =1 @ dummy compare
ldr \base, =0xFFFF // invalid interrupt
cmp \irqnr, \base
bne 1001f
ldr \irqstat, =0
1001:
tst \irqstat, #1 @ to make the condition code = TRUE
.endm
.macro irq_prio_table
.endm
#elif defined(CONFIG_ARCH_H720X)
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
#if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202)
@ we could use the id register on H7202, but this is not
@ properly updated when we come back from asm_do_irq
@ without a previous return from interrupt
@ (see loops below in irq_svc, irq_usr)
@ We see unmasked pending ints only, as the masked pending ints
@ are not visible here
mov \base, #0xf0000000 @ base register
orr \base, \base, #0x24000 @ irqbase
ldr \irqstat, [\base, #0x04] @ get interrupt status
#if defined (CONFIG_CPU_H7201)
ldr \tmp, =0x001fffff
#else
mvn \tmp, #0xc0000000
#endif
and \irqstat, \irqstat, \tmp @ mask out unused ints
mov \irqnr, #0
mov \tmp, #0xff00
orr \tmp, \tmp, #0xff
tst \irqstat, \tmp
addeq \irqnr, \irqnr, #16
moveq \irqstat, \irqstat, lsr #16
tst \irqstat, #255
addeq \irqnr, \irqnr, #8
moveq \irqstat, \irqstat, lsr #8
tst \irqstat, #15
addeq \irqnr, \irqnr, #4
moveq \irqstat, \irqstat, lsr #4
tst \irqstat, #3
addeq \irqnr, \irqnr, #2
moveq \irqstat, \irqstat, lsr #2
tst \irqstat, #1
addeq \irqnr, \irqnr, #1
moveq \irqstat, \irqstat, lsr #1
tst \irqstat, #1 @ bit 0 should be set
.endm
.macro irq_prio_table
.endm
#else
#error hynix processor selection missmatch
#endif
#else
#error Unknown architecture
#endif
/* /*
* Invalid mode handlers * Invalid mode handlers
*/ */
...@@ -1196,8 +202,6 @@ __pabt_svc: sub sp, sp, #S_FRAME_SIZE ...@@ -1196,8 +202,6 @@ __pabt_svc: sub sp, sp, #S_FRAME_SIZE
.LCirq_stat: .word irq_stat .LCirq_stat: .word irq_stat
#endif #endif
irq_prio_table
/* /*
* User mode handlers * User mode handlers
*/ */
......
arch/arm/kernel/entry-header.S
View file @ eb5a1b89
...@@ -6,6 +6,7 @@ ...@@ -6,6 +6,7 @@
#include <asm/errno.h> #include <asm/errno.h>
#include <asm/hardware.h> #include <asm/hardware.h>
#include <asm/arch/irqs.h> #include <asm/arch/irqs.h>
#include <asm/arch/entry-macro.S>
#ifndef MODE_SVC #ifndef MODE_SVC
#define MODE_SVC 0x13 #define MODE_SVC 0x13
......
arch/arm/mm/Kconfig
View file @ eb5a1b89
...@@ -82,9 +82,9 @@ config CPU_ARM920T ...@@ -82,9 +82,9 @@ config CPU_ARM920T
# ARM922T # ARM922T
config CPU_ARM922T config CPU_ARM922T
bool bool "Support ARM922T processor" if ARCH_INTEGRATOR
depends on ARCH_CAMELOT || ARCH_LH7A40X depends on ARCH_CAMELOT || ARCH_LH7A40X || ARCH_INTEGRATOR
default y default y if ARCH_CAMELOT || ARCH_LH7A40X
select CPU_32v4 select CPU_32v4
select CPU_ABRT_EV4T select CPU_ABRT_EV4T
select CPU_CACHE_V4WT select CPU_CACHE_V4WT
......
drivers/char/watchdog/Kconfig
View file @ eb5a1b89
...@@ -93,6 +93,11 @@ config IXP4XX_WATCHDOG ...@@ -93,6 +93,11 @@ config IXP4XX_WATCHDOG
be built as a module by choosing M. The module will be built as a module by choosing M. The module will
be called ixp4xx_wdt. be called ixp4xx_wdt.
Note: The internal IXP4xx watchdog does a soft CPU reset
which doesn't reset any peripherals. There are circumstances
where the watchdog will fail to reset the board correctly
(e.g., if the boot ROM is in an unreadable state).
Say N if you are unsure. Say N if you are unsure.
config IXP2000_WATCHDOG config IXP2000_WATCHDOG
......
include/asm-arm/arch-cl7500/entry-macro.S 0 → 100644
View file @ eb5a1b89
#include <asm/hardware/entry-macro-iomd.S>
include/asm-arm/arch-clps711x/entry-macro.S 0 → 100644
View file @ eb5a1b89
/*
* include/asm-arm/arch-CLPS711x/entry-macro.S
*
* Low-level IRQ helper macros for CLPS711X-based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware/clps7111.h>
.macro disable_fiq
.endm
#if (INTSR2 - INTSR1) != (INTMR2 - INTMR1)
#error INTSR stride != INTMR stride
#endif
.macro get_irqnr_and_base, irqnr, stat, base, mask
mov \base, #CLPS7111_BASE
ldr \stat, [\base, #INTSR1]
ldr \mask, [\base, #INTMR1]
mov \irqnr, #4
mov \mask, \mask, lsl #16
and \stat, \stat, \mask, lsr #16
movs \stat, \stat, lsr #4
bne 1001f
add \base, \base, #INTSR2 - INTSR1
ldr \stat, [\base, #INTSR1]
ldr \mask, [\base, #INTMR1]
mov \irqnr, #16
mov \mask, \mask, lsl #16
and \stat, \stat, \mask, lsr #16
1001: tst \stat, #255
addeq \irqnr, \irqnr, #8
moveq \stat, \stat, lsr #8
tst \stat, #15
addeq \irqnr, \irqnr, #4
moveq \stat, \stat, lsr #4
tst \stat, #3
addeq \irqnr, \irqnr, #2
moveq \stat, \stat, lsr #2
tst \stat, #1
addeq \irqnr, \irqnr, #1
moveq \stat, \stat, lsr #1
tst \stat, #1 @ bit 0 should be set
.endm
include/asm-arm/arch-ebsa110/entry-macro.S 0 → 100644
View file @ eb5a1b89
/*
* include/asm-arm/arch-ebsa110/entry-macro.S
*
* Low-level IRQ helper macros for ebsa110 platform.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#define IRQ_STAT 0xff000000 /* read */
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, stat, base, tmp
mov \base, #IRQ_STAT
ldrb \stat, [\base] @ get interrupts
mov \irqnr, #0
tst \stat, #15
addeq \irqnr, \irqnr, #4
moveq \stat, \stat, lsr #4
tst \stat, #3
addeq \irqnr, \irqnr, #2
moveq \stat, \stat, lsr #2
tst \stat, #1
addeq \irqnr, \irqnr, #1
moveq \stat, \stat, lsr #1
tst \stat, #1 @ bit 0 should be set
.endm
include/asm-arm/arch-ebsa285/entry-macro.S 0 → 100644
View file @ eb5a1b89
/*
* include/asm-arm/arch-footbridge/entry-macro.S
*
* Low-level IRQ helper macros for footbridge-based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware/dec21285.h>
.macro disable_fiq
.endm
.equ dc21285_high, ARMCSR_BASE & 0xff000000
.equ dc21285_low, ARMCSR_BASE & 0x00ffffff
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov r4, #dc21285_high
.if dc21285_low
orr r4, r4, #dc21285_low
.endif
ldr \irqstat, [r4, #0x180] @ get interrupts
mov \irqnr, #IRQ_SDRAMPARITY
tst \irqstat, #IRQ_MASK_SDRAMPARITY
bne 1001f
tst \irqstat, #IRQ_MASK_UART_RX
movne \irqnr, #IRQ_CONRX
bne 1001f
tst \irqstat, #IRQ_MASK_DMA1
movne \irqnr, #IRQ_DMA1
bne 1001f
tst \irqstat, #IRQ_MASK_DMA2
movne \irqnr, #IRQ_DMA2
bne 1001f
tst \irqstat, #IRQ_MASK_IN0
movne \irqnr, #IRQ_IN0
bne 1001f
tst \irqstat, #IRQ_MASK_IN1
movne \irqnr, #IRQ_IN1
bne 1001f
tst \irqstat, #IRQ_MASK_IN2
movne \irqnr, #IRQ_IN2
bne 1001f
tst \irqstat, #IRQ_MASK_IN3
movne \irqnr, #IRQ_IN3
bne 1001f
tst \irqstat, #IRQ_MASK_PCI
movne \irqnr, #IRQ_PCI
bne 1001f
tst \irqstat, #IRQ_MASK_DOORBELLHOST
movne \irqnr, #IRQ_DOORBELLHOST
bne 1001f
tst \irqstat, #IRQ_MASK_I2OINPOST
movne \irqnr, #IRQ_I2OINPOST
bne 1001f
tst \irqstat, #IRQ_MASK_TIMER1
movne \irqnr, #IRQ_TIMER1
bne 1001f
tst \irqstat, #IRQ_MASK_TIMER2
movne \irqnr, #IRQ_TIMER2
bne 1001f
tst \irqstat, #IRQ_MASK_TIMER3
movne \irqnr, #IRQ_TIMER3
bne 1001f
tst \irqstat, #IRQ_MASK_UART_TX
movne \irqnr, #IRQ_CONTX
bne 1001f
tst \irqstat, #IRQ_MASK_PCI_ABORT
movne \irqnr, #IRQ_PCI_ABORT
bne 1001f
tst \irqstat, #IRQ_MASK_PCI_SERR
movne \irqnr, #IRQ_PCI_SERR
bne 1001f
tst \irqstat, #IRQ_MASK_DISCARD_TIMER
movne \irqnr, #IRQ_DISCARD_TIMER
bne 1001f
tst \irqstat, #IRQ_MASK_PCI_DPERR
movne \irqnr, #IRQ_PCI_DPERR
bne 1001f
tst \irqstat, #IRQ_MASK_PCI_PERR
movne \irqnr, #IRQ_PCI_PERR
1001:
.endm
include/asm-arm/arch-epxa10db/entry-macro.S 0 → 100644
View file @ eb5a1b89
/*
* include/asm-arm/arch-epxa10db/entry-macro.S
*
* Low-level IRQ helper macros for epxa10db platform
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/arch/platform.h>
#undef IRQ_MODE /* same name defined in asm/proc/ptrace.h */
#include <asm/arch/int_ctrl00.h>
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, =INT_ID(IO_ADDRESS(EXC_INT_CTRL00_BASE))
ldr \irqnr,[\irqstat]
cmp \irqnr,#0
subne \irqnr,\irqnr,#1
.endm
include/asm-arm/arch-h720x/entry-macro.S 0 → 100644
View file @ eb5a1b89
/*
* include/asm-arm/arch-h720x/entry-macro.S
*
* Low-level IRQ helper macros for Hynix HMS720x based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
#if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202)
@ we could use the id register on H7202, but this is not
@ properly updated when we come back from asm_do_irq
@ without a previous return from interrupt
@ (see loops below in irq_svc, irq_usr)
@ We see unmasked pending ints only, as the masked pending ints
@ are not visible here
mov \base, #0xf0000000 @ base register
orr \base, \base, #0x24000 @ irqbase
ldr \irqstat, [\base, #0x04] @ get interrupt status
#if defined (CONFIG_CPU_H7201)
ldr \tmp, =0x001fffff
#else
mvn \tmp, #0xc0000000
#endif
and \irqstat, \irqstat, \tmp @ mask out unused ints
mov \irqnr, #0
mov \tmp, #0xff00
orr \tmp, \tmp, #0xff
tst \irqstat, \tmp
addeq \irqnr, \irqnr, #16
moveq \irqstat, \irqstat, lsr #16
tst \irqstat, #255
addeq \irqnr, \irqnr, #8
moveq \irqstat, \irqstat, lsr #8
tst \irqstat, #15
addeq \irqnr, \irqnr, #4
moveq \irqstat, \irqstat, lsr #4
tst \irqstat, #3
addeq \irqnr, \irqnr, #2
moveq \irqstat, \irqstat, lsr #2
tst \irqstat, #1
addeq \irqnr, \irqnr, #1
moveq \irqstat, \irqstat, lsr #1
tst \irqstat, #1 @ bit 0 should be set
.endm
.macro irq_prio_table
.endm
#else
#error hynix processor selection missmatch
#endif
include/asm-arm/arch-imx/entry-macro.S 0 → 100644
View file @ eb5a1b89
/*
* include/asm-arm/arch-imx/entry-macro.S
*
* Low-level IRQ helper macros for iMX-based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
.macro disable_fiq
.endm
#define AITC_NIVECSR 0x40
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, =IO_ADDRESS(IMX_AITC_BASE)
@ Load offset & priority of the highest priority
@ interrupt pending.
ldr \irqnr, [\irqstat, #AITC_NIVECSR]
@ Shift off the priority leaving the offset or
@ "interrupt number"
mov \irqnr, \irqnr, lsr #16
ldr \irqstat, =1 @ dummy compare
ldr \base, =0xFFFF // invalid interrupt
cmp \irqnr, \base
bne 1001f
ldr \irqstat, =0
1001:
tst \irqstat, #1 @ to make the condition code = TRUE
.endm
include/asm-arm/arch-integrator/entry-macro.S 0 → 100644
View file @ eb5a1b89
/*
* include/asm-arm/arch-integrator/entry-macro.S
*
* Low-level IRQ helper macros for Integrator platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
/* FIXME: should not be using soo many LDRs here */
ldr \base, =IO_ADDRESS(INTEGRATOR_IC_BASE)
mov \irqnr, #IRQ_PIC_START
ldr \irqstat, [\base, #IRQ_STATUS] @ get masked status
ldr \base, =IO_ADDRESS(INTEGRATOR_HDR_BASE)
teq \irqstat, #0
ldreq \irqstat, [\base, #(INTEGRATOR_HDR_IC_OFFSET+IRQ_STATUS)]
moveq \irqnr, #IRQ_CIC_START
1001: tst \irqstat, #15
bne 1002f
add \irqnr, \irqnr, #4
movs \irqstat, \irqstat, lsr #4
bne 1001b
1002: tst \irqstat, #1
bne 1003f
add \irqnr, \irqnr, #1
movs \irqstat, \irqstat, lsr #1
bne 1002b
1003: /* EQ will be set if no irqs pending */
.endm
include/asm-arm/arch-iop3xx/entry-macro.S 0 → 100644
View file @ eb5a1b89
/*
* include/asm-arm/arch-iop3xx/entry-macro.S
*
* Low-level IRQ helper macros for IOP3xx-based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#if defined(CONFIG_ARCH_IOP321)
.macro disable_fiq
.endm
/*
* Note: only deal with normal interrupts, not FIQ
*/
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqnr, #0
mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC
cmp \irqstat, #0
beq 1001f
clz \irqnr, \irqstat
mov \base, #31
subs \irqnr,\base,\irqnr
add \irqnr,\irqnr,#IRQ_IOP321_DMA0_EOT
1001:
.endm
#elif defined(CONFIG_ARCH_IOP331)
.macro disable_fiq
.endm
/*
* Note: only deal with normal interrupts, not FIQ
*/
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqnr, #0
mrc p6, 0, \irqstat, c4, c0, 0 @ Read IINTSRC0
cmp \irqstat, #0
bne 1002f
mrc p6, 0, \irqstat, c5, c0, 0 @ Read IINTSRC1
cmp \irqstat, #0
beq 1001f
clz \irqnr, \irqstat
/*
* mov \base, #31
* subs \irqnr,\base,\irqnr
*/
rsbs \irqnr,\irqnr,#31 @ recommend by RMK
add \irqnr,\irqnr,#IRQ_IOP331_XINT8
b 1001f
1002: clz \irqnr, \irqstat
mov \base, #31
subs \irqnr,\base,\irqnr
add \irqnr,\irqnr,#IRQ_IOP331_DMA0_EOT
1001:
.endm
#endif
include/asm-arm/arch-ixp2000/entry-macro.S 0 → 100644
View file @ eb5a1b89
/*
* include/asm-arm/arch-ixp2000/entry-macro.S
*
* Low-level IRQ helper macros for IXP2000-based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqnr, #0x0 @clear out irqnr as default
mov \base, #0xfe000000
orr \base, \base, #0x00ff0000
orr \base, \base, #0x0000a000
orr \base, \base, #0x08
ldr \irqstat, [\base] @ get interrupts
mov \tmp, #IXP2000_VALID_IRQ_MASK & 0xff000000
orr \tmp, \tmp, #IXP2000_VALID_IRQ_MASK & 0x00ff0000
orr \tmp, \tmp, #IXP2000_VALID_IRQ_MASK & 0x0000ff00
orr \tmp, \tmp, #IXP2000_VALID_IRQ_MASK & 0x000000ff
and \irqstat, \irqstat, \tmp
cmp \irqstat, #0
beq 1001f
clz \irqnr, \irqstat
mov \base, #31
subs \irqnr, \base, \irqnr
/*
* We handle PCIA and PCIB here so we don't have an
* extra layer of code just to check these two bits.
*/
cmp \irqnr, #IRQ_IXP2000_PCI
bne 1001f
mov \base, #0xfe000000
orr \base, \base, #0x00fd0000
orr \base, \base, #0x0000e100
orr \base, \base, #0x00000058
ldr \irqstat, [\base]
mov \tmp, #(1<<26)
tst \irqstat, \tmp
movne \irqnr, #IRQ_IXP2000_PCIA
bne 1001f
mov \tmp, #(1<<27)
tst \irqstat, \tmp
movne \irqnr, #IRQ_IXP2000_PCIB
1001:
.endm
include/asm-arm/arch-ixp4xx/entry-macro.S 0 → 100644
View file @ eb5a1b89
/*
* include/asm-arm/arch-ixp4xx/entry-macro.S
*
* Low-level IRQ helper macros for IXP4xx-based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
ldr \irqstat, [\irqstat] @ get interrupts
cmp \irqstat, #0
beq 1001f
clz \irqnr, \irqstat
mov \base, #31
subs \irqnr, \base, \irqnr
1001:
.endm
include/asm-arm/arch-l7200/entry-macro.S 0 → 100644
View file @ eb5a1b89
/*
* include/asm-arm/arch-l7200/entry-macro.S
*
* Low-level IRQ helper macros for L7200-based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <asm/hardware.h>
.equ irq_base_addr, IO_BASE_2
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqstat, #irq_base_addr @ Virt addr IRQ regs
add \irqstat, \irqstat, #0x00001000 @ Status reg
ldr \irqstat, [\irqstat, #0] @ get interrupts
mov \irqnr, #0
1001: tst \irqstat, #1
addeq \irqnr, \irqnr, #1
moveq \irqstat, \irqstat, lsr #1
tsteq \irqnr, #32
beq 1001b
teq \irqnr, #32
.endm
include/asm-arm/arch-lh7a40x/entry-macro.S 0 → 100644
View file @ eb5a1b89
/*
* include/asm-arm/arch-lh7a40x/entry-macro.S
*
* Low-level IRQ helper macros for LH7A40x platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
# if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
# error "LH7A400 and LH7A404 are mutually exclusive"
# endif
# if defined (CONFIG_ARCH_LH7A400)
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqnr, #0
mov \base, #io_p2v(0x80000000) @ APB registers
ldr \irqstat, [\base, #0x500] @ PIC INTSR
1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
bcs 1008f @ Bit set; irq found
add \irqnr, \irqnr, #1
bne 1001b @ Until no bits
b 1009f @ Nothing? Hmm.
1008: movs \irqstat, #1 @ Force !Z
1009:
.endm
#elif defined(CONFIG_ARCH_LH7A404)
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov \irqnr, #0 @ VIC1 irq base
mov \base, #io_p2v(0x80000000) @ APB registers
add \base, \base, #0x8000
ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR
tst \tmp, #VA_VECTORED @ Direct vectored
bne 1002f
tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1
ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS
bne 1001f
add \base, \base, #(0xa000 - 0x8000)
ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR
tst \tmp, #VA_VECTORED @ Direct vectored
bne 1002f
ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS
mov \irqnr, #32 @ VIC2 irq base
1001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
bcs 1008f @ Bit set; irq found
add \irqnr, \irqnr, #1
bne 1001b @ Until no bits
b 1009f @ Nothing? Hmm.
1002: and \irqnr, \tmp, #0x3f @ Mask for valid bits
1008: movs \irqstat, #1 @ Force !Z
str \tmp, [\base, #0x0030] @ Clear vector
1009:
.endm
#endif
include/asm-arm/arch-omap/entry-macro.S 0 → 100644
View file @ eb5a1b89
/*
* include/asm-arm/arch-omap/entry-macro.S
*
* Low-level IRQ helper macros for OMAP-based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =IO_ADDRESS(OMAP_IH1_BASE)
ldr \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
ldr \tmp, [\base, #IRQ_MIR_REG_OFFSET]
mov \irqstat, #0xffffffff
bic \tmp, \irqstat, \tmp
tst \irqnr, \tmp
beq 1510f
ldr \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
cmp \irqnr, #0
ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
cmpeq \irqnr, #INT_IH2_IRQ
ldreq \base, =IO_ADDRESS(OMAP_IH2_BASE)
ldreq \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
addeqs \irqnr, \irqnr, #32
1510:
.endm
include/asm-arm/arch-pxa/entry-macro.S 0 → 100644
View file @ eb5a1b89
/*
* include/asm-arm/arch-pxa/entry-macro.S
*
* Low-level IRQ helper macros for PXA-based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
#ifdef CONFIG_PXA27x
mrc p6, 0, \irqstat, c0, c0, 0 @ ICIP
mrc p6, 0, \irqnr, c1, c0, 0 @ ICMR
#else
mov \base, #io_p2v(0x40000000) @ IIR Ctl = 0x40d00000
add \base, \base, #0x00d00000
ldr \irqstat, [\base, #0] @ ICIP
ldr \irqnr, [\base, #4] @ ICMR
#endif
ands \irqnr, \irqstat, \irqnr
beq 1001f
rsb \irqstat, \irqnr, #0
and \irqstat, \irqstat, \irqnr
clz \irqnr, \irqstat
rsb \irqnr, \irqnr, #(31 - PXA_IRQ_SKIP)
1001:
.endm
include/asm-arm/arch-rpc/entry-macro.S 0 → 100644
View file @ eb5a1b89
#include <asm/hardware/entry-macro-iomd.S>
include/asm-arm/arch-s3c2410/entry-macro.S 0 → 100644
View file @ eb5a1b89
/*
* include/asm-arm/arch-s3c2410/entry-macro.S
*
* Low-level IRQ helper macros for S3C2410-based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
30000:
mov \tmp, #S3C2410_VA_IRQ
ldr \irqnr, [ \tmp, #0x14 ] @ get irq no
teq \irqnr, #4
teqne \irqnr, #5
beq 1002f @ external irq reg
teq \irqnr, #16
beq 1003f @ lcd controller
@ debug check to see if interrupt reported is the same
@ as the offset....
teq \irqnr, #0
beq 20002f
ldr \irqstat, [ \tmp, #0x10 ] @ INTPND
mov \irqstat, \irqstat, lsr \irqnr
tst \irqstat, #1
bne 20002f
#if 1
stmfd r13!, { r0 - r4 , r14 }
ldr r1, [ \tmp, #0x14 ] @ intoffset
ldr r2, [ \tmp, #0x10 ] @ INTPND
ldr r3, [ \tmp, #0x00 ] @ SRCPND
adr r0, 20003f
bl printk
b 20004f
#endif
20003:
.ascii "<7>irq: err - bad offset %d, intpnd=%08x, srcpnd=%08x\n"
.byte 0
.align 4
20004:
mov r1, #1
mov \tmp, #S3C2410_VA_IRQ
ldmfd r13!, { r0 - r4 , r14 }
@ try working out interript number for ourselves
mov \irqnr, #0
ldr \irqstat, [ \tmp, #0x10 ] @ INTPND
10021:
movs \irqstat, \irqstat, lsr#1
bcs 30000b @ try and re-start the proccess
add \irqnr, \irqnr, #1
cmp \irqnr, #32
ble 10021b
@ found no interrupt, set Z flag and leave
movs \irqnr, #0
b 1001f
20005:
20002: @ exit
@ we base the s3c2410x interrupts at 16 and above to allow
@ isa peripherals to have their standard interrupts, also
@ ensure that Z flag is un-set on exit
@ note, we cannot be sure if we get IRQ_EINT0 (0) that
@ there is simply no interrupt pending, so in all other
@ cases we jump to say we have found something, otherwise
@ we check to see if the interrupt really is assrted
adds \irqnr, \irqnr, #IRQ_EINT0
teq \irqnr, #IRQ_EINT0
bne 1001f @ exit
ldr \irqstat, [ \tmp, #0x10 ] @ INTPND
teq \irqstat, #0
moveq \irqnr, #0
b 1001f
@ we get here from no main or external interrupts pending
1002:
add \tmp, \tmp, #S3C2410_VA_GPIO - S3C2410_VA_IRQ
ldr \irqstat, [ \tmp, # 0xa8 ] @ EXTINTPEND
ldr \irqnr, [ \tmp, # 0xa4 ] @ EXTINTMASK
bic \irqstat, \irqstat, \irqnr @ clear masked irqs
mov \irqnr, #IRQ_EINT4 @ start extint nos
mov \irqstat, \irqstat, lsr#4 @ ignore bottom 4 bits
10021:
movs \irqstat, \irqstat, lsr#1
bcs 1004f
add \irqnr, \irqnr, #1
cmp \irqnr, #IRQ_EINT23
ble 10021b
@ found no interrupt, set Z flag and leave
movs \irqnr, #0
b 1001f
1003:
@ lcd interrupt has been asserted...
add \tmp, \tmp, #S3C2410_VA_LCD - S3C2410_VA_IRQ
ldr \irqstat, [ \tmp, # 0x54 ] @ lcd int pending
tst \irqstat, #2
movne \irqnr, #IRQ_LCD_FRAME
tst \irqstat, #1
movne \irqnr, #IRQ_LCD_FIFO
@ fall through to exit with flags updated
1004: @ ensure Z flag clear in case our MOVS shifted out the last bit
teq \irqnr, #0
1001:
@ exit irq routine
.endm
/* currently don't need an disable_fiq macro */
.macro disable_fiq
.endm
include/asm-arm/arch-sa1100/entry-macro.S 0 → 100644
View file @ eb5a1b89
/*
* include/asm-arm/arch-sa1100/entry-macro.S
*
* Low-level IRQ helper macros for SA1100-based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov r4, #0xfa000000 @ ICIP = 0xfa050000
add r4, r4, #0x00050000
ldr \irqstat, [r4] @ get irqs
ldr \irqnr, [r4, #4] @ ICMR = 0xfa050004
ands \irqstat, \irqstat, \irqnr
mov \irqnr, #0
beq 1001f
tst \irqstat, #0xff
moveq \irqstat, \irqstat, lsr #8
addeq \irqnr, \irqnr, #8
tsteq \irqstat, #0xff
moveq \irqstat, \irqstat, lsr #8
addeq \irqnr, \irqnr, #8
tsteq \irqstat, #0xff
moveq \irqstat, \irqstat, lsr #8
addeq \irqnr, \irqnr, #8
tst \irqstat, #0x0f
moveq \irqstat, \irqstat, lsr #4
addeq \irqnr, \irqnr, #4
tst \irqstat, #0x03
moveq \irqstat, \irqstat, lsr #2
addeq \irqnr, \irqnr, #2
tst \irqstat, #0x01
addeqs \irqnr, \irqnr, #1
1001:
.endm
include/asm-arm/arch-shark/entry-macro.S 0 → 100644
View file @ eb5a1b89
/*
* include/asm-arm/arch-shark/entry-macro.S
*
* Low-level IRQ helper macros for Shark platform
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov r4, #0xe0000000
mov \irqstat, #0x0C
strb \irqstat, [r4, #0x20] @outb(0x0C, 0x20) /* Poll command */
ldrb \irqnr, [r4, #0x20] @irq = inb(0x20) & 7
and \irqstat, \irqnr, #0x80
teq \irqstat, #0
beq 43f
and \irqnr, \irqnr, #7
teq \irqnr, #2
bne 44f
43: mov \irqstat, #0x0C
strb \irqstat, [r4, #0xa0] @outb(0x0C, 0xA0) /* Poll command */
ldrb \irqnr, [r4, #0xa0] @irq = (inb(0xA0) & 7) + 8
and \irqstat, \irqnr, #0x80
teq \irqstat, #0
beq 44f
and \irqnr, \irqnr, #7
add \irqnr, \irqnr, #8
44: teq \irqstat, #0
.endm
include/asm-arm/arch-versatile/entry-macro.S 0 → 100644
View file @ eb5a1b89
/*
* include/asm-arm/arch-versatile/entry-macro.S
*
* Low-level IRQ helper macros for Versatile platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE)
ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status
mov \irqnr, #0
teq \irqstat, #0
beq 1003f
1001: tst \irqstat, #15
bne 1002f
add \irqnr, \irqnr, #4
movs \irqstat, \irqstat, lsr #4
bne 1001b
1002: tst \irqstat, #1
bne 1003f
add \irqnr, \irqnr, #1
movs \irqstat, \irqstat, lsr #1
bne 1002b
1003: /* EQ will be set if no irqs pending */
@ clz \irqnr, \irqstat
@1003: /* EQ will be set if we reach MAXIRQNUM */
.endm
include/asm-arm/hardware/entry-macro-iomd.S 0 → 100644
View file @ eb5a1b89
/*
* arch/arm/commond/entry-macro-iomd.S
*
* Low-level IRQ helper macros for IOC/IOMD based platforms
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/* IOC / IOMD based hardware */
#include <asm/hardware/iomd.h>
.equ ioc_base_high, IOC_BASE & 0xff000000
.equ ioc_base_low, IOC_BASE & 0x00ff0000
.macro disable_fiq
mov r12, #ioc_base_high
.if ioc_base_low
orr r12, r12, #ioc_base_low
.endif
strb r12, [r12, #0x38] @ Disable FIQ register
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov r4, #ioc_base_high @ point at IOC
.if ioc_base_low
orr r4, r4, #ioc_base_low
.endif
ldrb \irqstat, [r4, #IOMD_IRQREQB] @ get high priority first
ldr \base, =irq_prio_h
teq \irqstat, #0
#ifdef IOMD_BASE
ldreqb \irqstat, [r4, #IOMD_DMAREQ] @ get dma
addeq \base, \base, #256 @ irq_prio_h table size
teqeq \irqstat, #0
bne 2406f
#endif
ldreqb \irqstat, [r4, #IOMD_IRQREQA] @ get low priority
addeq \base, \base, #256 @ irq_prio_d table size
teqeq \irqstat, #0
#ifdef IOMD_IRQREQC
ldreqb \irqstat, [r4, #IOMD_IRQREQC]
addeq \base, \base, #256 @ irq_prio_l table size
teqeq \irqstat, #0
#endif
#ifdef IOMD_IRQREQD
ldreqb \irqstat, [r4, #IOMD_IRQREQD]
addeq \base, \base, #256 @ irq_prio_lc table size
teqeq \irqstat, #0
#endif
2406: ldrneb \irqnr, [\base, \irqstat] @ get IRQ number
.endm
/*
* Interrupt table (incorporates priority). Please note that we
* rely on the order of these tables (see above code).
*/
.align 5
irq_prio_h: .byte 0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10
.byte 12, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10
.byte 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
.byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
.byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
.byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
#ifdef IOMD_BASE
irq_prio_d: .byte 0,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 20,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
.byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
#endif
irq_prio_l: .byte 0, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3
.byte 4, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3
.byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
.byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
.byte 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3
.byte 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3
.byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
.byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
.byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
#ifdef IOMD_IRQREQC
irq_prio_lc: .byte 24,24,25,24,26,26,26,26,27,27,27,27,27,27,27,27
.byte 28,24,25,24,26,26,26,26,27,27,27,27,27,27,27,27
.byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
.byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
.byte 30,30,30,30,30,30,30,30,27,27,27,27,27,27,27,27
.byte 30,30,30,30,30,30,30,30,27,27,27,27,27,27,27,27
.byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
.byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
.byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
#endif
#ifdef IOMD_IRQREQD
irq_prio_ld: .byte 40,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43
.byte 44,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43
.byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
.byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
.byte 46,46,46,46,46,46,46,46,43,43,43,43,43,43,43,43
.byte 46,46,46,46,46,46,46,46,43,43,43,43,43,43,43,43
.byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
.byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
.byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
#endif
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